mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-28 20:43:45 +08:00
aarch64: Add the SME2 dot-product instructions
BFDOT, FDOT and USDOT share the same instruction format. SDOT and UDOT share a different format. SUDOT does not have the multi vector x multi vector forms, since they would be redundant with USDOT.
This commit is contained in:
Richard Sandiford
parent
a8cb21aa06
commit
57e727c77a
3
gas/testsuite/gas/aarch64/sme2-15-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-15-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-15-invalid.s
|
||||
#error_output: sme2-15-invalid.l
|
||||
97
gas/testsuite/gas/aarch64/sme2-15-invalid.l
Normal file
97
gas/testsuite/gas/aarch64/sme2-15-invalid.l
Normal file
@ -0,0 +1,97 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `bfdot 0,{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `bfdot za\.s\[w8,0\],0,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},0'
|
||||
[^ :]+:[0-9]+: Error: missing braces at operand 2 -- `bfdot za\.h\[w8,0\],z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w12,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,-1\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,8\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z1\.h-z2\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[4\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w7,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w12,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,-1\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,8\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z1\.h-z4\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z2\.h-z5\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z3\.h-z6\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[4\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `bfdot za\.s\[w8,0\],{z0-z1},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\.h\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h-z4\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h,z1\.h,z5\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `bfdot za\.s\[w8,0\],{z0-z1},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\[w8,0\],{z0\.h-z1\.h},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w7,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w12,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,-1\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,8\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z1\.h-z2\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z15\.h-z16\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z31\.h,z0\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w7,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfdot za\.s\[w12,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,-1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `bfdot za\.s\[w8,8\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z1\.h-z4\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z2\.h-z5\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfdot za\.s\[w8,0\],{z3\.h-z6\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},{z15\.h-z18\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},{z29\.h,z30\.h,z31\.h,z0\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `bfdot za\.s\[w8,0\],{z0\.h-z2\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z2\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z4\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot za\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfdot za\.s\[w8, 0\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfdot za\.s\[w8,0:0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `bfdot za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `bfdot za\.s\[w8,0:2\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `bfdot za\.s\[w8,0:3\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfdot za\.s\[w8,1:0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `bfdot za\.s\[w8,foo:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `bfdot za\.s\[w8,1:foo\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `bfdot za\.s\[w8,foo:bar\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
87
gas/testsuite/gas/aarch64/sme2-15-invalid.s
Normal file
87
gas/testsuite/gas/aarch64/sme2-15-invalid.s
Normal file
@ -0,0 +1,87 @@
|
||||
bfdot 0, { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], 0, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, 0
|
||||
|
||||
bfdot za.h[w8, 0], z0.h, z0.h
|
||||
bfdot za.h[w8, 0], { z0.h - z1.h }, z0.h
|
||||
|
||||
bfdot za.s[w7, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w12, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, -1], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 8], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z2.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z1.h - z2.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0.h[-1]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0.h[4]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z16.h[0]
|
||||
|
||||
bfdot za.s[w7, 0], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w12, 0], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, -1], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, 8], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z1.h - z4.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z2.h - z5.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z3.h - z6.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z0.h[-1]
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z0.h[4]
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z16.h[0]
|
||||
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0 - z1 }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0[0]
|
||||
bfdot za.h[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.h[w8, 0], { z0.s - z1.s }, z0.s[0]
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z2.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h - z4.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h, z1.h, z2.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h, z1.h, z5.h }, z0.h
|
||||
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z3.h }, z0.h
|
||||
bfdot za[w8, 0], { z0.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0 - z1 }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0
|
||||
bfdot za[w8, 0], { z0.h - z1.h }, z0
|
||||
|
||||
bfdot za.s[w7, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w12, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, -1], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 8], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z1.h - z2.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z15.h - z16.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z31.h, z0.h }
|
||||
|
||||
bfdot za.s[w7, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w12, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, -1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 8], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z1.h - z4.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z2.h - z5.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z3.h - z6.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, { z15.h - z18.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, { z29.h, z30.h, z31.h, z0.h }
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z2.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z2.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z4.h }
|
||||
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
bfdot za[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
|
||||
bfdot za.s[w8, 0:0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0:2], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0:3], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 1:0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, foo:1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 1:foo], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, foo:bar], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
3
gas/testsuite/gas/aarch64/sme2-15-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-15-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-15.s
|
||||
#error_output: sme2-15-noarch.l
|
||||
187
gas/testsuite/gas/aarch64/sme2-15-noarch.l
Normal file
187
gas/testsuite/gas/aarch64/sme2-15-noarch.l
Normal file
@ -0,0 +1,187 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w9,1\],{z4\.h-z7\.h},z10\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `bfdot za\.s\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w9,1\],{z4\.h-z7\.h},z10\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fdot za\.s\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w10,2\],{z14\.b-z15\.b},z13\.b\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z31\.b,z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z31\.b-z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w9,3\],{z21\.b-z22\.b},z9\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z30\.b,z31\.b,z0\.b,z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z30\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z31\.b-z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w10,5\],{z17\.b-z20\.b},z3\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},{Z0\.b-Z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},{Z0\.B-Z1\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z30\.b-z31\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z1\.b},{z30\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w10,1\],{z22\.b-z23\.b},{z18\.b-z19\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},{Z0\.b-Z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},{Z0\.B-Z3\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,7\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z28\.b-z31\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w8,0\],{z0\.b-z3\.b},{z28\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `usdot za\.s\[w11,3\],{z16\.b-z19\.b},{z24\.b-z27\.b}'
|
||||
195
gas/testsuite/gas/aarch64/sme2-15.d
Normal file
195
gas/testsuite/gas/aarch64/sme2-15.d
Normal file
@ -0,0 +1,195 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1501018 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501018 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501018 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501018 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1507018 bfdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c150101f bfdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c15013d8 bfdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f1018 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1501c18 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
|
||||
[^:]+: c15d55da bfdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1509018 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509018 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509018 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509018 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150f018 bfdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150901f bfdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509398 bfdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f9018 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1509c18 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[3\]
|
||||
[^:]+: c15ab899 bfdot za\.s\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[2\]
|
||||
[^:]+: c1201010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1207010 bfdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201017 bfdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c12013d0 bfdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c12013f0 bfdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c12013f0 bfdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c12f1010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c12932b3 bfdot za\.s\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1301010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1307010 bfdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301017 bfdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301390 bfdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c13013d0 bfdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c13013d0 bfdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c13013f0 bfdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c13013f0 bfdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c13f1010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c1335235 bfdot za\.s\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1a01010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a07010 bfdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01017 bfdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a013d0 bfdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1be1010 bfdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1b252d1 bfdot za\.s\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1a11010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a17010 bfdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11017 bfdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11390 bfdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1bd1010 bfdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1b97213 bfdot za\.s\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
[^:]+: c1501008 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501008 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501008 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501008 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1507008 fdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c150100f fdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c15013c8 fdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f1008 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1501c08 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
|
||||
[^:]+: c15d55ca fdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1509008 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509008 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509008 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509008 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150f008 fdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150900f fdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509388 fdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f9008 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1509c08 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[3\]
|
||||
[^:]+: c15ab889 fdot za\.s\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[2\]
|
||||
[^:]+: c1201000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1207000 fdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1201007 fdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c12013c0 fdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c12013e0 fdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c12013e0 fdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c12f1000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c12932a3 fdot za\.s\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1301000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1307000 fdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301007 fdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1301380 fdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c13013c0 fdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c13013c0 fdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c13013e0 fdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c13013e0 fdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c13f1000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c1335225 fdot za\.s\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1a01000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a07000 fdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a01007 fdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1a013c0 fdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1be1000 fdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1b252c1 fdot za\.s\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1a11000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a17000 fdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11007 fdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1a11380 fdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1bd1000 fdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1b97203 fdot za\.s\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
[^:]+: c1501028 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501028 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501028 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501028 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1507028 usdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c150102f usdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c15013e8 usdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f1028 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
|
||||
[^:]+: c1501c28 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
|
||||
[^:]+: c15d55ea usdot za\.s\[w10, 2, vgx2\], {z14\.b-z15\.b}, z13\.b\[1\]
|
||||
[^:]+: c1509028 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509028 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509028 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509028 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150f028 usdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150902f usdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c15093a8 usdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f9028 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
|
||||
[^:]+: c1509c28 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
|
||||
[^:]+: c15ab8a9 usdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
|
||||
[^:]+: c1201408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1207408 usdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c120140f usdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c12017c8 usdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12017e8 usdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12017e8 usdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12f1408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
|
||||
[^:]+: c12936ab usdot za\.s\[w9, 3, vgx2\], {z21\.b-z22\.b}, z9\.b
|
||||
[^:]+: c1301408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1307408 usdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c130140f usdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301788 usdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b
|
||||
[^:]+: c13017c8 usdot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017c8 usdot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017e8 usdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13017e8 usdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13f1408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
|
||||
[^:]+: c133562d usdot za\.s\[w10, 5, vgx4\], {z17\.b-z20\.b}, z3\.b
|
||||
[^:]+: c1a01408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a07408 usdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a0140f usdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a017c8 usdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1be1408 usdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
|
||||
[^:]+: c1b256c9 usdot za\.s\[w10, 1, vgx2\], {z22\.b-z23\.b}, {z18\.b-z19\.b}
|
||||
[^:]+: c1a11408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a17408 usdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a1140f usdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11788 usdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1bd1408 usdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
|
||||
[^:]+: c1b9760b usdot za\.s\[w11, 3, vgx4\], {z16\.b-z19\.b}, {z24\.b-z27\.b}
|
||||
203
gas/testsuite/gas/aarch64/sme2-15.s
Normal file
203
gas/testsuite/gas/aarch64/sme2-15.s
Normal file
@ -0,0 +1,203 @@
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
BFDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
BFDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
bfdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
|
||||
bfdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
BFDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
BFDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
bfdot za.s[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z0.h[3]
|
||||
bfdot za.s[w9, 1], { z4.h - z7.h }, z10.h[2]
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
BFDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
BFDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
bfdot za.s[w11, 0], { z0.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 7], { z0.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z30.h - z31.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z31.h, z0.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z31.h - z0.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, z15.h
|
||||
bfdot za.s[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z0.h
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
BFDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
BFDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
bfdot za.s[w11, 0], { z0.h - z3.h }, z0.h
|
||||
bfdot za.s[w8, 7], { z0.h - z3.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z28.h - z31.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z30.h - z1.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z31.h - z2.h }, z0.h
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, z15.h
|
||||
bfdot za.s[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
BFDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
BFDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
bfdot za.s[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
bfdot za.s[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
BFDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
BFDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
bfdot za.s[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
bfdot za.s[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
bfdot za.s[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
fdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
FDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
FDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
fdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
fdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
fdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
|
||||
fdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
FDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
FDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
fdot za.s[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
fdot za.s[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
fdot za.s[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, z0.h[3]
|
||||
fdot za.s[w9, 1], { z4.h - z7.h }, z10.h[2]
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, z0.h
|
||||
fdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
FDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
FDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
fdot za.s[w11, 0], { z0.h - z1.h }, z0.h
|
||||
fdot za.s[w8, 7], { z0.h - z1.h }, z0.h
|
||||
fdot za.s[w8, 0], { z30.h - z31.h }, z0.h
|
||||
fdot za.s[w8, 0], { z31.h, z0.h }, z0.h
|
||||
fdot za.s[w8, 0], { z31.h - z0.h }, z0.h
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, z15.h
|
||||
fdot za.s[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, z0.h
|
||||
fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
FDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
FDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
fdot za.s[w11, 0], { z0.h - z3.h }, z0.h
|
||||
fdot za.s[w8, 7], { z0.h - z3.h }, z0.h
|
||||
fdot za.s[w8, 0], { z28.h - z31.h }, z0.h
|
||||
fdot za.s[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
fdot za.s[w8, 0], { z30.h - z1.h }, z0.h
|
||||
fdot za.s[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
fdot za.s[w8, 0], { z31.h - z2.h }, z0.h
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, z15.h
|
||||
fdot za.s[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
fdot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
FDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
FDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
fdot za.s[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
fdot za.s[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
fdot za.s[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
fdot za.s[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
fdot za.s[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
FDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
FDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
fdot za.s[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
fdot za.s[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
fdot za.s[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
fdot za.s[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
fdot za.s[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
|
||||
usdot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b[0]
|
||||
USDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b[0]
|
||||
USDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B[0]
|
||||
usdot za.s[w11, 0], { z0.b - z1.b }, z0.b[0]
|
||||
usdot za.s[w8, 7], { z0.b - z1.b }, z0.b[0]
|
||||
usdot za.s[w8, 0], { z30.b - z31.b }, z0.b[0]
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, z0.b[3]
|
||||
usdot za.s[w10, 2], { z14.b - z15.b }, z13.b[1]
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
|
||||
usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
|
||||
USDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
|
||||
USDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
|
||||
usdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
|
||||
usdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
|
||||
usdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
|
||||
usdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, z0.b
|
||||
usdot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b
|
||||
USDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b
|
||||
USDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B
|
||||
usdot za.s[w11, 0], { z0.b - z1.b }, z0.b
|
||||
usdot za.s[w8, 7], { z0.b - z1.b }, z0.b
|
||||
usdot za.s[w8, 0], { z30.b - z31.b }, z0.b
|
||||
usdot za.s[w8, 0], { z31.b, z0.b }, z0.b
|
||||
usdot za.s[w8, 0], { z31.b - z0.b }, z0.b
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, z15.b
|
||||
usdot za.s[w9, 3], { z21.b - z22.b }, z9.b
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, z0.b
|
||||
usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
|
||||
USDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b
|
||||
USDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B
|
||||
usdot za.s[w11, 0], { z0.b - z3.b }, z0.b
|
||||
usdot za.s[w8, 7], { z0.b - z3.b }, z0.b
|
||||
usdot za.s[w8, 0], { z28.b - z31.b }, z0.b
|
||||
usdot za.s[w8, 0], { z30.b, z31.b, z0.b, z1.b }, z0.b
|
||||
usdot za.s[w8, 0], { z30.b - z1.b }, z0.b
|
||||
usdot za.s[w8, 0], { z31.b, z0.b, z1.b, z2.b }, z0.b
|
||||
usdot za.s[w8, 0], { z31.b - z2.b }, z0.b
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, z15.b
|
||||
usdot za.s[w10, 5], { z17.b - z20.b }, z3.b
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
usdot za.s[w8, 0, vgx2], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
USDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, { Z0.b - Z1.b }
|
||||
USDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, { Z0.B - Z1.B }
|
||||
usdot za.s[w11, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
usdot za.s[w8, 7], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
usdot za.s[w8, 0], { z30.b - z31.b }, { z0.b - z1.b }
|
||||
usdot za.s[w8, 0], { z0.b - z1.b }, { z30.b - z31.b }
|
||||
usdot za.s[w10, 1], { z22.b - z23.b }, { z18.b - z19.b }
|
||||
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
USDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, { Z0.b - Z3.b }
|
||||
USDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, { Z0.B - Z3.B }
|
||||
usdot za.s[w11, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
usdot za.s[w8, 7], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
usdot za.s[w8, 0], { z28.b - z31.b }, { z0.b - z3.b }
|
||||
usdot za.s[w8, 0], { z0.b - z3.b }, { z28.b - z31.b }
|
||||
usdot za.s[w11, 3], { z16.b - z19.b }, { z24.b - z27.b }
|
||||
3
gas/testsuite/gas/aarch64/sme2-16-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-16-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-16-invalid.s
|
||||
#error_output: sme2-16-invalid.l
|
||||
97
gas/testsuite/gas/aarch64/sme2-16-invalid.l
Normal file
97
gas/testsuite/gas/aarch64/sme2-16-invalid.l
Normal file
@ -0,0 +1,97 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sdot 0,{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sdot za\.s\[w8,0\],0,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},0'
|
||||
[^ :]+:[0-9]+: Error: missing braces at operand 2 -- `sdot za\.h\[w8,0\],z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w12,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,-1\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,8\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z1\.h-z2\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[4\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w7,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w12,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,-1\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,8\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z1\.h-z4\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z2\.h-z5\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z3\.h-z6\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[4\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `sdot za\.s\[w8,0\],{z0-z1},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\.h\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h-z4\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h,z1\.h,z5\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `sdot za\.s\[w8,0\],{z0-z1},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\[w8,0\],{z0\.h-z1\.h},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w7,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w12,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,-1\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,8\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z1\.h-z2\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z15\.h-z16\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z31\.h,z0\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w7,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `sdot za\.s\[w12,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,-1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `sdot za\.s\[w8,8\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z1\.h-z4\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z2\.h-z5\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sdot za\.s\[w8,0\],{z3\.h-z6\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},{z15\.h-z18\.h}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},{z29\.h,z30\.h,z31\.h,z0\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `sdot za\.s\[w8,0\],{z0\.h-z2\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z2\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z4\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sdot za\.s\[w8,0,vgx2\],{z0\.h-z3\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sdot za\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sdot za\.s\[w8, 0\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `sdot za\.s\[w8,0:0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `sdot za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `sdot za\.s\[w8,0:2\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `sdot za\.s\[w8,0:3\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `sdot za\.s\[w8,1:0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `sdot za\.s\[w8,foo:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `sdot za\.s\[w8,1:foo\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected a constant immediate offset at operand 1 -- `sdot za\.s\[w8,foo:bar\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
87
gas/testsuite/gas/aarch64/sme2-16-invalid.s
Normal file
87
gas/testsuite/gas/aarch64/sme2-16-invalid.s
Normal file
@ -0,0 +1,87 @@
|
||||
sdot 0, { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], 0, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, 0
|
||||
|
||||
sdot za.h[w8, 0], z0.h, z0.h
|
||||
sdot za.h[w8, 0], { z0.h - z1.h }, z0.h
|
||||
|
||||
sdot za.s[w7, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w12, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, -1], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 8], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z2.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z1.h - z2.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0.h[-1]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0.h[4]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z16.h[0]
|
||||
|
||||
sdot za.s[w7, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w12, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, -1], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, 8], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z1.h - z4.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z2.h - z5.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z3.h - z6.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z0.h[-1]
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z0.h[4]
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z16.h[0]
|
||||
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0 - z1 }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0[0]
|
||||
sdot za.h[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.h[w8, 0], { z0.s - z1.s }, z0.s[0]
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z2.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h - z4.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h, z1.h, z2.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h, z1.h, z5.h }, z0.h
|
||||
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z3.h }, z0.h
|
||||
sdot za[w8, 0], { z0.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0 - z1 }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0
|
||||
sdot za[w8, 0], { z0.h - z1.h }, z0
|
||||
|
||||
sdot za.s[w7, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w12, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, -1], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 8], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z1.h - z2.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z15.h - z16.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z31.h, z0.h }
|
||||
|
||||
sdot za.s[w7, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w12, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, -1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 8], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z1.h - z4.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z2.h - z5.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z3.h - z6.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, { z15.h - z18.h }
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, { z29.h, z30.h, z31.h, z0.h }
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z2.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z2.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z4.h }
|
||||
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z3.h }, { z0.h - z1.h }
|
||||
sdot za[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
|
||||
sdot za.s[w8, 0:0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0:2], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0:3], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 1:0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, foo:1], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 1:foo], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, foo:bar], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
3
gas/testsuite/gas/aarch64/sme2-16-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-16-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-16.s
|
||||
#error_output: sme2-16-noarch.l
|
||||
249
gas/testsuite/gas/aarch64/sme2-16-noarch.l
Normal file
249
gas/testsuite/gas/aarch64/sme2-16-noarch.l
Normal file
@ -0,0 +1,249 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w9,1\],{z4\.h-z7\.h},z10\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,2\],{z14\.b-z15\.b},z13\.b\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.b,z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.b-z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w9,3\],{z21\.b-z22\.b},z9\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.b,z31\.b,z0\.b,z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z31\.b-z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,5\],{z17\.b-z20\.b},z3\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},{Z0\.b-Z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},{Z0\.B-Z1\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z30\.b-z31\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z1\.b},{z30\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w10,1\],{z22\.b-z23\.b},{z18\.b-z19\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},{Z0\.b-Z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},{Z0\.B-Z3\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,7\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z28\.b-z31\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w8,0\],{z0\.b-z3\.b},{z28\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.s\[w11,3\],{z16\.b-z19\.b},{z24\.b-z27\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w9,1\],{z4\.h-z7\.h},z10\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,2\],{z14\.b-z15\.b},z13\.b\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.b,z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.b-z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w9,3\],{z21\.b-z22\.b},z9\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.b,z31\.b,z0\.b,z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z31\.b-z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,5\],{z17\.b-z20\.b},z3\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},{Z0\.b-Z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},{Z0\.B-Z1\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z30\.b-z31\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z1\.b},{z30\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w10,1\],{z22\.b-z23\.b},{z18\.b-z19\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},{Z0\.b-Z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},{Z0\.B-Z3\.B}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,7\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z28\.b-z31\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w8,0\],{z0\.b-z3\.b},{z28\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.s\[w11,3\],{z16\.b-z19\.b},{z24\.b-z27\.b}'
|
||||
257
gas/testsuite/gas/aarch64/sme2-16.d
Normal file
257
gas/testsuite/gas/aarch64/sme2-16.d
Normal file
@ -0,0 +1,257 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1501000 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501000 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501000 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501000 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1507000 sdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501007 sdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c15013c0 sdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f1000 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1501c00 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
|
||||
[^:]+: c15d55c2 sdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1509000 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509000 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509000 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509000 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150f000 sdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509007 sdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509380 sdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f9000 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1509c00 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[3\]
|
||||
[^:]+: c15ab881 sdot za\.s\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[2\]
|
||||
[^:]+: c1601408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1607408 sdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c160140f sdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c16017c8 sdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16017e8 sdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16017e8 sdot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16f1408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c16936ab sdot za\.s\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1701408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1707408 sdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c170140f sdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701788 sdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c17017c8 sdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017c8 sdot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017e8 sdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17017e8 sdot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17f1408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c173562d sdot za\.s\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1e01408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e07408 sdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e0140f sdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e017c8 sdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1fe1408 sdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1f256c9 sdot za\.s\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1e11408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e17408 sdot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e1140f sdot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11788 sdot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1fd1408 sdot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1f9760b sdot za\.s\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
[^:]+: c1501020 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501020 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501020 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501020 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1507020 sdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501027 sdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c15013e0 sdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f1020 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
|
||||
[^:]+: c1501c20 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
|
||||
[^:]+: c15d55e2 sdot za\.s\[w10, 2, vgx2\], {z14\.b-z15\.b}, z13\.b\[1\]
|
||||
[^:]+: c1509020 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509020 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509020 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509020 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150f020 sdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509027 sdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c15093a0 sdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f9020 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
|
||||
[^:]+: c1509c20 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
|
||||
[^:]+: c15ab8a1 sdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
|
||||
[^:]+: c1201400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1207400 sdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201407 sdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c12017c0 sdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12017e0 sdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12017e0 sdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12f1400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
|
||||
[^:]+: c12936a3 sdot za\.s\[w9, 3, vgx2\], {z21\.b-z22\.b}, z9\.b
|
||||
[^:]+: c1301400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1307400 sdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301407 sdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301780 sdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b
|
||||
[^:]+: c13017c0 sdot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017c0 sdot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017e0 sdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13017e0 sdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13f1400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
|
||||
[^:]+: c1335625 sdot za\.s\[w10, 5, vgx4\], {z17\.b-z20\.b}, z3\.b
|
||||
[^:]+: c1a01400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a07400 sdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01407 sdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a017c0 sdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1be1400 sdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
|
||||
[^:]+: c1b256c1 sdot za\.s\[w10, 1, vgx2\], {z22\.b-z23\.b}, {z18\.b-z19\.b}
|
||||
[^:]+: c1a11400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a17400 sdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11407 sdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11780 sdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1bd1400 sdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
|
||||
[^:]+: c1b97603 sdot za\.s\[w11, 3, vgx4\], {z16\.b-z19\.b}, {z24\.b-z27\.b}
|
||||
[^:]+: c1501010 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501010 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501010 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501010 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1507010 udot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1501017 udot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c15013d0 udot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f1010 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1501c10 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
|
||||
[^:]+: c15d55d2 udot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1509010 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509010 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509010 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509010 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c150f010 udot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509017 udot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1509390 udot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c15f9010 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1509c10 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[3\]
|
||||
[^:]+: c15ab891 udot za\.s\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[2\]
|
||||
[^:]+: c1601418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1607418 udot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c160141f udot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c16017d8 udot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16017f8 udot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16017f8 udot za\.s\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16f1418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c16936bb udot za\.s\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1701418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1707418 udot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c170141f udot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701798 udot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c17017d8 udot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017d8 udot za\.s\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017f8 udot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17017f8 udot za\.s\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17f1418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c173563d udot za\.s\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1e01418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e07418 udot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e0141f udot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e017d8 udot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1fe1418 udot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1f256d9 udot za\.s\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1e11418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e17418 udot za\.s\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e1141f udot za\.s\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11798 udot za\.s\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1fd1418 udot za\.s\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1f9761b udot za\.s\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
[^:]+: c1501030 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501030 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501030 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501030 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1507030 udot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501037 udot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c15013f0 udot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f1030 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
|
||||
[^:]+: c1501c30 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
|
||||
[^:]+: c15d55f2 udot za\.s\[w10, 2, vgx2\], {z14\.b-z15\.b}, z13\.b\[1\]
|
||||
[^:]+: c1509030 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509030 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509030 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509030 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150f030 udot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509037 udot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c15093b0 udot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f9030 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
|
||||
[^:]+: c1509c30 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
|
||||
[^:]+: c15ab8b1 udot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
|
||||
[^:]+: c1201410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1207410 udot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201417 udot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c12017d0 udot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12017f0 udot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12017f0 udot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12f1410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
|
||||
[^:]+: c12936b3 udot za\.s\[w9, 3, vgx2\], {z21\.b-z22\.b}, z9\.b
|
||||
[^:]+: c1301410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1307410 udot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301417 udot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301790 udot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b
|
||||
[^:]+: c13017d0 udot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017d0 udot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017f0 udot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13017f0 udot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13f1410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
|
||||
[^:]+: c1335635 udot za\.s\[w10, 5, vgx4\], {z17\.b-z20\.b}, z3\.b
|
||||
[^:]+: c1a01410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a07410 udot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a01417 udot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1a017d0 udot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1be1410 udot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
|
||||
[^:]+: c1b256d1 udot za\.s\[w10, 1, vgx2\], {z22\.b-z23\.b}, {z18\.b-z19\.b}
|
||||
[^:]+: c1a11410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a17410 udot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11417 udot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1a11790 udot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1bd1410 udot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
|
||||
[^:]+: c1b97613 udot za\.s\[w11, 3, vgx4\], {z16\.b-z19\.b}, {z24\.b-z27\.b}
|
||||
271
gas/testsuite/gas/aarch64/sme2-16.s
Normal file
271
gas/testsuite/gas/aarch64/sme2-16.s
Normal file
@ -0,0 +1,271 @@
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
sdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
|
||||
sdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
sdot za.s[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z0.h[3]
|
||||
sdot za.s[w9, 1], { z4.h - z7.h }, z10.h[2]
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
sdot za.s[w11, 0], { z0.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 7], { z0.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 0], { z30.h - z31.h }, z0.h
|
||||
sdot za.s[w8, 0], { z31.h, z0.h }, z0.h
|
||||
sdot za.s[w8, 0], { z31.h - z0.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, z15.h
|
||||
sdot za.s[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z0.h
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
sdot za.s[w11, 0], { z0.h - z3.h }, z0.h
|
||||
sdot za.s[w8, 7], { z0.h - z3.h }, z0.h
|
||||
sdot za.s[w8, 0], { z28.h - z31.h }, z0.h
|
||||
sdot za.s[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
sdot za.s[w8, 0], { z30.h - z1.h }, z0.h
|
||||
sdot za.s[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
sdot za.s[w8, 0], { z31.h - z2.h }, z0.h
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, z15.h
|
||||
sdot za.s[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
sdot za.s[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
sdot za.s[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
sdot za.s[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
sdot za.s[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
sdot za.s[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
sdot za.s[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
|
||||
sdot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b[0]
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b[0]
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B[0]
|
||||
sdot za.s[w11, 0], { z0.b - z1.b }, z0.b[0]
|
||||
sdot za.s[w8, 7], { z0.b - z1.b }, z0.b[0]
|
||||
sdot za.s[w8, 0], { z30.b - z31.b }, z0.b[0]
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, z0.b[3]
|
||||
sdot za.s[w10, 2], { z14.b - z15.b }, z13.b[1]
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
|
||||
sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
|
||||
sdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
|
||||
sdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
|
||||
sdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
|
||||
sdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, z0.b
|
||||
sdot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B
|
||||
sdot za.s[w11, 0], { z0.b - z1.b }, z0.b
|
||||
sdot za.s[w8, 7], { z0.b - z1.b }, z0.b
|
||||
sdot za.s[w8, 0], { z30.b - z31.b }, z0.b
|
||||
sdot za.s[w8, 0], { z31.b, z0.b }, z0.b
|
||||
sdot za.s[w8, 0], { z31.b - z0.b }, z0.b
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, z15.b
|
||||
sdot za.s[w9, 3], { z21.b - z22.b }, z9.b
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, z0.b
|
||||
sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B
|
||||
sdot za.s[w11, 0], { z0.b - z3.b }, z0.b
|
||||
sdot za.s[w8, 7], { z0.b - z3.b }, z0.b
|
||||
sdot za.s[w8, 0], { z28.b - z31.b }, z0.b
|
||||
sdot za.s[w8, 0], { z30.b, z31.b, z0.b, z1.b }, z0.b
|
||||
sdot za.s[w8, 0], { z30.b - z1.b }, z0.b
|
||||
sdot za.s[w8, 0], { z31.b, z0.b, z1.b, z2.b }, z0.b
|
||||
sdot za.s[w8, 0], { z31.b - z2.b }, z0.b
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, z15.b
|
||||
sdot za.s[w10, 5], { z17.b - z20.b }, z3.b
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sdot za.s[w8, 0, vgx2], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
SDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, { Z0.b - Z1.b }
|
||||
SDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, { Z0.B - Z1.B }
|
||||
sdot za.s[w11, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sdot za.s[w8, 7], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sdot za.s[w8, 0], { z30.b - z31.b }, { z0.b - z1.b }
|
||||
sdot za.s[w8, 0], { z0.b - z1.b }, { z30.b - z31.b }
|
||||
sdot za.s[w10, 1], { z22.b - z23.b }, { z18.b - z19.b }
|
||||
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
SDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, { Z0.b - Z3.b }
|
||||
SDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, { Z0.B - Z3.B }
|
||||
sdot za.s[w11, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sdot za.s[w8, 7], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sdot za.s[w8, 0], { z28.b - z31.b }, { z0.b - z3.b }
|
||||
sdot za.s[w8, 0], { z0.b - z3.b }, { z28.b - z31.b }
|
||||
sdot za.s[w11, 3], { z16.b - z19.b }, { z24.b - z27.b }
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
udot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
|
||||
udot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
udot za.s[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.s[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.s[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, z0.h[3]
|
||||
udot za.s[w9, 1], { z4.h - z7.h }, z10.h[2]
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, z0.h
|
||||
udot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
udot za.s[w11, 0], { z0.h - z1.h }, z0.h
|
||||
udot za.s[w8, 7], { z0.h - z1.h }, z0.h
|
||||
udot za.s[w8, 0], { z30.h - z31.h }, z0.h
|
||||
udot za.s[w8, 0], { z31.h, z0.h }, z0.h
|
||||
udot za.s[w8, 0], { z31.h - z0.h }, z0.h
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, z15.h
|
||||
udot za.s[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, z0.h
|
||||
udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
udot za.s[w11, 0], { z0.h - z3.h }, z0.h
|
||||
udot za.s[w8, 7], { z0.h - z3.h }, z0.h
|
||||
udot za.s[w8, 0], { z28.h - z31.h }, z0.h
|
||||
udot za.s[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
udot za.s[w8, 0], { z30.h - z1.h }, z0.h
|
||||
udot za.s[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
udot za.s[w8, 0], { z31.h - z2.h }, z0.h
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, z15.h
|
||||
udot za.s[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.s[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
udot za.s[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.s[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.s[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
udot za.s[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
udot za.s[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
udot za.s[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.s[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.s[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
udot za.s[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
udot za.s[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
|
||||
udot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b[0]
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b[0]
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B[0]
|
||||
udot za.s[w11, 0], { z0.b - z1.b }, z0.b[0]
|
||||
udot za.s[w8, 7], { z0.b - z1.b }, z0.b[0]
|
||||
udot za.s[w8, 0], { z30.b - z31.b }, z0.b[0]
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, z0.b[3]
|
||||
udot za.s[w10, 2], { z14.b - z15.b }, z13.b[1]
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
|
||||
udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
|
||||
udot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
|
||||
udot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
|
||||
udot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
|
||||
udot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, z0.b
|
||||
udot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B
|
||||
udot za.s[w11, 0], { z0.b - z1.b }, z0.b
|
||||
udot za.s[w8, 7], { z0.b - z1.b }, z0.b
|
||||
udot za.s[w8, 0], { z30.b - z31.b }, z0.b
|
||||
udot za.s[w8, 0], { z31.b, z0.b }, z0.b
|
||||
udot za.s[w8, 0], { z31.b - z0.b }, z0.b
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, z15.b
|
||||
udot za.s[w9, 3], { z21.b - z22.b }, z9.b
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, z0.b
|
||||
udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B
|
||||
udot za.s[w11, 0], { z0.b - z3.b }, z0.b
|
||||
udot za.s[w8, 7], { z0.b - z3.b }, z0.b
|
||||
udot za.s[w8, 0], { z28.b - z31.b }, z0.b
|
||||
udot za.s[w8, 0], { z30.b, z31.b, z0.b, z1.b }, z0.b
|
||||
udot za.s[w8, 0], { z30.b - z1.b }, z0.b
|
||||
udot za.s[w8, 0], { z31.b, z0.b, z1.b, z2.b }, z0.b
|
||||
udot za.s[w8, 0], { z31.b - z2.b }, z0.b
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, z15.b
|
||||
udot za.s[w10, 5], { z17.b - z20.b }, z3.b
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
udot za.s[w8, 0, vgx2], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
UDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, { Z0.b - Z1.b }
|
||||
UDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, { Z0.B - Z1.B }
|
||||
udot za.s[w11, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
udot za.s[w8, 7], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
udot za.s[w8, 0], { z30.b - z31.b }, { z0.b - z1.b }
|
||||
udot za.s[w8, 0], { z0.b - z1.b }, { z30.b - z31.b }
|
||||
udot za.s[w10, 1], { z22.b - z23.b }, { z18.b - z19.b }
|
||||
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
udot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
UDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, { Z0.b - Z3.b }
|
||||
UDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, { Z0.B - Z3.B }
|
||||
udot za.s[w11, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
udot za.s[w8, 7], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
udot za.s[w8, 0], { z28.b - z31.b }, { z0.b - z3.b }
|
||||
udot za.s[w8, 0], { z0.b - z3.b }, { z28.b - z31.b }
|
||||
udot za.s[w11, 3], { z16.b - z19.b }, { z24.b - z27.b }
|
||||
3
gas/testsuite/gas/aarch64/sme2-17-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-17-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-17-invalid.s
|
||||
#error_output: sme2-17-invalid.l
|
||||
20
gas/testsuite/gas/aarch64/sme2-17-invalid.l
Normal file
20
gas/testsuite/gas/aarch64/sme2-17-invalid.l
Normal file
@ -0,0 +1,20 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sudot 0,{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sudot za\.s\[w8,0\],0,z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.s\[w8,0\],{z0\.b-z1\.b},0'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z1\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z3\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.s\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.s\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
12
gas/testsuite/gas/aarch64/sme2-17-invalid.s
Normal file
12
gas/testsuite/gas/aarch64/sme2-17-invalid.s
Normal file
@ -0,0 +1,12 @@
|
||||
sudot 0, { z0.b - z1.b }, z0.b[0]
|
||||
sudot za.s[w8, 0], 0, z0.b[0]
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, 0
|
||||
|
||||
sudot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sudot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sudot za.s[w8, 0], { z0.h - z1.h }, z0.h
|
||||
sudot za.s[w8, 0], { z0.h - z3.h }, z0.h
|
||||
sudot za.s[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sudot za.s[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, { z0.b - z3.b }
|
||||
3
gas/testsuite/gas/aarch64/sme2-17-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-17-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-17.s
|
||||
#error_output: sme2-17-noarch.l
|
||||
45
gas/testsuite/gas/aarch64/sme2-17-noarch.l
Normal file
45
gas/testsuite/gas/aarch64/sme2-17-noarch.l
Normal file
@ -0,0 +1,45 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w10,2\],{z14\.b-z15\.b},z13\.b\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0,vgx2\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.s\[W8,0,VGx2\],{Z0\.b-Z1\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.S\[W8,0,VGX2\],{Z0\.B-Z1\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w11,0\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,7\],{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z30\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z31\.b,z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z31\.b-z0\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z1\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w9,3\],{z21\.b-z22\.b},z9\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z30\.b,z31\.b,z0\.b,z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z30\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z31\.b-z2\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sudot za\.s\[w10,5\],{z17\.b-z20\.b},z3\.b'
|
||||
53
gas/testsuite/gas/aarch64/sme2-17.d
Normal file
53
gas/testsuite/gas/aarch64/sme2-17.d
Normal file
@ -0,0 +1,53 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1501038 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501038 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501038 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1501038 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c1507038 sudot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c150103f sudot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^:]+: c15013f8 sudot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f1038 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
|
||||
[^:]+: c1501c38 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
|
||||
[^:]+: c15d55fa sudot za\.s\[w10, 2, vgx2\], {z14\.b-z15\.b}, z13\.b\[1\]
|
||||
[^:]+: c1509038 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509038 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509038 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c1509038 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150f038 sudot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c150903f sudot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^:]+: c15093b8 sudot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
|
||||
[^:]+: c15f9038 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
|
||||
[^:]+: c1509c38 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
|
||||
[^:]+: c15ab8b9 sudot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
|
||||
[^:]+: c1201418 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201418 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201418 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1201418 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c1207418 sudot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c120141f sudot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c12017d8 sudot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12017f8 sudot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12017f8 sudot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
|
||||
[^:]+: c12f1418 sudot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
|
||||
[^:]+: c12936bb sudot za\.s\[w9, 3, vgx2\], {z21\.b-z22\.b}, z9\.b
|
||||
[^:]+: c1301418 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301418 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301418 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301418 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1307418 sudot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c130141f sudot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c1301798 sudot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b
|
||||
[^:]+: c13017d8 sudot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017d8 sudot za\.s\[w8, 0, vgx4\], {z30\.b-z1\.b}, z0\.b
|
||||
[^:]+: c13017f8 sudot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13017f8 sudot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
|
||||
[^:]+: c13f1418 sudot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
|
||||
[^:]+: c133563d sudot za\.s\[w10, 5, vgx4\], {z17\.b-z20\.b}, z3\.b
|
||||
47
gas/testsuite/gas/aarch64/sme2-17.s
Normal file
47
gas/testsuite/gas/aarch64/sme2-17.s
Normal file
@ -0,0 +1,47 @@
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
|
||||
sudot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b[0]
|
||||
SUDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b[0]
|
||||
SUDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B[0]
|
||||
sudot za.s[w11, 0], { z0.b - z1.b }, z0.b[0]
|
||||
sudot za.s[w8, 7], { z0.b - z1.b }, z0.b[0]
|
||||
sudot za.s[w8, 0], { z30.b - z31.b }, z0.b[0]
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, z0.b[3]
|
||||
sudot za.s[w10, 2], { z14.b - z15.b }, z13.b[1]
|
||||
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
|
||||
sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
|
||||
SUDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
|
||||
SUDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
|
||||
sudot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
|
||||
sudot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
|
||||
sudot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
|
||||
sudot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
|
||||
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, z0.b
|
||||
sudot za.s[w8, 0, vgx2], { z0.b - z1.b }, z0.b
|
||||
SUDOT ZA.s[W8, 0, VGx2], { Z0.b - Z1.b }, Z0.b
|
||||
SUDOT ZA.S[W8, 0, VGX2], { Z0.B - Z1.B }, Z0.B
|
||||
sudot za.s[w11, 0], { z0.b - z1.b }, z0.b
|
||||
sudot za.s[w8, 7], { z0.b - z1.b }, z0.b
|
||||
sudot za.s[w8, 0], { z30.b - z31.b }, z0.b
|
||||
sudot za.s[w8, 0], { z31.b, z0.b }, z0.b
|
||||
sudot za.s[w8, 0], { z31.b - z0.b }, z0.b
|
||||
sudot za.s[w8, 0], { z0.b - z1.b }, z15.b
|
||||
sudot za.s[w9, 3], { z21.b - z22.b }, z9.b
|
||||
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, z0.b
|
||||
sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
|
||||
SUDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b
|
||||
SUDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B
|
||||
sudot za.s[w11, 0], { z0.b - z3.b }, z0.b
|
||||
sudot za.s[w8, 7], { z0.b - z3.b }, z0.b
|
||||
sudot za.s[w8, 0], { z28.b - z31.b }, z0.b
|
||||
sudot za.s[w8, 0], { z30.b, z31.b, z0.b, z1.b }, z0.b
|
||||
sudot za.s[w8, 0], { z30.b - z1.b }, z0.b
|
||||
sudot za.s[w8, 0], { z31.b, z0.b, z1.b, z2.b }, z0.b
|
||||
sudot za.s[w8, 0], { z31.b - z2.b }, z0.b
|
||||
sudot za.s[w8, 0], { z0.b - z3.b }, z15.b
|
||||
sudot za.s[w10, 5], { z17.b - z20.b }, z3.b
|
||||
3
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-i16i64-3-invalid.s
|
||||
#error_output: sme2-i16i64-3-invalid.l
|
||||
19
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.l
Normal file
19
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.l
Normal file
@ -0,0 +1,19 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[2\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z3\.b}, z0\.b\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z1\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sudot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sudot za\.s\[w8, 0\], {z0\.b-z3\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.d\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sudot za\.d\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
12
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.s
Normal file
12
gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.s
Normal file
@ -0,0 +1,12 @@
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z0.h[-1]
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z0.h[2]
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z0.h[-1]
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z0.h[2]
|
||||
|
||||
sudot za.d[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sudot za.d[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sudot za.d[w8, 0], { z0.h - z1.h }, z0.h
|
||||
sudot za.d[w8, 0], { z0.h - z3.h }, z0.h
|
||||
sudot za.d[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sudot za.d[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
3
gas/testsuite/gas/aarch64/sme2-i16i64-3-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-i16i64-3-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#source: sme2-i16i64-3.s
|
||||
#error_output: sme2-i16i64-3-noarch.l
|
||||
125
gas/testsuite/gas/aarch64/sme2-i16i64-3-noarch.l
Normal file
125
gas/testsuite/gas/aarch64/sme2-i16i64-3-noarch.l
Normal file
@ -0,0 +1,125 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w9,1\],{z4\.h-z7\.h},z10\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sdot za\.d\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w9,1\],{z4\.h-z7\.h},z10\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z31\.h,z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z31\.h-z0\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w9,3\],{z21\.h-z22\.h},z9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z30\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z31\.h-z2\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w10,5\],{z17\.h-z20\.h},z3\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w10,1\],{z22\.h-z23\.h},{z18\.h-z19\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,7\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w8,0\],{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `udot za\.d\[w11,3\],{z16\.h-z19\.h},{z24\.h-z27\.h}'
|
||||
133
gas/testsuite/gas/aarch64/sme2-i16i64-3.d
Normal file
133
gas/testsuite/gas/aarch64/sme2-i16i64-3.d
Normal file
@ -0,0 +1,133 @@
|
||||
#as: -march=armv8-a+sme2+sme-i16i64
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1d00008 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00008 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00008 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00008 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d06008 sdot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0000f sdot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d003c8 sdot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c1df0008 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1d00408 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[1\]
|
||||
[^:]+: c1dd45ca sdot za\.d\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1d08008 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08008 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08008 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08008 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0e008 sdot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0800f sdot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08388 sdot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c1df8008 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1d08408 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[1\]
|
||||
[^:]+: c1daa489 sdot za\.d\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[1\]
|
||||
[^:]+: c1601400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1607400 sdot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601407 sdot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c16017c0 sdot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16017e0 sdot za\.d\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16017e0 sdot za\.d\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16f1400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c16936a3 sdot za\.d\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1701400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1707400 sdot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701407 sdot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701780 sdot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c17017c0 sdot za\.d\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017c0 sdot za\.d\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017e0 sdot za\.d\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17017e0 sdot za\.d\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17f1400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c1735625 sdot za\.d\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1e01400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e07400 sdot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01407 sdot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e017c0 sdot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1fe1400 sdot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1f256c1 sdot za\.d\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1e11400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e17400 sdot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11407 sdot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11780 sdot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1fd1400 sdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1f97603 sdot za\.d\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
[^:]+: c1d00018 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00018 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00018 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d00018 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d06018 udot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0001f udot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d003d8 udot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c1df0018 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
|
||||
[^:]+: c1d00418 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[1\]
|
||||
[^:]+: c1dd45da udot za\.d\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
|
||||
[^:]+: c1d08018 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08018 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08018 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08018 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0e018 udot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d0801f udot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
|
||||
[^:]+: c1d08398 udot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
|
||||
[^:]+: c1df8018 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
|
||||
[^:]+: c1d08418 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[1\]
|
||||
[^:]+: c1daa099 udot za\.d\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[0\]
|
||||
[^:]+: c1601410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1607410 udot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c1601417 udot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c16017d0 udot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16017f0 udot za\.d\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16017f0 udot za\.d\[w8, 0, vgx2\], {z31\.h-z0\.h}, z0\.h
|
||||
[^:]+: c16f1410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c16936b3 udot za\.d\[w9, 3, vgx2\], {z21\.h-z22\.h}, z9\.h
|
||||
[^:]+: c1701410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1707410 udot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701417 udot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c1701790 udot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c17017d0 udot za\.d\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017d0 udot za\.d\[w8, 0, vgx4\], {z30\.h-z1\.h}, z0\.h
|
||||
[^:]+: c17017f0 udot za\.d\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17017f0 udot za\.d\[w8, 0, vgx4\], {z31\.h-z2\.h}, z0\.h
|
||||
[^:]+: c17f1410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c1735635 udot za\.d\[w10, 5, vgx4\], {z17\.h-z20\.h}, z3\.h
|
||||
[^:]+: c1e01410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e07410 udot za\.d\[w11, 0, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e01417 udot za\.d\[w8, 7, vgx2\], {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1e017d0 udot za\.d\[w8, 0, vgx2\], {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1fe1410 udot za\.d\[w8, 0, vgx2\], {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c1f256d1 udot za\.d\[w10, 1, vgx2\], {z22\.h-z23\.h}, {z18\.h-z19\.h}
|
||||
[^:]+: c1e11410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e17410 udot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11417 udot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1e11790 udot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1fd1410 udot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1f97613 udot za\.d\[w11, 3, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h}
|
||||
135
gas/testsuite/gas/aarch64/sme2-i16i64-3.s
Normal file
135
gas/testsuite/gas/aarch64/sme2-i16i64-3.s
Normal file
@ -0,0 +1,135 @@
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.d[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
SDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
SDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
sdot za.d[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.d[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
sdot za.d[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z0.h[1]
|
||||
sdot za.d[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
SDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
SDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
sdot za.d[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.d[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
sdot za.d[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z0.h[1]
|
||||
sdot za.d[w9, 1], { z4.h - z7.h }, z10.h[1]
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z0.h
|
||||
sdot za.d[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
SDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
SDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
sdot za.d[w11, 0], { z0.h - z1.h }, z0.h
|
||||
sdot za.d[w8, 7], { z0.h - z1.h }, z0.h
|
||||
sdot za.d[w8, 0], { z30.h - z31.h }, z0.h
|
||||
sdot za.d[w8, 0], { z31.h, z0.h }, z0.h
|
||||
sdot za.d[w8, 0], { z31.h - z0.h }, z0.h
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, z15.h
|
||||
sdot za.d[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z0.h
|
||||
sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
SDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
SDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
sdot za.d[w11, 0], { z0.h - z3.h }, z0.h
|
||||
sdot za.d[w8, 7], { z0.h - z3.h }, z0.h
|
||||
sdot za.d[w8, 0], { z28.h - z31.h }, z0.h
|
||||
sdot za.d[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
sdot za.d[w8, 0], { z30.h - z1.h }, z0.h
|
||||
sdot za.d[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
sdot za.d[w8, 0], { z31.h - z2.h }, z0.h
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, z15.h
|
||||
sdot za.d[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.d[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
SDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
SDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
sdot za.d[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.d[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sdot za.d[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
sdot za.d[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
sdot za.d[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
SDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
SDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
sdot za.d[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.d[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sdot za.d[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
sdot za.d[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
sdot za.d[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.d[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
|
||||
UDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
|
||||
UDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
|
||||
udot za.d[w11, 0], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.d[w8, 7], { z0.h - z1.h }, z0.h[0]
|
||||
udot za.d[w8, 0], { z30.h - z31.h }, z0.h[0]
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, z15.h[0]
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, z0.h[1]
|
||||
udot za.d[w10, 2], { z14.h - z15.h }, z13.h[1]
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
|
||||
UDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
|
||||
UDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
|
||||
udot za.d[w11, 0], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.d[w8, 7], { z0.h - z3.h }, z0.h[0]
|
||||
udot za.d[w8, 0], { z28.h - z31.h }, z0.h[0]
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, z15.h[0]
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, z0.h[1]
|
||||
udot za.d[w9, 1], { z4.h - z7.h }, z10.h[0]
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, z0.h
|
||||
udot za.d[w8, 0, vgx2], { z0.h - z1.h }, z0.h
|
||||
UDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h
|
||||
UDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H
|
||||
udot za.d[w11, 0], { z0.h - z1.h }, z0.h
|
||||
udot za.d[w8, 7], { z0.h - z1.h }, z0.h
|
||||
udot za.d[w8, 0], { z30.h - z31.h }, z0.h
|
||||
udot za.d[w8, 0], { z31.h, z0.h }, z0.h
|
||||
udot za.d[w8, 0], { z31.h - z0.h }, z0.h
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, z15.h
|
||||
udot za.d[w9, 3], { z21.h - z22.h }, z9.h
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, z0.h
|
||||
udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h
|
||||
UDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h
|
||||
UDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H
|
||||
udot za.d[w11, 0], { z0.h - z3.h }, z0.h
|
||||
udot za.d[w8, 7], { z0.h - z3.h }, z0.h
|
||||
udot za.d[w8, 0], { z28.h - z31.h }, z0.h
|
||||
udot za.d[w8, 0], { z30.h, z31.h, z0.h, z1.h }, z0.h
|
||||
udot za.d[w8, 0], { z30.h - z1.h }, z0.h
|
||||
udot za.d[w8, 0], { z31.h, z0.h, z1.h, z2.h }, z0.h
|
||||
udot za.d[w8, 0], { z31.h - z2.h }, z0.h
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, z15.h
|
||||
udot za.d[w10, 5], { z17.h - z20.h }, z3.h
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.d[w8, 0, vgx2], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
UDOT ZA.d[W8, 0, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h }
|
||||
UDOT ZA.D[W8, 0, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H }
|
||||
udot za.d[w11, 0], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.d[w8, 7], { z0.h - z1.h }, { z0.h - z1.h }
|
||||
udot za.d[w8, 0], { z30.h - z31.h }, { z0.h - z1.h }
|
||||
udot za.d[w8, 0], { z0.h - z1.h }, { z30.h - z31.h }
|
||||
udot za.d[w10, 1], { z22.h - z23.h }, { z18.h - z19.h }
|
||||
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
UDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h }
|
||||
UDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H }
|
||||
udot za.d[w11, 0], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.d[w8, 7], { z0.h - z3.h }, { z0.h - z3.h }
|
||||
udot za.d[w8, 0], { z28.h - z31.h }, { z0.h - z3.h }
|
||||
udot za.d[w8, 0], { z0.h - z3.h }, { z28.h - z31.h }
|
||||
udot za.d[w11, 3], { z16.h - z19.h }, { z24.h - z27.h }
|
||||
File diff suppressed because it is too large
Load Diff
@ -5349,6 +5349,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("bfdot", 0xc1501018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("bfdot", 0xc1509018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("bfdot", 0xc1201010, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("bfdot", 0xc1301010, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("bfdot", 0xc1a01010, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("bfdot", 0xc1a11010, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("bfmlal", 0xc1801010, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0),
|
||||
SME2_INSN ("bfmlal", 0xc1901010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("bfmlal", 0xc1909010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0),
|
||||
@ -5368,6 +5374,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
|
||||
SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fdot", 0xc1501008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("fdot", 0xc1509008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("fdot", 0xc1201000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("fdot", 0xc1301000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("fdot", 0xc1a01000, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("fdot", 0xc1a11000, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("fmax", 0xc120a100, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
|
||||
SME2_INSN ("fmax", 0xc120a900, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
|
||||
SME2_INSN ("fmax", 0xc120b100, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),
|
||||
@ -5506,6 +5518,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
|
||||
SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
|
||||
SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
|
||||
SME2_INSN ("sdot", 0xc1501000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1509000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("sdot", 0xc1601408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1701408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("sdot", 0xc1e01408, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1e11408, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("sdot", 0xc1501020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1509020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("sdot", 0xc1201400, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1301400, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("sdot", 0xc1a01400, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0),
|
||||
SME2_INSN ("sdot", 0xc1a11400, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("sel", 0xc1208000, 0xff21e021, sme_size_22, 0, OP4 (SME_Zdnx2, SME_PNg3, SME_Znx2, SME_Zmx2), OP_SVE_VUVV_BHSD, 0, 0),
|
||||
SME2_INSN ("sel", 0xc1218000, 0xff23e063, sme_size_22, 0, OP4 (SME_Zdnx4, SME_PNg3, SME_Znx4, SME_Zmx4), OP_SVE_VUVV_BHSD, 0, 0),
|
||||
SME2_INSN ("smax", 0xc120a000, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
@ -5627,11 +5651,27 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("sub", 0xc1301818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("sub", 0xc1a01818, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("sub", 0xc1a11818, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("sudot", 0xc1501038, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("sudot", 0xc1509038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("sudot", 0xc1201418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("sudot", 0xc1301418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("sumlall", 0xc1000014, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0),
|
||||
SME2_INSN ("sumlall", 0xc1100030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("sumlall", 0xc1108030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("sumlall", 0xc1200014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("sumlall", 0xc1300014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1501010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1509010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1601418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1701418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1e01418, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1e11418, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1501030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1509030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1201410, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1301410, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("udot", 0xc1a01410, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0),
|
||||
SME2_INSN ("udot", 0xc1a11410, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("umax", 0xc120a001, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("umax", 0xc120a801, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("umax", 0xc120b001, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
|
||||
@ -5676,6 +5716,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("urshl", 0xc120ba21, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("usdot", 0xc1501028, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("usdot", 0xc1509028, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("usdot", 0xc1201408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("usdot", 0xc1301408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("usdot", 0xc1a01408, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("usdot", 0xc1a11408, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SBB, F_OD (4), 0),
|
||||
SME2_INSN ("usmlall", 0xc1000004, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0),
|
||||
SME2_INSN ("usmlall", 0xc1100020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0),
|
||||
SME2_INSN ("usmlall", 0xc1108020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0),
|
||||
@ -5695,12 +5741,16 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),
|
||||
|
||||
/* SME2 I16I64 instructions. */
|
||||
SME2_I16I64_INSN ("sdot", 0xc1d00008, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (2), 0),
|
||||
SME2_I16I64_INSN ("sdot", 0xc1d08008, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0),
|
||||
SME2_I16I64_INSN ("smlall", 0xc1800000, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0),
|
||||
SME2_I16I64_INSN ("smlall", 0xc1900000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0),
|
||||
SME2_I16I64_INSN ("smlall", 0xc1908000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0),
|
||||
SME2_I16I64_INSN ("smlsll", 0xc1800008, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0),
|
||||
SME2_I16I64_INSN ("smlsll", 0xc1900008, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0),
|
||||
SME2_I16I64_INSN ("smlsll", 0xc1908008, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0),
|
||||
SME2_I16I64_INSN ("udot", 0xc1d00018, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (2), 0),
|
||||
SME2_I16I64_INSN ("udot", 0xc1d08018, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0),
|
||||
SME2_I16I64_INSN ("umlall", 0xc1800010, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0),
|
||||
SME2_I16I64_INSN ("umlall", 0xc1900010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0),
|
||||
SME2_I16I64_INSN ("umlall", 0xc1908010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user