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aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
This patch adds missing contraints to FEAT_B16B16 sve2 instructions bfclamp, bfmla and bfmls and add negative tests for all the bfloat instructions. The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.* to maintain consistency in the testsuite. The bfloat16-1-invalid.* tests are modified so that "selected processor does not support" is generated by the assembler, since +b16b16 is not passed in the command line. The bfloat16-2-invalid.* testcase includes the wrong operands bfloat16 tests.
This commit is contained in:
Srinath Parvathaneni
parent
98043d5fae
commit
524e985281
4
gas/testsuite/gas/aarch64/bfloat16-1-invalid.d
Normal file
4
gas/testsuite/gas/aarch64/bfloat16-1-invalid.d
Normal file
@ -0,0 +1,4 @@
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#name: Negative test with missing +b16b16 flag.
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#as: -march=armv9.4-a
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#source: bfloat16-1-invalid.s
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#error_output: bfloat16-1-invalid.l
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11
gas/testsuite/gas/aarch64/bfloat16-1-invalid.l
Normal file
11
gas/testsuite/gas/aarch64/bfloat16-1-invalid.l
Normal file
@ -0,0 +1,11 @@
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.*: Assembler messages:
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.*: Error: selected processor does not support `bfadd z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfmax z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfmaxnm z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfmin z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfminnm z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfmul z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfsub z0.h,p0/m,z0.h,z0.h'
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.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
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.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
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.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
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10
gas/testsuite/gas/aarch64/bfloat16-1-invalid.s
Normal file
10
gas/testsuite/gas/aarch64/bfloat16-1-invalid.s
Normal file
@ -0,0 +1,10 @@
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bfadd z0.h, p0/m, z0.h, z0.h
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bfmax z0.h, p0/m, z0.h, z0.h
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bfmaxnm z0.h, p0/m, z0.h, z0.h
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bfmin z0.h, p0/m, z0.h, z0.h
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bfminnm z0.h, p0/m, z0.h, z0.h
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bfmul z0.h, p0/m, z0.h, z0.h
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bfsub z0.h, p0/m, z0.h, z0.h
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bfclamp z3.h,z4.h,z16.h
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bfmla z3.h,z16.h,z6.h[7]
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bfmls z3.h,z16.h,z6.h[7]
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@ -104,3 +104,9 @@
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.*: 65020604 bfsub z4.h, z16.h, z2.h
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.*: 65010688 bfsub z8.h, z20.h, z1.h
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.*: 65000710 bfsub z16.h, z24.h, z0.h
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.*: 0420bca3 movprfx z3, z5
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.*: 64302483 bfclamp z3.h, z4.h, z16.h
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.*: 0420bca3 movprfx z3, z5
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.*: 647e0a03 bfmla z3.h, z16.h, z6.h\[7\]
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.*: 0420bca3 movprfx z3, z5
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.*: 647e0e03 bfmls z3.h, z16.h, z6.h\[7\]
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@ -110,4 +110,9 @@ bfsub z4.h, z16.h, z2.h
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bfsub z8.h, z20.h, z1.h
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bfsub z16.h, z24.h, z0.h
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movprfx z3, z5
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bfclamp z3.h, z4.h, z16.h
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movprfx z3, z5
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bfmla z3.h, z16.h, z6.h[7]
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movprfx z3, z5
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bfmls z3.h, z16.h, z6.h[7]
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4
gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
Normal file
4
gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
Normal file
@ -0,0 +1,4 @@
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#name: Test Bfloat16 instructions with wrong operand combinations
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#as: -march=armv9.4-a+b16b16
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#source: bfloat16-2-invalid.s
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#error_output: bfloat16-2-invalid.l
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265
gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
Normal file
265
gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
Normal file
@ -0,0 +1,265 @@
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.*: Assembler messages:
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.*: Error: operand mismatch -- `bfadd z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfadd z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfadd z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfadd z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfadd z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmax z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmax z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfmax z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmax z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmax z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmaxnm z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmaxnm z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmaxnm z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmaxnm z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmin z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmin z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfmin z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmin z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmin z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfminnm z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfminnm z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfminnm z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfminnm z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmla z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmla z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmla z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmla z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmls z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmls z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmls z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmls z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfmul z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfmul z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfmul z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfmul z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfmul z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfsub z0.s,p0/m,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
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.*: Error: p0-p7 expected at operand 2 -- `bfsub z0.h,p8/m,z0.h,z16.h'
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.*: Error: operand 3 must be the same register as operand 1 -- `bfsub z31.h,p0/m,z0.h,z16.h'
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.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.s,z16.h'
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.*: Info: did you mean this\?
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.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.d'
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.*: Info: did you mean this\?
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.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
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.*: Error: operand mismatch -- `bfsub z31.d,p7/m,z31.d,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfsub z31.h, p7/m, z31.h, z31.h
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.*: Error: operand mismatch -- `bfadd z0.b,z0.h,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfadd z0.s,z0.h,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfadd z0.h,z0.d,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfadd z0.h,z0.h,z0.b'
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.*: Info: did you mean this\?
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.*: Info: bfadd z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfadd z31.h, z31.h, z31.h
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.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h'
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.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h'
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.*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h'
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.*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfclamp z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfclamp z0.s,z0.h,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfclamp z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfclamp z0.h,z0.d,z0.h'
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.*: Info: did you mean this\?
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.*: Info: bfclamp z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfclamp z0.h,z0.h,z0.b'
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.*: Info: did you mean this\?
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.*: Info: bfclamp z0.h, z0.h, z0.h
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.*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d'
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.*: Info: did you mean this\?
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.*: Info: bfclamp z31.h, z31.h, z31.h
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.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h'
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.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h'
|
||||
.*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
|
||||
.*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmla z0.h, z0.h, z0.h\[0\]
|
||||
.*: Error: operand mismatch -- `bfmla z0.s,z0.h,z0.h\[6\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmla z0.h, z0.h, z0.h\[6\]
|
||||
.*: Error: operand mismatch -- `bfmla z0.h,z0.d,z0.h\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmla z0.h, z0.h, z0.h\[8\]
|
||||
.*: Error: operand mismatch -- `bfmla z0.h,z0.h,z0.b\[2\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmla z0.h, z0.h, z0.h\[2\]
|
||||
.*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmla z31.h, z31.h, z31.h\[8\]
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]'
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]'
|
||||
.*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]'
|
||||
.*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmls z0.h, z0.h, z0.h\[0\]
|
||||
.*: Error: operand mismatch -- `bfmls z0.s,z0.h,z0.h\[6\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmls z0.h, z0.h, z0.h\[6\]
|
||||
.*: Error: operand mismatch -- `bfmls z0.h,z0.d,z0.h\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmls z0.h, z0.h, z0.h\[8\]
|
||||
.*: Error: operand mismatch -- `bfmls z0.h,z0.h,z0.b\[2\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmls z0.h, z0.h, z0.h\[2\]
|
||||
.*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmls z31.h, z31.h, z31.h\[8\]
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]'
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]'
|
||||
.*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]'
|
||||
.*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmul z0.h, z0.h, z0.h\[0\]
|
||||
.*: Error: operand mismatch -- `bfmul z0.s,z0.h,z0.h\[6\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmul z0.h, z0.h, z0.h\[6\]
|
||||
.*: Error: operand mismatch -- `bfmul z0.h,z0.d,z0.h\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmul z0.h, z0.h, z0.h\[8\]
|
||||
.*: Error: operand mismatch -- `bfmul z0.h,z0.h,z0.b\[2\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmul z0.h, z0.h, z0.h\[2\]
|
||||
.*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfmul z31.h, z31.h, z31.h\[8\]
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]'
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h-z0.h},z0.h\[2\]'
|
||||
.*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
|
||||
.*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfsub z0.h, z0.h, z0.h
|
||||
.*: Error: operand mismatch -- `bfsub z0.s,z0.h,z0.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfsub z0.h, z0.h, z0.h
|
||||
.*: Error: operand mismatch -- `bfsub z0.h,z0.d,z0.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfsub z0.h, z0.h, z0.h
|
||||
.*: Error: operand mismatch -- `bfsub z0.h,z0.h,z0.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfsub z0.h, z0.h, z0.h
|
||||
.*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: bfsub z31.h, z31.h, z31.h
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h'
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h'
|
||||
.*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h'
|
||||
.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h'
|
||||
.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]'
|
||||
.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfmls z1.h,z3.h,z3.h\[7\]'
|
||||
.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z4,z5'
|
||||
.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z2.h,z3.h,z4.h'
|
||||
147
gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
Normal file
147
gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
Normal file
@ -0,0 +1,147 @@
|
||||
bfadd z0.s, p0/m, z0.h, z16.h
|
||||
bfadd z0.h, p0/z, z0.h, z16.h
|
||||
bfadd z0.h, p8/m, z0.h, z16.h
|
||||
bfadd z31.h, p0/m, z0.h, z16.h
|
||||
bfadd z0.h, p0/z, z0.s, z16.h
|
||||
bfadd z0.h, p0/z, z0.h, z16.d
|
||||
bfadd z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmax z0.s, p0/m, z0.h, z16.h
|
||||
bfmax z0.h, p0/z, z0.h, z16.h
|
||||
bfmax z0.h, p8/m, z0.h, z16.h
|
||||
bfmax z31.h, p0/m, z0.h, z16.h
|
||||
bfmax z0.h, p0/z, z0.s, z16.h
|
||||
bfmax z0.h, p0/z, z0.h, z16.d
|
||||
bfmax z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmaxnm z0.s, p0/m, z0.h, z16.h
|
||||
bfmaxnm z0.h, p0/z, z0.h, z16.h
|
||||
bfmaxnm z0.h, p8/m, z0.h, z16.h
|
||||
bfmaxnm z31.h, p0/m, z0.h, z16.h
|
||||
bfmaxnm z0.h, p0/z, z0.s, z16.h
|
||||
bfmaxnm z0.h, p0/z, z0.h, z16.d
|
||||
bfmaxnm z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmin z0.s, p0/m, z0.h, z16.h
|
||||
bfmin z0.h, p0/z, z0.h, z16.h
|
||||
bfmin z0.h, p8/m, z0.h, z16.h
|
||||
bfmin z31.h, p0/m, z0.h, z16.h
|
||||
bfmin z0.h, p0/z, z0.s, z16.h
|
||||
bfmin z0.h, p0/z, z0.h, z16.d
|
||||
bfmin z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfminnm z0.s, p0/m, z0.h, z16.h
|
||||
bfminnm z0.h, p0/z, z0.h, z16.h
|
||||
bfminnm z0.h, p8/m, z0.h, z16.h
|
||||
bfminnm z31.h, p0/m, z0.h, z16.h
|
||||
bfminnm z0.h, p0/z, z0.s, z16.h
|
||||
bfminnm z0.h, p0/z, z0.h, z16.d
|
||||
bfminnm z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmla z0.s, p0/m, z0.h, z16.h
|
||||
bfmla z0.h, p0/z, z0.h, z16.h
|
||||
bfmla z0.h, p8/m, z0.h, z16.h
|
||||
bfmla z31.h, p0/m, z0.h, z16.h
|
||||
bfmla z0.h, p0/z, z0.s, z16.h
|
||||
bfmla z0.h, p0/z, z0.h, z16.d
|
||||
bfmla z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmls z0.s, p0/m, z0.h, z16.h
|
||||
bfmls z0.h, p0/z, z0.h, z16.h
|
||||
bfmls z0.h, p8/m, z0.h, z16.h
|
||||
bfmls z31.h, p0/m, z0.h, z16.h
|
||||
bfmls z0.h, p0/z, z0.s, z16.h
|
||||
bfmls z0.h, p0/z, z0.h, z16.d
|
||||
bfmls z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfmul z0.s, p0/m, z0.h, z16.h
|
||||
bfmul z0.h, p0/z, z0.h, z16.h
|
||||
bfmul z0.h, p8/m, z0.h, z16.h
|
||||
bfmul z31.h, p0/m, z0.h, z16.h
|
||||
bfmul z0.h, p0/z, z0.s, z16.h
|
||||
bfmul z0.h, p0/z, z0.h, z16.d
|
||||
bfmul z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfsub z0.s, p0/m, z0.h, z16.h
|
||||
bfsub z0.h, p0/z, z0.h, z16.h
|
||||
bfsub z0.h, p8/m, z0.h, z16.h
|
||||
bfsub z31.h, p0/m, z0.h, z16.h
|
||||
bfsub z0.h, p0/z, z0.s, z16.h
|
||||
bfsub z0.h, p0/z, z0.h, z16.d
|
||||
bfsub z31.d, p7/m, z31.d, z31.d
|
||||
|
||||
bfadd z0.b, z0.h, z0.h
|
||||
bfadd z31.h, z0.h, z0.h
|
||||
bfadd z0.s, z0.h, z0.h
|
||||
bfadd z0.h, z0.d, z0.h
|
||||
bfadd z0.h, z0.h, z0.b
|
||||
bfadd z31.b, z31.s, z31.d
|
||||
bfadd {z0.h}, z0.h, z0.h
|
||||
bfadd {z0.h - z0.h}, z0.h
|
||||
bfadd z0.h, z0.h
|
||||
|
||||
bfclamp z0.b, z0.h, z0.h
|
||||
bfclamp z31.h, z0.h, z0.h
|
||||
bfclamp z0.s, z0.h, z0.h
|
||||
bfclamp z0.h, z0.d, z0.h
|
||||
bfclamp z0.h, z0.h, z0.b
|
||||
bfclamp z31.b, z31.s, z31.d
|
||||
bfclamp {z0.h}, z0.h, z0.h
|
||||
bfclamp {z0.h - z0.h}, z0.h
|
||||
bfclamp z0.h, z0.h
|
||||
|
||||
bfmla z0.b, z0.h, z0.h[0]
|
||||
bfmla z31.h, z0.h, z0.h[3]
|
||||
bfmla z0.s, z0.h, z0.h[6]
|
||||
bfmla z0.h, z0.d, z0.h[8]
|
||||
bfmla z0.h, z0.h, z0.b[2]
|
||||
bfmla z31.b, z31.s, z31.d[8]
|
||||
bfmla {z0.h}, z0.h, z0.h[1]
|
||||
bfmla {z0.h - z0.h}, z0.h[2]
|
||||
bfmla z0.h, z0.h[3]
|
||||
|
||||
bfmls z0.b, z0.h, z0.h[0]
|
||||
bfmls z31.h, z0.h, z0.h[3]
|
||||
bfmls z0.s, z0.h, z0.h[6]
|
||||
bfmls z0.h, z0.d, z0.h[8]
|
||||
bfmls z0.h, z0.h, z0.b[2]
|
||||
bfmls z31.b, z31.s, z31.d[8]
|
||||
bfmls {z0.h}, z0.h, z0.h[1]
|
||||
bfmls {z0.h - z0.h}, z0.h[2]
|
||||
bfmls z0.h, z0.h[3]
|
||||
|
||||
bfmul z0.b, z0.h, z0.h[0]
|
||||
bfmul z31.h, z0.h, z0.h[3]
|
||||
bfmul z0.s, z0.h, z0.h[6]
|
||||
bfmul z0.h, z0.d, z0.h[8]
|
||||
bfmul z0.h, z0.h, z0.b[2]
|
||||
bfmul z31.b, z31.s, z31.d[8]
|
||||
bfmul {z0.h}, z0.h, z0.h[1]
|
||||
bfmul {z0.h - z0.h}, z0.h[2]
|
||||
bfmul z0.h, z0.h[3]
|
||||
|
||||
bfsub z0.b, z0.h, z0.h
|
||||
bfsub z31.h, z0.h, z0.h
|
||||
bfsub z0.s, z0.h, z0.h
|
||||
bfsub z0.h, z0.d, z0.h
|
||||
bfsub z0.h, z0.h, z0.b
|
||||
bfsub z31.b, z31.s, z31.d
|
||||
bfsub {z0.h}, z0.h, z0.h
|
||||
bfsub {z0.h - z0.h}, z0.h
|
||||
bfsub z0.h, z0.h
|
||||
|
||||
bfmla z0.h, p0/m, z4.h, z16.h
|
||||
movprfx z3, z5
|
||||
bfclamp z1.h, z3.h, z16.h
|
||||
|
||||
movprfx z3, z5
|
||||
bfmla z10.h, z16.h, z3.h[7]
|
||||
|
||||
movprfx z3, z5
|
||||
bfmls z1.h, z3.h, z3.h[7]
|
||||
|
||||
movprfx z2, z3
|
||||
movprfx z4, z5
|
||||
bfclamp z2.h, z3.h, z4.h
|
||||
bfmla z4.h, z5.h, z6.h[7]
|
||||
bfmls z3.h, z1.h, z4.h[7]
|
||||
@ -95,3 +95,6 @@
|
||||
.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
|
||||
.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
|
||||
.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
|
||||
.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
|
||||
.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
|
||||
.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
|
||||
|
||||
@ -1,4 +0,0 @@
|
||||
#name: Test Bfloat16 instructions with wrong operand combinations
|
||||
#as: -march=armv9.4-a
|
||||
#source: bfloat16-invalid.s
|
||||
#error_output: bfloat16-invalid.l
|
||||
@ -1,8 +0,0 @@
|
||||
.*: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
|
||||
@ -1,13 +0,0 @@
|
||||
bfadd z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfmax z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfmaxnm z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfmin z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfminnm z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfmul z0.h, p0/m, z1.h, z0.h
|
||||
|
||||
bfsub z0.h, p0/m, z1.h, z0.h
|
||||
@ -17566,7 +17566,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
|
||||
10987654321098765432109876543210
|
||||
011001x00x1xxxxx000x10xxxxxxxxxx
|
||||
bfmla. */
|
||||
return 3295;
|
||||
return 3292;
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -17585,7 +17585,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
|
||||
10987654321098765432109876543210
|
||||
011001x00x1xxxxx000x11xxxxxxxxxx
|
||||
bfmls. */
|
||||
return 3296;
|
||||
return 3293;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -33782,16 +33782,16 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
|
||||
case 1697: return NULL; /* ldff1b --> NULL. */
|
||||
case 1715: value = 1716; break; /* ldff1h --> ldff1h. */
|
||||
case 1716: return NULL; /* ldff1h --> NULL. */
|
||||
case 2475: value = 3292; break; /* fclamp --> bfclamp. */
|
||||
case 3292: return NULL; /* bfclamp --> NULL. */
|
||||
case 2475: value = 3291; break; /* fclamp --> bfclamp. */
|
||||
case 3291: return NULL; /* bfclamp --> NULL. */
|
||||
case 1789: value = 1790; break; /* ldr --> ldr. */
|
||||
case 1790: return NULL; /* ldr --> NULL. */
|
||||
case 1445: value = 3291; break; /* fadd --> bfadd. */
|
||||
case 3291: return NULL; /* bfadd --> NULL. */
|
||||
case 1512: value = 3293; break; /* fmul --> bfmul. */
|
||||
case 3293: return NULL; /* bfmul --> NULL. */
|
||||
case 1538: value = 3294; break; /* fsub --> bfsub. */
|
||||
case 3294: return NULL; /* bfsub --> NULL. */
|
||||
case 1445: value = 3294; break; /* fadd --> bfadd. */
|
||||
case 3294: return NULL; /* bfadd --> NULL. */
|
||||
case 1512: value = 3295; break; /* fmul --> bfmul. */
|
||||
case 3295: return NULL; /* bfmul --> NULL. */
|
||||
case 1538: value = 3296; break; /* fsub --> bfsub. */
|
||||
case 3296: return NULL; /* bfsub --> NULL. */
|
||||
case 1503: value = 3287; break; /* fmla --> bfmla. */
|
||||
case 3287: return NULL; /* bfmla --> NULL. */
|
||||
case 2008: value = 2009; break; /* str --> str. */
|
||||
|
||||
@ -2782,8 +2782,8 @@ static const aarch64_feature_set aarch64_feature_the =
|
||||
AARCH64_FEATURE (THE);
|
||||
static const aarch64_feature_set aarch64_feature_d128_the =
|
||||
AARCH64_FEATURES (2, D128, THE);
|
||||
static const aarch64_feature_set aarch64_feature_b16b16 =
|
||||
AARCH64_FEATURE (B16B16);
|
||||
static const aarch64_feature_set aarch64_feature_b16b16_sve2 =
|
||||
AARCH64_FEATURES (2, B16B16, SVE2);
|
||||
static const aarch64_feature_set aarch64_feature_sme2p1 =
|
||||
AARCH64_FEATURE (SME2p1);
|
||||
static const aarch64_feature_set aarch64_feature_sve2p1 =
|
||||
@ -2894,7 +2894,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
|
||||
#define D128 &aarch64_feature_d128
|
||||
#define THE &aarch64_feature_the
|
||||
#define D128_THE &aarch64_feature_d128_the
|
||||
#define B16B16 &aarch64_feature_b16b16
|
||||
#define B16B16_SVE2 &aarch64_feature_b16b16_sve2
|
||||
#define SME2p1 &aarch64_feature_sme2p1
|
||||
#define SVE2p1 &aarch64_feature_sve2p1
|
||||
#define RCPC3 &aarch64_feature_rcpc3
|
||||
@ -2991,11 +2991,11 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
|
||||
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
|
||||
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
|
||||
#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
|
||||
#define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
|
||||
FLAGS | F_STRICT, 0, TIED, NULL }
|
||||
#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
|
||||
#define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
|
||||
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
|
||||
#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
|
||||
@ -6597,22 +6597,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
|
||||
|
||||
/* BFloat16 SVE Instructions. */
|
||||
B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
|
||||
B16B16_SVE2_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_SVE2_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_SVE2_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
|
||||
B16B16_SVE2_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_SVE2_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_SVE2_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
|
||||
B16B16_SVE2_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
|
||||
/* SME2.1 movaz instructions. */
|
||||
SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user