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Revert 2 June 1994 changes (Alpha 21164 support), for lack of assignment
paperwork.
This commit is contained in:
Ken Raeburn
parent
8e86815b1c
commit
50c551d06f
@ -86,7 +86,7 @@ Kinds of operands:
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e fa floating point register.
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f fb floating point register.
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g fc floating point register.
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I 26 bit immediate (PALcode function #)
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I 26 bit immediate
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l 16 low bits of immediate
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h 16 high(er) bits of immediate [Never used. KR]
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L 22 bit PC relative immediate.
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@ -173,33 +173,6 @@ static const struct alpha_opcode alpha_opcodes[] =
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{ "stq_c", 0xbc000000, 0, "1,l(2)" },
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{ "stq_c", 0xbc000000, 0, "1,P" }, /* regbase macro */
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{ "ldb", 0, 0, "1,l(2)Bd" },
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{ "ldb", 0, 0, "1,PBd" },
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{ "ldbu", 0, 0, "1,l(2)Bd" },
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{ "ldbu", 0, 0, "1,PBd" },
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{ "ldw", 0, 0, "1,l(2)Bd" },
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{ "ldw", 0, 0, "1,PBd" },
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{ "ldwu", 0, 0, "1,l(2)Bd" },
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{ "ldwu", 0, 0, "1,PBd" },
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{ "stb", 0, 0, "1,l(2)Bd" },
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{ "stb", 0, 0, "1,PBd" },
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{ "stw", 0, 0, "1,l(2)Bd" },
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{ "stw", 0, 0, "1,PBd" },
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{ "ustw", 0, 0, "1,l(2)Bd" },
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{ "ustw", 0, 0, "1,PBd" },
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{ "ustl", 0, 0, "1,l(2)Bd" },
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{ "ustl", 0, 0, "1,PBd" },
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{ "ustq", 0, 0, "1,l(2)Bd" },
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{ "ustq", 0, 0, "1,PBd" },
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{ "uldw", 0, 0, "1,l(2)Bd" },
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{ "uldw", 0, 0, "1,PBd" },
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{ "uldwu", 0, 0, "1,l(2)Bd" },
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{ "uldwu", 0, 0, "1,PBd" },
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{ "uldl", 0, 0, "1,l(2)Bd" },
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{ "uldl", 0, 0, "1,PBd" },
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{ "uldq", 0, 0, "1,l(2)Bd" },
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{ "uldq", 0, 0, "1,PBd" },
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{ "beq", 0xe4000000, 0, "1,L" }, /* 6o+5a+21d */
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{ "bne", 0xf4000000, 0, "1,L" },
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{ "blt", 0xe8000000, 0, "1,L" },
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@ -758,7 +731,7 @@ static const struct alpha_opcode alpha_opcodes[] =
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{ "mult/suid", 0x5800fc40, 1, "e,f,g" },
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/*
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* Miscellaneous, including standard PAL instructions.
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* Miscellaneous
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*/
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{ "pal", 0x00000000, 0, "I" }, /* 6o+26f */
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{ "call_pal", 0x00000000, 0, "I" }, /* alias */
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@ -778,19 +751,8 @@ static const struct alpha_opcode alpha_opcodes[] =
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{ "rs", 0x6000f000, 0, "1" },
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/*
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* More macros
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* PAL instructions
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*/
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{ "nop", 0x47ff041f, 0, "" }, /* or zero,zero,zero */
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{ "mov", 0x47e00400, 0, "2,3" }, /* or zero,r2,r3 */
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};
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#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0]))
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/*
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* PAL instructions for 21064 (and 21066/68)
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*/
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static const struct alpha_opcode alpha_pal21064_opcodes[] =
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{
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{ "hw_ld", 0x6c000000, 0, "1,t(2)" },
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{ "hw_ld/p", 0x6c008000, 0, "1,t(2)" },
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{ "hw_ld/a", 0x6c004000, 0, "1,t(2)" },
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@ -862,42 +824,11 @@ static const struct alpha_opcode alpha_pal21064_opcodes[] =
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{ "hw_mtpr", 0x74000000, 0, "R,8" },
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{ "hw_rei", 0x7bff8000, 0, "" },
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};
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#define NUM21064OPCODES ((sizeof alpha_pal21064_opcodes)/(sizeof alpha_pal21064_opcodes[0]))
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/*
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* 21164 (and 21166/68) specific PAL instructions.
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* More macros
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*/
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static const struct alpha_opcode alpha_pal21164_opcodes[] =
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{
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{ "hw_ld", 0x6c000000, 0, "1,l(2)" }, /* RA, 16 bit displacement (RB) */
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{ "hw_st", 0x7c000000, 0, "1,l(2)" }, /* RA, 16 bit displacement (RB) */
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{ "hw_ldl/a", 0x6c004000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldq/a", 0x6c005000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stl/a", 0x7c004000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stq/a", 0x7c005000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldl/p", 0x6c008000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldq/p", 0x6c009000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stl/p", 0x7c008000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stq/p", 0x7c009000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldq/v", 0x6c001800, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldl/l", 0x6c000400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_ldq/l", 0x6c001400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stl/c", 0x7c000400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_stq/c", 0x7c001400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
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{ "hw_mfpr", 0x64000000, 0, "R,l" }, /* RA,RB,16 bits displacement */
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{ "hw_mtpr", 0x74000000, 0, "R,l" }, /* RA,RB,16 bits displacement */
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{ "hw_rei", 0x7bff8000, 0, "" },
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{ "hw_rei_stall", 0x7bffc000, 0, "" },
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{ "nop", 0x47ff041f, 0, "" }, /* or zero,zero,zero */
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{ "mov", 0x47e00400, 0, "2,3" }, /* or zero,r2,r3 */
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};
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#define NUM21164OPCODES ((sizeof alpha_pal21164_opcodes)/(sizeof alpha_pal21164_opcodes[0]))
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#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0]))
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@ -63,10 +63,6 @@
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/* @@ Will a simple 0x8000 work here? If not, why not? */
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#define GP_ADJUSTMENT (0x8000 - 0x10)
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/* Which machine type is this? Currently stores an integer for the
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model, one of: 21064, 21066, 21164. */
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static unsigned long machine;
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/* These are exported to relaxing code, even though we don't do any
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relaxing on this processor currently. */
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const relax_typeS md_relax_table[1];
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@ -554,72 +550,6 @@ get_lit4_offset (val)
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return retval;
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}
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#define load_insn(NAME, OP) (hash_insert (op_hash, (NAME), (PTR) (OP)))
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static void
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load_insn_table (ops, size)
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struct alpha_opcode *ops;
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int size;
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{
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struct alpha_opcode *end = ops + size;
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struct alpha_opcode *op;
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const char *name;
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for (op = ops; op < end; )
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{
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const char *retval;
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name = op->name;
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retval = load_insn (op->name, op);
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if (retval)
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as_fatal ("internal error: can't hash opcode `%s': %s",
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op->name, retval);
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do
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op++;
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while (op < end
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&& (op->name == name
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|| !strcmp (op->name, name)));
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}
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/* Some opcodes include modifiers of various sorts with a "/mod"
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syntax, like the architecture documentation suggests. However,
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for use with gcc at least, we also need to access those same
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opcodes without the "/". */
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for (op = ops; op < end; )
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{
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name = op->name;
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if (strchr (name, '/'))
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{
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char *name2, *p;
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const char *q;
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name2 = xmalloc (strlen (name));
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p = name2;
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q = name;
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while (*q)
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if (*q == '/')
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q++;
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else
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*p++ = *q++;
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*p = 0;
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/* Ignore failures -- the opcode table does duplicate some
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variants in different forms, like "hw_stq" and "hw_st/q".
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Maybe the variants can be eliminated, and this error checking
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restored. */
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load_insn (name2, op);
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}
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do
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op++;
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while (op < end
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&& (op->name == name
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|| !strcmp (op->name, name)));
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}
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}
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static struct alpha_it clear_insn;
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/* This function is called once, at assembler startup time. It should
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@ -628,26 +558,56 @@ static struct alpha_it clear_insn;
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void
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md_begin ()
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{
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int i;
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const char *retval, *name;
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unsigned int i = 0;
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op_hash = hash_new ();
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load_insn_table (alpha_opcodes, NUMOPCODES);
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/* Default to 21064 PAL instructions. */
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if (machine == 0)
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machine = 21064;
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switch (machine)
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for (i = 0; i < NUMOPCODES; )
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{
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case 21064:
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case 21066:
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load_insn_table (alpha_pal21064_opcodes, NUM21064OPCODES);
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break;
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case 21164:
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load_insn_table (alpha_pal21164_opcodes, NUM21164OPCODES);
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break;
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default:
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as_fatal ("palcode set unknown (internal error)");
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const char *name = alpha_opcodes[i].name;
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retval = hash_insert (op_hash, name, (PTR) &alpha_opcodes[i]);
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if (retval)
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as_fatal ("internal error: can't hash opcode `%s': %s",
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name, retval);
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do
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i++;
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while (i < NUMOPCODES
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&& (alpha_opcodes[i].name == name
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|| !strcmp (alpha_opcodes[i].name, name)));
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}
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/* Some opcodes include modifiers of various sorts with a "/mod"
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syntax, like the architecture documentation suggests. However,
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for use with gcc at least, we also need to access those same
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opcodes without the "/". */
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for (i = 0; i < NUMOPCODES; )
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{
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name = alpha_opcodes[i].name;
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if (strchr (name, '/'))
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{
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char *p = xmalloc (strlen (name));
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const char *q = name;
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char *q2 = p;
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for (; *q; q++)
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if (*q /= '/')
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*q2++ = *q;
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*q2++ = 0;
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retval = hash_insert (op_hash, p, (PTR) &alpha_opcodes[i]);
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/* Ignore failures -- the opcode table does duplicate some
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variants in different forms, like "hw_stq" and "hw_st/q".
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Maybe the variants can be eliminated, and this error
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checking restored. */
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}
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do
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i++;
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while (i < NUMOPCODES
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&& (alpha_opcodes[i].name == name
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|| !strcmp (alpha_opcodes[i].name, name)));
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}
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lituse_basereg.X_op = O_constant;
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@ -2263,31 +2223,6 @@ md_parse_option (c, arg)
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addr32 = 1;
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break;
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case 'm':
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{
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unsigned long mach;
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if (!strcmp (arg, "21064"))
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mach = 21064;
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else if (!strcmp (arg, "21066"))
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mach = 21066;
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else if (!strcmp (arg, "21164"))
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mach = 21164;
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else
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{
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as_bad ("invalid architecture %s", arg);
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return 0;
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}
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if (machine != 0 && machine != mach)
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{
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as_warn ("machine type %lu already chosen, overriding with %lu",
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machine, mach);
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}
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machine = mach;
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}
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break;
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default:
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return 0;
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}
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