mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-29 04:53:56 +08:00
There were several cases where the registers in the REX encoded range
got treated identically to the ones in the base range, due to not
paying attention to the fact that reg_entry's reg_num field doesn't
fully specify the register number (reg_flags also needs to be checked
for RegRex). This patch introduces and uses a new (inline) function to
obtain the full register number, and uses it to fix all those cases.
It additionally adds the missing operand checks for SVME instructions
(which match the monitor/mwait ones).
gas/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (register_number): New function.
(build_vex_prefix, process_immext, process_operands,
build_modrm_byte, i386_index_check): Use it.
gas/testsuite/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* gas/i386/x86-64-specific-reg.{s,l}: New.
* gas/i386/i386.exp: Run new test.
opcodes/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
This commit is contained in:
Jan Beulich
parent
dc1039df63
commit
4c692bc7aa
@ -1,3 +1,9 @@
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2012-08-07 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (register_number): New function.
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(build_vex_prefix, process_immext, process_operands,
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build_modrm_byte, i386_index_check): Use it.
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2012-08-07 Daniel Green <venix1@gmail.com>
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* config/tc-i386.c (lex_got): Provide implementation for PE
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@ -1757,6 +1757,17 @@ operand_type_register_match (i386_operand_type m0,
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return 0;
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}
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static INLINE unsigned int
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register_number (const reg_entry *r)
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{
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unsigned int nr = r->reg_num;
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if (r->reg_flags & RegRex)
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nr += 8;
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return nr;
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}
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static INLINE unsigned int
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mode_from_disp_size (i386_operand_type t)
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{
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@ -2830,12 +2841,7 @@ build_vex_prefix (const insn_template *t)
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/* Check register specifier. */
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if (i.vex.register_specifier)
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{
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register_specifier = i.vex.register_specifier->reg_num;
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if ((i.vex.register_specifier->reg_flags & RegRex))
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register_specifier += 8;
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register_specifier = ~register_specifier & 0xf;
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}
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register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
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else
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register_specifier = 0xf;
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@ -2974,16 +2980,17 @@ process_immext (void)
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{
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expressionS *exp;
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if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
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if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
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&& i.operands > 0)
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{
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/* SSE3 Instructions have the fixed operands with an opcode
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suffix which is coded in the same place as an 8-bit immediate
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field would be. Here we check those operands and remove them
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afterwards. */
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/* MONITOR/MWAIT as well as SVME instructions have fixed operands
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with an opcode suffix which is coded in the same place as an
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8-bit immediate field would be.
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Here we check those operands and remove them afterwards. */
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unsigned int x;
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for (x = 0; x < i.operands; x++)
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if (i.op[x].regs->reg_num != x)
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if (register_number (i.op[x].regs) != x)
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as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
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register_prefix, i.op[x].regs->reg_name, x + 1,
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i.tm.name);
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@ -5071,7 +5078,7 @@ process_operands (void)
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{
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/* The first operand is implicit and must be xmm0. */
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gas_assert (operand_type_equal (&i.types[0], ®xmm));
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if (i.op[0].regs->reg_num != 0)
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if (register_number (i.op[0].regs) != 0)
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return bad_implicit_operand (1);
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if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
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@ -5145,7 +5152,7 @@ duplicate:
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gas_assert (i.reg_operands
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&& (operand_type_equal (&i.types[0], ®xmm)
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|| operand_type_equal (&i.types[0], ®ymm)));
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if (i.op[0].regs->reg_num != 0)
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if (register_number (i.op[0].regs) != 0)
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return bad_implicit_operand (i.types[0].bitfield.regxmm);
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for (j = 1; j < i.operands; j++)
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@ -5348,10 +5355,7 @@ build_modrm_byte (void)
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|| operand_type_equal (&i.tm.operand_types[reg_slot],
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®ymm));
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exp->X_op = O_constant;
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exp->X_add_number
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= ((i.op[reg_slot].regs->reg_num
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+ ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
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<< 4);
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exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
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}
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else
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{
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@ -5395,9 +5399,7 @@ build_modrm_byte (void)
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|| operand_type_equal (&i.tm.operand_types[reg_slot],
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®ymm));
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i.op[imm_slot].imms->X_add_number
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|= ((i.op[reg_slot].regs->reg_num
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+ ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
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<< 4);
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|= register_number (i.op[reg_slot].regs) << 4;
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}
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gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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@ -7413,7 +7415,7 @@ i386_index_check (const char *operand_string)
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? i.base_reg->reg_type.bitfield.reg32
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: i.base_reg->reg_type.bitfield.reg16))
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ok = 0;
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else if (i.base_reg->reg_num != expected)
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else if (register_number (i.base_reg) != expected)
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ok = -1;
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if (ok < 0)
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@ -7428,7 +7430,7 @@ i386_index_check (const char *operand_string)
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: (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
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? i386_regtab[j].reg_type.bitfield.reg32
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: i386_regtab[j].reg_type.bitfield.reg16)
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&& i386_regtab[j].reg_num == expected)
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&& register_number(i386_regtab + j) == expected)
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break;
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gas_assert (j < i386_regtab_size);
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as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
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@ -1,3 +1,8 @@
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2012-08-07 Jan Beulich <jbeulich@suse.com>
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* gas/i386/x86-64-specific-reg.{s,l}: New.
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* gas/i386/i386.exp: Run new test.
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2012-08-07 Nick Clifton <nickc@redhat.com>
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* gas/i386/secrel.s: Add test of <symbol>@SECREL32.
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@ -374,6 +374,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-disp-intel"
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run_dump_test "x86-64-disp32"
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run_dump_test "rexw"
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run_list_test "x86-64-specific-reg"
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run_dump_test "x86-64-fxsave"
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run_dump_test "x86-64-fxsave-intel"
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run_dump_test "x86-64-arch-1"
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376
gas/testsuite/gas/i386/x86-64-specific-reg.l
Normal file
376
gas/testsuite/gas/i386/x86-64-specific-reg.l
Normal file
@ -0,0 +1,376 @@
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.*: Assembler messages:
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.*:[0-9]*: Warning: .*rax.*rsi.*
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.*:[0-9]*: Warning: .*rax.*rdi.*
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.*:[0-9]*: Warning: .*rax.*rdi.*
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.*:[0-9]*: Warning: .*rax.*rdi.*
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.*:[0-9]*: Warning: .*rax.*rsi.*
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.*:[0-9]*: Warning: .*rax.*rbx.*
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.*:[0-9]*: Warning: .*rax.*rsi.*
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.*:[0-9]*: Warning: .*rax.*rdi.*
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.*:[0-9]*: Warning: .*rax.*rdi.*
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.*:[0-9]*: Warning: .*rax.*rsi.*
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.*:[0-9]*: Error: .*rax.* 2 .*mwait.*
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.*:[0-9]*: Error: .*rax.* 2 .*monitor.*
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.*:[0-9]*: Error: .*rax.* 3 .*monitor.*
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.*:[0-9]*: Error: .*eax.* 2 .*invlpga.*
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.*:[0-9]*: Warning: .*rcx.*rsi.*
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.*:[0-9]*: Warning: .*rcx.*rdi.*
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||||
.*:[0-9]*: Warning: .*rcx.*rdi.*
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||||
.*:[0-9]*: Warning: .*rcx.*rdi.*
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||||
.*:[0-9]*: Warning: .*rcx.*rsi.*
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||||
.*:[0-9]*: Warning: .*rcx.*rbx.*
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||||
.*:[0-9]*: Warning: .*rcx.*rsi.*
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||||
.*:[0-9]*: Warning: .*rcx.*rdi.*
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.*:[0-9]*: Warning: .*rcx.*rdi.*
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.*:[0-9]*: Warning: .*rcx.*rsi.*
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.*:[0-9]*: Error: .*rcx.* 1 .*mwait.*
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.*:[0-9]*: Error: .*rcx.* 1 .*monitor.*
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.*:[0-9]*: Error: .*rcx.* 3 .*monitor.*
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.*:[0-9]*: Error: .*rcx.* 1 .*vmload.*
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.*:[0-9]*: Error: .*rcx.* 1 .*vmrun.*
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.*:[0-9]*: Error: .*rcx.* 1 .*vmsave.*
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.*:[0-9]*: Error: .*rcx.* 1 .*invlpga.*
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.*:[0-9]*: Error: .*ecx.* 1 .*skinit.*
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.*:[0-9]*: Warning: .*rdx.*rsi.*
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.*:[0-9]*: Warning: .*rdx.*rdi.*
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.*:[0-9]*: Warning: .*rdx.*rdi.*
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.*:[0-9]*: Warning: .*rdx.*rdi.*
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.*:[0-9]*: Warning: .*rdx.*rsi.*
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.*:[0-9]*: Warning: .*rdx.*rbx.*
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.*:[0-9]*: Warning: .*rdx.*rsi.*
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.*:[0-9]*: Warning: .*rdx.*rdi.*
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.*:[0-9]*: Warning: .*rdx.*rdi.*
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.*:[0-9]*: Warning: .*rdx.*rsi.*
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.*:[0-9]*: Error: .*rdx.* 1 .*mwait.*
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.*:[0-9]*: Error: .*rdx.* 2 .*mwait.*
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.*:[0-9]*: Error: .*rdx.* 1 .*monitor.*
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.*:[0-9]*: Error: .*rdx.* 2 .*monitor.*
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.*:[0-9]*: Error: .*rdx.* 1 .*vmload.*
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.*:[0-9]*: Error: .*rdx.* 1 .*vmrun.*
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.*:[0-9]*: Error: .*rdx.* 1 .*vmsave.*
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.*:[0-9]*: Error: .*rdx.* 1 .*invlpga.*
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.*:[0-9]*: Error: .*edx.* 2 .*invlpga.*
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.*:[0-9]*: Error: .*edx.* 1 .*skinit.*
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||||
.*:[0-9]*: Warning: .*rbx.*rsi.*
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||||
.*:[0-9]*: Warning: .*rbx.*rdi.*
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||||
.*:[0-9]*: Warning: .*rbx.*rdi.*
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||||
.*:[0-9]*: Warning: .*rbx.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbx.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rbx.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rbx.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbx.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbx.*rsi.*
|
||||
.*:[0-9]*: Error: .*rbx.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rbx.* 2 .*mwait.*
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||||
.*:[0-9]*: Error: .*rbx.* 1 .*monitor.*
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||||
.*:[0-9]*: Error: .*rbx.* 2 .*monitor.*
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||||
.*:[0-9]*: Error: .*rbx.* 3 .*monitor.*
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||||
.*:[0-9]*: Error: .*rbx.* 1 .*vmload.*
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||||
.*:[0-9]*: Error: .*rbx.* 1 .*vmrun.*
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||||
.*:[0-9]*: Error: .*rbx.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*rbx.* 1 .*invlpga.*
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||||
.*:[0-9]*: Error: .*ebx.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*ebx.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rbx.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsp.*rsi.*
|
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.*:[0-9]*: Error: .*rsp.* 1 .*mwait.*
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||||
.*:[0-9]*: Error: .*rsp.* 2 .*mwait.*
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.*:[0-9]*: Error: .*rsp.* 1 .*monitor.*
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.*:[0-9]*: Error: .*rsp.* 2 .*monitor.*
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.*:[0-9]*: Error: .*rsp.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rsp.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*rsp.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*rsp.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*rsp.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*esp.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*esp.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rbx.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rbp.*rsi.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rbp.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rbp.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rbp.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*rbp.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*ebp.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*ebp.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rbx.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rdi.*
|
||||
.*:[0-9]*: Warning: .*rsi.*rdi.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rsi.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rsi.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rsi.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*rsi.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*esi.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*esi.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*rdi.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rdi.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rdi.*rbx.*
|
||||
.*:[0-9]*: Warning: .*rdi.*rsi.*
|
||||
.*:[0-9]*: Warning: .*rdi.*rsi.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rdi.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rdi.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rdi.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*rdi.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*edi.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*edi.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r8.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r8.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r8.*rsi.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r8.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r8.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r8.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r8.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r8.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r9.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r9.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r9.*rsi.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r9.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r9.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r9.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r9.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r9.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r10.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r10.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r10.*rsi.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r10.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r10.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r10.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r10.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r10.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r11.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r11.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r11.*rsi.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r11.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r11.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r11.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r11.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r11.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r12.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r12.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r12.*rsi.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r12.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r12.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r12.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r12.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r12.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r13.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r13.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r13.*rsi.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r13.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r13.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r13.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r13.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r13.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r14.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r14.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r14.*rsi.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r14.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r14.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r14.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r14.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r14.* 1 .*skinit.*
|
||||
.*:[0-9]*: Warning: .*r15.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rbx.*
|
||||
.*:[0-9]*: Warning: .*r15.*rsi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rdi.*
|
||||
.*:[0-9]*: Warning: .*r15.*rsi.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r15.* 2 .*mwait.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r15.* 2 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r15.* 3 .*monitor.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*vmload.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*vmrun.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*vmsave.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r15.* 2 .*invlpga.*
|
||||
.*:[0-9]*: Error: .*r15.* 1 .*skinit.*
|
||||
# xmm1
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm2
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm3
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm4
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm5
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm6
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm7
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm8
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm9
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm10
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm11
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm12
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm13
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm14
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
# xmm15
|
||||
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
|
||||
.*:[0-9]*: Error: .*blendvps.*xmm0.*
|
||||
.*:[0-9]*: Error: .*pblendv.*xmm0.*
|
||||
90
gas/testsuite/gas/i386/x86-64-specific-reg.s
Normal file
90
gas/testsuite/gas/i386/x86-64-specific-reg.s
Normal file
@ -0,0 +1,90 @@
|
||||
# 64bit insns with special register requirements
|
||||
|
||||
.text
|
||||
special:
|
||||
.irp reg1, ax, cx, dx, bx, sp, bp, si, di
|
||||
lodsb %ds:(%r\reg1)
|
||||
|
||||
stosb %es:(%r\reg1)
|
||||
|
||||
scasb %es:(%r\reg1)
|
||||
|
||||
insb %dx, %es:(%r\reg1)
|
||||
|
||||
outsb %ds:(%r\reg1), %dx
|
||||
|
||||
xlatb %ds:(%r\reg1)
|
||||
|
||||
movsb %ds:(%r\reg1), %es:(%rdi)
|
||||
movsb %ds:(%rsi), %es:(%r\reg1)
|
||||
|
||||
cmpsb %es:(%r\reg1), %ds:(%rsi)
|
||||
cmpsb %es:(%rdi), %ds:(%r\reg1)
|
||||
|
||||
mwait %r\reg1, %rcx
|
||||
mwait %rax, %r\reg1
|
||||
|
||||
monitor %r\reg1, %rcx, %rdx
|
||||
monitor %rax, %r\reg1, %rdx
|
||||
monitor %rax, %rcx, %r\reg1
|
||||
|
||||
# FIXME: Need to ensure only "vmload %[re]ax" is accepted.
|
||||
vmload %r\reg1
|
||||
|
||||
# FIXME: Need to ensure only "vmrun %[re]ax" is accepted.
|
||||
vmrun %r\reg1
|
||||
|
||||
# FIXME: Need to ensure only "vmsave %[re]ax" is accepted.
|
||||
vmsave %r\reg1
|
||||
|
||||
# FIXME: Need to ensure only "invlpga %[re]ax,%ecx" is accepted.
|
||||
invlpga %r\reg1, %ecx
|
||||
invlpga %rax, %e\reg1
|
||||
|
||||
# FIXME: Need to ensure only "skinit %eax" is accepted.
|
||||
skinit %e\reg1
|
||||
.endr
|
||||
|
||||
.irp reg1, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
lodsb %ds:(%r\reg1)
|
||||
|
||||
stosb %es:(%r\reg1)
|
||||
|
||||
scasb %es:(%r\reg1)
|
||||
|
||||
insb %dx, %es:(%r\reg1)
|
||||
|
||||
outsb %ds:(%r\reg1), %dx
|
||||
|
||||
xlatb %ds:(%r\reg1)
|
||||
|
||||
movsb %ds:(%r\reg1), %es:(%rdi)
|
||||
movsb %ds:(%rsi), %es:(%r\reg1)
|
||||
|
||||
cmpsb %es:(%r\reg1), %ds:(%rsi)
|
||||
cmpsb %es:(%rdi), %ds:(%r\reg1)
|
||||
|
||||
mwait %r\reg1, %rcx
|
||||
mwait %rax, %r\reg1
|
||||
|
||||
monitor %r\reg1, %rcx, %rdx
|
||||
monitor %rax, %r\reg1, %rdx
|
||||
monitor %rax, %rcx, %r\reg1
|
||||
|
||||
vmload %r\reg1
|
||||
|
||||
vmrun %r\reg1
|
||||
|
||||
vmsave %r\reg1
|
||||
|
||||
invlpga %r\reg1, %ecx
|
||||
invlpga %rax, %r\reg1\(d)
|
||||
|
||||
skinit %r\reg1\(d)
|
||||
.endr
|
||||
|
||||
.irp n, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
blendvpd %xmm\n, %xmm\n, %xmm\n
|
||||
blendvps %xmm\n, %xmm\n, %xmm\n
|
||||
pblendvb %xmm\n, %xmm\n, %xmm\n
|
||||
.endr
|
||||
@ -1,3 +1,7 @@
|
||||
2012-08-07 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
|
||||
|
||||
2012-08-06 Roland McGrath <mcgrathr@google.com>
|
||||
|
||||
* i386-dis.c (print_insn): Print spaces between multiple excess
|
||||
|
||||
@ -3004,21 +3004,16 @@ rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No
|
||||
// AMD Pacifica additions.
|
||||
clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
invlpga, 0, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// FIXME: Need to ensure only "invlpga %[re]ax,%ecx" is accepted.
|
||||
invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg32 }
|
||||
skinit, 0, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// FIXME: Need to ensure only "skinit %eax" is accepted.
|
||||
skinit, 1, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Reg32 }
|
||||
stgi, 0, 0xf01, 0xdc, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
vmload, 0, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// FIXME: Need to ensure only "vmload %[re]ax" is accepted.
|
||||
vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
|
||||
vmmcall, 0, 0xf01, 0xd9, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
vmrun, 0, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// FIXME: Need to ensure only "vmrun %[re]ax" is accepted.
|
||||
vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
|
||||
vmsave, 0, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// FIXME: Need to ensure only "vmsave %[re]ax" is accepted.
|
||||
vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user