mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-28 04:25:10 +08:00
gas/
2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (vex_imm4): Removed. (VEX_check_operands): Likewise. (match_template): Updated. opcodes/ 2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4. (operand_types): Remove Vex_Imm4. * i386-opc.h (Vex_Imm4): Removed. (OTMax): Updated. (i386_operand_type): Remove vex_imm4. * i386-opc.tbl: Remove Vex_Imm4 comments. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
7bcbeb0f1c
commit
4c664d7bf7
@ -1,3 +1,9 @@
|
||||
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* config/tc-i386.c (vex_imm4): Removed.
|
||||
(VEX_check_operands): Likewise.
|
||||
(match_template): Updated.
|
||||
|
||||
2009-02-23 Martin Schwidefsky <schwidefsky@de.ibm.com>
|
||||
|
||||
* doc/all.texi: Set S390.
|
||||
|
||||
@ -1398,7 +1398,6 @@ static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
|
||||
static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
|
||||
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
|
||||
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
|
||||
static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
|
||||
|
||||
enum operand_type
|
||||
{
|
||||
@ -3572,29 +3571,6 @@ optimize_disp (void)
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if operands are valid for the instrucrtion. Update VEX
|
||||
operand types. */
|
||||
|
||||
static int
|
||||
VEX_check_operands (const template *t)
|
||||
{
|
||||
if (!t->opcode_modifier.vex)
|
||||
return 0;
|
||||
|
||||
/* Only check VEX_Imm4, which must be the first operand. */
|
||||
if (t->operand_types[0].bitfield.vex_imm4)
|
||||
{
|
||||
if (i.op[0].imms->X_op != O_constant
|
||||
|| !fits_in_imm4 (i.op[0].imms->X_add_number))
|
||||
return 1;
|
||||
|
||||
/* Turn off Imm8 so that update_imm won't complain. */
|
||||
i.types[0] = vex_imm4;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const template *
|
||||
match_template (void)
|
||||
{
|
||||
@ -3899,10 +3875,6 @@ check_reverse:
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Check if VEX operands are valid. */
|
||||
if (VEX_check_operands (t))
|
||||
continue;
|
||||
|
||||
/* We've found a match; break out of loop. */
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1,3 +1,16 @@
|
||||
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
|
||||
(operand_types): Remove Vex_Imm4.
|
||||
|
||||
* i386-opc.h (Vex_Imm4): Removed.
|
||||
(OTMax): Updated.
|
||||
(i386_operand_type): Remove vex_imm4.
|
||||
|
||||
* i386-opc.tbl: Remove Vex_Imm4 comments.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2009-02-23 Richard Earnshaw <rearnsha@arm.com>
|
||||
|
||||
* arm-dis.c (neon_opcodes): Correct bit-mask and patterns for
|
||||
|
||||
@ -234,8 +234,6 @@ static initializer operand_type_init[] =
|
||||
"Imm32|Imm32S|Imm64|Disp32" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
|
||||
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
|
||||
{ "OPERAND_TYPE_VEX_IMM4",
|
||||
"VEX_Imm4" },
|
||||
};
|
||||
|
||||
typedef struct bitfield
|
||||
@ -396,7 +394,6 @@ static bitfield operand_types[] =
|
||||
BITFIELD (Ymmword),
|
||||
BITFIELD (Unspecified),
|
||||
BITFIELD (Anysize),
|
||||
BITFIELD (Vex_Imm4),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
|
||||
@ -215,234 +215,229 @@
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_VEX_IMM4 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
@ -447,11 +447,8 @@ typedef struct i386_opcode_modifier
|
||||
/* Any memory size. */
|
||||
#define Anysize (Unspecified + 1)
|
||||
|
||||
/* VEX 4 bit immediate */
|
||||
#define Vex_Imm4 (Anysize + 1)
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
#define OTMax Vex_Imm4
|
||||
#define OTMax Anysize
|
||||
|
||||
#define OTNumOfUints \
|
||||
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
@ -510,7 +507,6 @@ typedef union i386_operand_type
|
||||
unsigned int ymmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
unsigned int vex_imm4:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
||||
@ -1767,9 +1767,6 @@ pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSu
|
||||
|
||||
// AVX instructions.
|
||||
|
||||
// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand
|
||||
// is an immediate. We will check if its value will fit 4 bits.
|
||||
|
||||
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
11240
opcodes/i386-tbl.h
11240
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user