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x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
3a5d12fbb4
commit
4b5aaf5f69
@ -1,3 +1,16 @@
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2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25516
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* config/tc-i386.c (intel64): Renamed to ...
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(isa64): This.
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(match_template): Accept Intel64 only instruction by default.
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(i386_displacement): Updated.
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(md_parse_option): Updated.
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* c-i386.texi: Update -mamd64/-mintel64 documentation.
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* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
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-mamd64 to x86-64-sysenter-amd.
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* testsuite/gas/i386/x86-64-sysenter.d: New file.
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2020-02-10 Alan Modra <amodra@gmail.com>
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* config/obj-elf.c (obj_elf_change_section): Error for section
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@ -598,9 +598,11 @@ static int shared = 0;
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0 if att syntax. */
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static int intel_syntax = 0;
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/* 1 for Intel64 ISA,
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0 if AMD64 ISA. */
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static int intel64;
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static enum x86_64_isa
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{
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amd64 = 1, /* AMD64 ISA. */
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intel64 /* Intel64 ISA. */
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} isa64;
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/* 1 for intel mnemonic,
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0 if att mnemonic. */
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@ -5805,14 +5807,32 @@ match_template (char mnem_suffix)
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if (intel_mnemonic && t->opcode_modifier.attmnemonic)
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continue;
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/* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
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/* Check AT&T/Intel syntax. */
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i.error = unsupported_syntax;
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if ((intel_syntax && t->opcode_modifier.attsyntax)
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|| (!intel_syntax && t->opcode_modifier.intelsyntax)
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|| (intel64 && t->opcode_modifier.amd64)
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|| (!intel64 && t->opcode_modifier.intel64))
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|| (!intel_syntax && t->opcode_modifier.intelsyntax))
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continue;
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/* Check Intel64/AMD64 ISA. */
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switch (isa64)
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{
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default:
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/* Default: Don't accept Intel64. */
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if (t->opcode_modifier.isa64 == INTEL64)
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continue;
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break;
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case amd64:
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/* -mamd64: Don't accept Intel64 and Intel64 only. */
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if (t->opcode_modifier.isa64 >= INTEL64)
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continue;
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break;
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case intel64:
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/* -mintel64: Don't accept AMD64. */
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if (t->opcode_modifier.isa64 == AMD64)
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continue;
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break;
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}
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/* Check the suffix. */
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i.error = invalid_instruction_suffix;
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if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
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@ -9963,7 +9983,7 @@ i386_displacement (char *disp_start, char *disp_end)
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if (t->opcode_modifier.jump
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!= current_templates->start->opcode_modifier.jump)
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break;
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if (t->opcode_modifier.intel64)
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if ((t->opcode_modifier.isa64 >= INTEL64))
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has_intel64 = TRUE;
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}
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if (t < current_templates->end)
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@ -12525,11 +12545,11 @@ md_parse_option (int c, const char *arg)
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break;
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case OPTION_MAMD64:
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intel64 = 0;
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isa64 = amd64;
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break;
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case OPTION_MINTEL64:
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intel64 = 1;
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isa64 = intel64;
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break;
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case 'O':
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@ -488,7 +488,8 @@ with 01, 10 and 11 RC bits, respectively.
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@item -mamd64
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@itemx -mintel64
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This option specifies that the assembler should accept only AMD64 or
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Intel64 ISA in 64-bit mode. The default is to accept both.
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Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
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only and AMD64 ISAs.
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@cindex @samp{-O0} option, i386
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@cindex @samp{-O0} option, x86-64
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@ -728,10 +728,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-nops-5"
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run_dump_test "x86-64-nops-5-k8"
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run_dump_test "x86-64-nops-7"
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run_dump_test "x86-64-sysenter"
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run_dump_test "x86-64-sysenter-intel"
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run_dump_test "x86-64-sysenter-mixed"
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run_dump_test "x86-64-sysenter-amd"
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run_list_test "x86-64-sysenter-amd"
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run_list_test "x86-64-sysenter-amd" "-mamd64"
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run_dump_test "noreg64"
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run_list_test "noreg64"
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run_list_test "cvtsi2sX"
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5
gas/testsuite/gas/i386/x86-64-sysenter.d
Normal file
5
gas/testsuite/gas/i386/x86-64-sysenter.d
Normal file
@ -0,0 +1,5 @@
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#as:
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#objdump: -dw
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#name: x86-64 sysenter (Default)
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#source: x86-64-sysenter-amd.s
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#dump: x86-64-sysenter-intel.d
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@ -1,3 +1,21 @@
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2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25516
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* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
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with ISA64.
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* i386-opc.h (AMD64): Removed.
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(Intel64): Likewose.
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(AMD64): New.
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(INTEL64): Likewise.
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(INTEL64ONLY): Likewise.
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(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
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* i386-opc.tbl (Amd64): New.
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(Intel64): Likewise.
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(Intel64Only): Likewise.
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Replace AMD64 with Amd64. Update sysenter/sysenter with
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Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
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* i386-tbl.h: Regenerated.
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2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25469
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@ -666,8 +666,7 @@ static bitfield opcode_modifiers[] =
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BITFIELD (ATTMnemonic),
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BITFIELD (ATTSyntax),
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BITFIELD (IntelSyntax),
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BITFIELD (AMD64),
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BITFIELD (Intel64),
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BITFIELD (ISA64),
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};
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#define CLASS(n) #n, n
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@ -638,10 +638,16 @@ enum
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ATTSyntax,
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/* Intel syntax. */
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IntelSyntax,
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/* AMD64. */
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AMD64,
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/* Intel64. */
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Intel64,
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/* ISA64: Don't change the order without other code adjustments.
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0: Common to AMD64 and Intel64.
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1: AMD64.
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2: Intel64.
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3: Only in Intel64.
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*/
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#define AMD64 1
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#define INTEL64 2
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#define INTEL64ONLY 3
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ISA64,
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/* The last bitfield in i386_opcode_modifier. */
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Opcode_Modifier_Num
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};
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@ -705,8 +711,7 @@ typedef struct i386_opcode_modifier
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unsigned int attmnemonic:1;
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unsigned int attsyntax:1;
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unsigned int intelsyntax:1;
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unsigned int amd64:1;
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unsigned int intel64:1;
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unsigned int isa64:2;
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} i386_opcode_modifier;
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/* Operand classes. */
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@ -22,6 +22,10 @@
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#include "i386-opc.h"
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#undef None
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#define Amd64 ISA64=AMD64
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#define Intel64 ISA64=INTEL64
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#define Intel64Only ISA64=INTEL64ONLY
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#define Reg8 Class=Reg|Byte
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#define Reg16 Class=Reg|Word
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#define Reg32 Class=Reg|Dword
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@ -136,7 +140,7 @@ movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
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movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
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movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 }
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movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
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movsxd, 2, 0x63, None, 1, Cpu64, AMD64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
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movsxd, 2, 0x63, None, 1, Cpu64, Amd64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
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movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
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// Move with zero extend.
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@ -373,10 +377,10 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
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// Control transfer instructions.
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call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
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call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
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call, 1, 0xe8, None, 1, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
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call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
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call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
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call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
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call, 1, 0xff, 0x2, 1, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
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call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
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// Intel Syntax
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call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
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@ -386,10 +390,10 @@ lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|N
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lcall, 1, 0xff, 0x3, 1, 0, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
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jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
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jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
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jmp, 1, 0xeb, None, 1, Cpu64, Amd64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
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jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
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jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
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jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
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jmp, 1, 0xff, 0x4, 1, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
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jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
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// Intel Syntax.
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jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
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@ -400,8 +404,8 @@ ljmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {
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ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
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ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
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ret, 0, 0xc3, None, 1, Cpu64, AMD64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
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ret, 1, 0xc2, None, 1, Cpu64, AMD64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
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ret, 0, 0xc3, None, 1, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
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ret, 1, 0xc2, None, 1, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
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ret, 0, 0xc3, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
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ret, 1, 0xc2, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
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lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
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@ -909,10 +913,10 @@ rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
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cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|IsLockable|NoRex64|HLEPrefixOk, { Qword|Unspecified|BaseIndex }
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// Pentium II/Pentium Pro extensions.
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sysenter, 0, 0xf34, None, 2, Cpu686, Intel64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysenter, 0, 0xf34, None, 2, Cpu686|CpuNo64, AMD64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686, Intel64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686|CpuNo64, AMD64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysenter, 0, 0xf34, None, 2, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysenter, 0, 0xf34, None, 2, Cpu686|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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fxsave, 1, 0xfae, 0x0, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
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fxsave64, 1, 0xfae, 0x0, 2, CpuFXSR|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex }
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fxrstor, 1, 0xfae, 0x1, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
|
||||
|
||||
7858
opcodes/i386-tbl.h
7858
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue
Block a user