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* gencode.c (process_instructions): Correct shift count for 32
bit shift instructions. Correct sign extension for arithmetic shifts to not shift the number of bits in the type.
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@ -1,7 +1,9 @@
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Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
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* gencode.c (process_instructions): Correct handling of nor
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instruction.
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instruction. Correct shift count for 32 bit shift instructions.
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Correct sign extension for arithmetic shifts to not shift the
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number of bits in the type.
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Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
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@ -1134,7 +1134,7 @@ process_instructions(doarch,features)
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/* If HI32 specified, then shift range is 32..63 */
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if (MIPS_DECODE[loop].flags & HI32)
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printf(" op1 |= (1 << 6);\n");
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printf(" op1 |= (1 << 5);\n");
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/* We do not need to perform pre-masking with 0xFFFFFFFF when
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dealing with 32bit shift lefts, since the sign-extension
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@ -1144,9 +1144,12 @@ process_instructions(doarch,features)
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else
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printf(" GPR[destreg] = ((uword64)(op2%s) >> op1);\n",((bits == 32) ? " & 0xFFFFFFFF" : ""));
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/* For ARITHMETIC shifts, we must duplicate the sign-bit */
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/* For ARITHMETIC shifts, we must duplicate the sign-bit. We
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don't do this if op1 is zero, since it is not needed and
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since that would cause an undefined shift of the number of
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bits in the type. */
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if (MIPS_DECODE[loop].flags & ARITHMETIC)
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printf(" GPR[destreg] |= ((op2 & ((%s)1 << %d)) ? ((((%s)1 << (op1 + 1)) - 1) << (%d - op1)) : 0);\n",ltype,(bits - 1),ltype,(bits - 1));
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printf(" GPR[destreg] |= (op1 != 0 && (op2 & ((%s)1 << %d)) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,(bits - 1),ltype,bits);
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/* Ensure WORD values are sign-extended into 64bit registers */
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if ((bits == 32) && (gprlen == 64))
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