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gas: Implement categorization of Morello-specific instructions
While the concept of a core instruction relates to the idea of instructions that are available irrespective of the presence of architectural extensions, this concept breaks down with the introduction of the Morello architecture. Rather, what is observed in Morello is that when PSTATE.C64 == 1, the A64C_INSN variant becomes the ONLY valid aarch64_opcode variant, with the CORE_INSN variant becoming illegal. Therefore, some way of ruling out the use of such CORE_INSNs is needed. Similarly, some A64C_INSN instructions are only valid for PSTATE.C64 == 1 and are not valid when compiling for Morello A64 mode. At the assembly level, the CORE_INSN and A64C_INSN variants share the same mnemonic, differing only by whether they are passed a general- purpose register argument or its capability counterpart, e.g. * CORE_INSN: adr x0, #0 * A64C_INSN: adr c0, #0 This makes the prospect of combining both insn variants in binutils into a single insn entry in aarch64_opcode_table[], resolving the appropriate operand code (e.g. AARCH64_OPND_Can versus AARCH64_OPND_Rn) at compile time by analyzing the -march and -mabi flags. This approach falls short when dealing with instructions such as `bl' where the core and morello instructions share the same mnemonic but have distinct encodings. A more flexible approach is therefore presented here. Special restrictions to instructions are encoded in the FLAGS field, which can then be used in checks carried out in `md_assemble'. This fixes two issues: 1. Wrong fix suggestions in `output_operand_error_record': - attempting to assemble `adr w0, #0' at present, for example, results in a suggestion that `w0' be changed to `x0' as opposed to `c0'. 2. Purecap only instructions being accepted when assembling without the C64 extension: - `adr c0, #0' is currently accepted when assembling for Hybrid mode. This patch defines the F_NONC64 and F_C64ONLY flags for labellig these instructions in aarch64_opcode.flags, such that unavailable instructions could be identified by cross-referencing this field along with whether C64 is set in the `cpu_variant' aarch64_feature_set variable. When the conditions set by the flag is not met by `cpu_variant', the instruction can be attributed a AARCH64_OPDE_SYNTAX_ERROR, allowing for correct error handling in md_assemble. ChangeLog: * include/opcode/aarch64.h (F_NONC64): New flag. * include/opcode/aarch64.h (F_C64ONLY): Likewise. opcodes/ChangeLog: * aarch64-tbl.h (aarch64_opcode_table): Add F_NONC64 and F_C64ONLY to relevant aarch64_opcodes gas/ChangeLog: * config/tc-aarch64.c (validate_opcode_for_feature): New. (md_assemble): Use `validate_opcode_for_feature' in template selection. * gas/testsuite/gas/aarch64/morello-exclude.l: New testcase. * gas/testsuite/gas/aarch64/morello-exclude.s: Likewise. * gas/testsuite/gas/aarch64/morello-exclude.l: Likewise. * gas/testsuite/gas/aarch64/morello_insn.s: Fix hybrid codegen.
This commit is contained in:
Victor Do Nascimento
parent
f103ba71c7
commit
459784def0
@ -7642,6 +7642,36 @@ dump_opcode_operands (const aarch64_opcode *opcode)
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}
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#endif /* DEBUG_AARCH64 */
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/* With the introduction of Morello, some CORE_INSNs are no longer
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valid if IS_C64 is true. It is important that such instructions
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are no longer treated as core in such contexts and are
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disconsidered, rather being treated as belonging to any other
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unavailable architectural extension. Likewise, reject purecap-specific
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instructions when assembling for hybrid (or any other) tartgets. */
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static bfd_boolean
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validate_opcode_for_feature (const aarch64_opcode *opcode,
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aarch64_feature_set features)
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{
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/* If opcode is memory-related, Ensure this CPU does not impose any
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restriction on allowed operands. */
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if (opcode->flags & F_NONC64
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&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_C64))
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{
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set_default_error ();
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return FALSE;
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}
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/* Reject purecap-specific instructions when assembling for any other
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target. */
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if (opcode->flags & F_C64ONLY
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&& !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_C64)))
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{
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set_default_error ();
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return FALSE;
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}
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return TRUE;
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}
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/* This is the guts of the machine-dependent assembler. STR points to a
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machine dependent instruction. This function is supposed to emit
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the frags/bytes it assembles to. */
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@ -7736,7 +7766,8 @@ md_assemble (char *str)
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continue;
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}
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if (parse_operands (p, opcode)
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if (validate_opcode_for_feature (opcode, cpu_variant)
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&& parse_operands (p, opcode)
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&& programmer_friendly_fixup (&inst)
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&& do_encode (inst_base->opcode, &inst.base, &inst_base->value))
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{
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4
gas/testsuite/gas/aarch64/morello-exclude.d
Normal file
4
gas/testsuite/gas/aarch64/morello-exclude.d
Normal file
@ -0,0 +1,4 @@
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#name: Morello opcode filter
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#as: -march=morello+c64 -mabi=purecap
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#source: morello-exclude.s
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#error_output: morello-exclude.l
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9
gas/testsuite/gas/aarch64/morello-exclude.l
Normal file
9
gas/testsuite/gas/aarch64/morello-exclude.l
Normal file
@ -0,0 +1,9 @@
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[^:]+: Assembler messages:
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `adr w0,#0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `adr x0,#0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `adrp w0,#0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `adrp x0,#0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `blr w0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `blr x0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `ret w0'
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[^:]+:[0-9]+: Error: operand 1 must be a Capability register -- `ret x0'
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8
gas/testsuite/gas/aarch64/morello-exclude.s
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8
gas/testsuite/gas/aarch64/morello-exclude.s
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@ -0,0 +1,8 @@
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adr w0, #0
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adr x0, #0
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adrp w0, #0
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adrp x0, #0
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blr w0
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blr x0
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ret w0
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ret x0
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@ -72,7 +72,12 @@ Label:
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\op \cd, Label
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.endr
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.endm
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morello_adrx c0
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.ifdef C64MODE
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morello_adrx c0
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.else
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morello_adrx x0
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.endif
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.ifdef C64MODE
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adrdp c0, #4096
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@ -969,7 +969,13 @@ extern aarch64_opcode aarch64_opcode_table[];
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#define F_SCAN (1ULL << 31)
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/* Do no shift immediate operand. */
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#define F_NOSHIFT (1ULL << 32)
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/* Next bit is 33. */
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/* Opcode variant is invalidated by PSTATE.C64. When PSTATE.C64 == 1, operation
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requires use of capability operands. */
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#define F_NONC64 (1ULL << 33)
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/* Opcode vatiant not suitable for morello hybrid mode and will fail unless
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PSTATE.C64 == 1. */
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#define F_C64ONLY (1ULL << 34)
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/* Next bit is 35. */
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/* Instruction constraints. */
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/* This instruction has a predication constraint on the instruction at PC+4. */
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@ -3395,9 +3395,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, 0),
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CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, 0),
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/* Unconditional branch (register). */
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CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0),
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CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0),
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CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)),
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CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_NONC64),
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CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_NONC64),
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CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30) | F_NONC64),
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CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
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CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
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V8_3_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
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@ -3986,10 +3986,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),
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CORE_INSN ("movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, OP2 (Rd, HALF), QL_DST_R, F_SF),
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/* PC-rel. addressing. */
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CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
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CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
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CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP,F_NONC64),
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CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, F_NONC64),
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/* Pc-rel. addressing with capabilities. */
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A64C_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Cad, ADDR_PCREL21), QL2_A64C_CA_NIL, 0),
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A64C_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Cad, ADDR_PCREL21), QL2_A64C_CA_NIL, F_C64ONLY),
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A64C_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Cad, ADDR_ADRP), QL2_A64C_CA_NIL, 0),
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A64C_INSN ("adrdp", 0x90000000, 0x9f800000, pcreladdr, 0, OP2 (Cad, A64C_ADDR_ADRDP), QL2_A64C_CA_NIL, 0),
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/* A64C Instructions. */
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