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gprofng: add hardware counters for Appliedmicro processor
gprofng/ChangeLog 2024-08-15 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>. * common/hwc_cpus.h: New constant for Appliedmicro processor. * common/hwctable.c: Add the hwc table for Appliedmicro processor. * src/hhwc_arm64_amcc.h: New file. * src/collctrl.cc (read_int): Use strtol instead of atoi.
This commit is contained in:
Vladimir Mezentsev
parent
1b32f601b1
commit
4456cb827f
@ -128,6 +128,10 @@ extern cpu_info_t *read_cpuinfo();
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#define CPC_SPARC64_X 4006 /* Athena */
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#define CPC_SPARC64_XII 4010 /* Athena++ */
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// Arm
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#define CPC_ARM_GENERIC 3500
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#define CPC_ARM64_AMCC 3501 /* Applied Micro Circuits Corporation (ARM) */
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#define AMD_FAM_19H_ZEN3_NAME "AMD Family 19h (Zen3)"
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#define AMD_FAM_19H_ZEN4_NAME "AMD Family 19h (Zen4)"
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@ -243,6 +243,7 @@ static Hwcentry papi_generic_list[] = {
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{NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
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};
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#if defined(__i386__) || defined(__x86_64)
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/* Kernel profiling pseudo-chip, OBSOLETE (To support 12.3 and earlier, TBR) */
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static Hwcentry kproflist[] = {
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{"kcycles", "kcycles", 0, STXT ("KCPU Cycles"), PRELOADS_5, 1, ABST_NONE},
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@ -1215,6 +1216,7 @@ static Hwcentry amd_15h[] = {
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{"insts1", "EX_retired_instr_w_excp_intr", 1, NULL, PRELOADS_8, 0, ABST_NONE},
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{NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
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};
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#endif /* __i386__ or __x86_64 */
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#define INIT_HWC(nm, mtr, cfg, ty) .name = (nm), .metric = (mtr), \
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.config = (cfg), .type = ty, .use_perf_event_type = 1, \
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@ -1296,15 +1298,18 @@ static Hwcentry amd_15h[] = {
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{ HWCE("iTLB-loads", STXT("The Instruction TLB Loads"),\
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PERF_COUNT_HW_CACHE_ITLB,\
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PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
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static Hwcentry generic_list[] = {
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HWC_GENERIC
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{NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
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};
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#include "hwc_amd_zen3.h"
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#include "hwc_amd_zen4.h"
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#include "hwc_intel_icelake.h"
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#if defined(__i386__) || defined(__x86_64)
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#include "hwc_amd_zen3.h"
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#include "hwc_amd_zen4.h"
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#include "hwc_intel_icelake.h"
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#elif defined(__aarch64__)
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#include "hwc_arm64_amcc.h"
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#endif
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/* structure defining the counters for a CPU type */
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typedef struct
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@ -1325,6 +1330,7 @@ typedef struct
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* If the string is not formatted that way, -h hi and -h lo will fail
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*/
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static cpu_list_t cputabs[] = {
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#if defined(__i386__) || defined(__x86_64)
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{CPC_PENTIUM_PRO_MMX, pentiumIIlist, {"insts", 0}},
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{CPC_PENTIUM_PRO, pentiumIIIlist, {"insts", 0}},
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{CPC_PENTIUM_4, pentium4, {"insts", 0}},
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@ -1353,10 +1359,13 @@ static cpu_list_t cputabs[] = {
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{CPC_AMD_FAM_11H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
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{CPC_AMD_FAM_15H, amd_15h, {"insts,,cycles", 0}},
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{CPC_KPROF, kproflist, {NULL}}, // OBSOLETE (To support 12.3 and earlier, TBR)
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{ARM_CPU_IMP_APM, generic_list, {"insts,,cycles", 0}},
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{CPC_AMD_Authentic, generic_list, {"insts,,cycles", 0}},
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{CPC_AMD_FAM_19H_ZEN3, amd_zen3_list, {"insts,,cycles", 0}},
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{CPC_AMD_FAM_19H_ZEN4, amd_zen4_list, {"insts,,cycles", 0}},
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#elif defined(__aarch64__)
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{CPC_ARM64_AMCC, arm64_amcc_list, {"insts,,cycles", 0}},
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{CPC_ARM_GENERIC, generic_list, {"insts,,cycles", 0}},
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#endif
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{0, generic_list, {"insts,,cycles", 0}},
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};
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@ -1856,6 +1865,13 @@ setup_cpc_general (int skip_hwc_test)
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cpcx_cpuver = CPC_INTEL_ICELAKE;
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}
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}
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else if (strcmp (cpu_p->cpu_vendorstr, AARCH64_VENDORSTR_ARM) == 0)
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{
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if (cpu_p->cpu_family == 0x50)
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cpcx_cpuver = CPC_ARM64_AMCC;
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else
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cpcx_cpuver = CPC_ARM_GENERIC;
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}
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#ifdef DISALLOW_PENTIUM_PRO_MMX_7007575
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if (cpcx_cpuver == CPC_PENTIUM_PRO_MMX)
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@ -77,7 +77,7 @@ read_int (char *from)
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{
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char *val = strchr (from, ':');
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if (val)
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return atoi (val + 1);
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return (int) strtol (val + 1, NULL, 0);
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return 0;
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}
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@ -130,7 +130,11 @@ read_cpuinfo ()
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fclose (procf);
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}
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if (cpu_info.cpu_vendorstr == NULL)
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#if defined(__aarch64__)
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cpu_info.cpu_vendorstr = strdup (AARCH64_VENDORSTR_ARM);
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#else
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cpu_info.cpu_vendorstr = GTXT ("Unknown processor");
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#endif
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if (cpu_info.cpu_modelstr == NULL)
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cpu_info.cpu_modelstr = GTXT ("Unknown cpu model");
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return &cpu_info;
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182
gprofng/src/hwc_arm64_amcc.h
Normal file
182
gprofng/src/hwc_arm64_amcc.h
Normal file
@ -0,0 +1,182 @@
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/* Copyright (C) 2024 Free Software Foundation, Inc.
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Contributed by Oracle.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef _HWC_ARM64_AMCC_H
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#define _HWC_ARM64_AMCC_H
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#define I(nm, event, mtr) INIT_HWC(nm, mtr, (event), PERF_TYPE_RAW)
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static Hwcentry arm64_amcc_list[] = {
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HWC_GENERIC
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/* branch: */
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{ I("br_immed_spec", 0x78,
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STXT("Branch speculatively executed, immediate branch")) },
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{ I("br_indirect_spec", 0x7a,
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STXT("Branch speculatively executed, indirect branch")) },
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{ I("br_mis_pred", 0x10, STXT("Branch mispredicted")) },
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{ I("br_pred", 0x12, STXT("Predictable branch")) },
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{ I("br_return_spec", 0x79,
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STXT("Branch speculatively executed, procedure return")) },
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/* bus: */
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{ I("bus_access", 0x19, STXT("Attributable Bus access")) },
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{ I("bus_access_normal", 0x64, STXT("Bus access, Normal")) },
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{ I("bus_access_not_shared", 0x63,
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STXT("Bus access, not Normal, Cacheable, Shareable")) },
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{ I("bus_access_periph", 0x65, STXT("Bus access, peripheral")) },
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{ I("bus_access_shared", 0x62,
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STXT("Bus access, Normal, Cacheable, Shareable")) },
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/* cache: */
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{ I("btb_mis_pred", 0x102, STXT("BTB misprediction")) },
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{ I("dtb_miss", 0x104, STXT("DTB miss")) },
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{ I("itb_miss", 0x103, STXT("ITB miss")) },
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{ I("l1_stage2_tlb_refill", 0x111, STXT("L1 stage 2 TLB refill")) },
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{ I("l1d_cache", 0x4, STXT("Level 1 data cache access")) },
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{ I("l1d_cache_inval", 0x48, STXT("L1D cache invalidate")) },
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{ I("l1d_cache_late_miss", 0x105, STXT("L1D cache late miss")) },
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{ I("l1d_cache_prefetch", 0x106, STXT("L1D cache prefetch")) },
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{ I("l1d_cache_refill", 0x3, STXT("Level 1 data cache refill")) },
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{ I("l1d_tlb", 0x25, STXT("L1D TLB access")) },
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{ I("l1d_tlb_refill", 0x5, STXT("Attributable Level 1 data TLB refill")) },
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{ I("l1i_cache", 0x14,
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STXT("Attributable Level 1 instruction cache access")) },
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{ I("l1i_cache_refill", 0x1, STXT("Level 1 instruction cache refill")) },
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{ I("l1i_tlb", 0x26, STXT("Attributable Level 1 instruction TLB access")) },
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{ I("l1i_tlb_refill", 0x2,
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STXT("Attributable Level 1 instruction TLB refill")) },
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{ I("l2d_cache", 0x16, STXT("Level 2 data cache access")) },
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{ I("l2d_cache_inval", 0x58, STXT("L2D cache invalidate")) },
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{ I("l2d_cache_prefetch", 0x107, STXT("L2D cache prefetch")) },
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{ I("l2d_cache_rd", 0x50, STXT("L2D cache access, read")) },
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{ I("l2d_cache_refill", 0x17, STXT("Level 2 data refill")) },
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{ I("l2d_cache_refill_rd", 0x52, STXT("L2D cache refill, read")) },
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{ I("l2d_cache_refill_wr", 0x53, STXT("L2D cache refill, write")) },
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{ I("l2d_cache_wb", 0x18,
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STXT("Attributable Level 2 data cache write-back")) },
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{ I("l2d_cache_wb_clean", 0x57,
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STXT("L2D cache Write-Back, cleaning and coherency")) },
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{ I("l2d_cache_wb_victim", 0x56, STXT("L2D cache Write-Back, victim")) },
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{ I("l2d_cache_wr", 0x51, STXT("L2D cache access, write")) },
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{ I("l2d_tlb_access", 0x34, STXT("L2D TLB access")) },
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{ I("l2i_tlb_access", 0x35, STXT("L2I TLB access")) },
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{ I("page_walk_l0_stage1_hit", 0x112, STXT("Page walk, L0 stage-1 hit")) },
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{ I("page_walk_l1_stage1_hit", 0x113, STXT("Page walk, L1 stage-1 hit")) },
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{ I("page_walk_l1_stage2_hit", 0x115, STXT("Page walk, L1 stage-2 hit")) },
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{ I("page_walk_l2_stage1_hit", 0x114, STXT("Page walk, L2 stage-1 hit")) },
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{ I("page_walk_l2_stage2_hit", 0x116, STXT("Page walk, L2 stage-2 hit")) },
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/* clock: */
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{ I("cpu_cycles", 0x11, STXT("Cycle")) },
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{ I("fsu_clock_off_cycles", 0x101, STXT("FSU clocking gated off cycle")) },
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{ I("wait_cycles", 0x110, STXT("Wait state cycle")) },
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/* core imp def: */
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{ I("bus_access_rd", 0x60, STXT("Bus access read")) },
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{ I("bus_access_wr", 0x61, STXT("Bus access write")) },
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{ I("l1d_cache_rd", 0x40, STXT("L1D cache access, read")) },
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{ I("l1d_cache_refill_rd", 0x42, STXT("L1D cache refill, read")) },
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{ I("l1d_cache_refill_wr", 0x43, STXT("L1D cache refill, write")) },
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{ I("l1d_cache_wr", 0x41, STXT("L1D cache access, write")) },
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{ I("l1d_tlb_rd", 0x4e, STXT("L1D tlb access, read")) },
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{ I("l1d_tlb_refill_rd", 0x4c, STXT("L1D tlb refill, read")) },
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{ I("l1d_tlb_refill_wr", 0x4d, STXT("L1D tlb refill, write")) },
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{ I("l1d_tlb_wr", 0x4f, STXT("L1D tlb access, write")) },
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/* exception: */
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{ I("exc_dabort", 0x84, STXT("Exception taken, Data Abort and SError")) },
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{ I("exc_fiq", 0x87, STXT("Exception taken, FIQ")) },
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{ I("exc_hvc", 0x8a, STXT("Exception taken, Hypervisor Call")) },
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{ I("exc_irq", 0x86, STXT("Exception taken, IRQ")) },
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{ I("exc_pabort", 0x83, STXT("Exception taken, Instruction Abort")) },
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{ I("exc_return", 0xa,
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STXT("Instruction architecturally executed, condition check pass, exception"
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" return")) },
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{ I("exc_svc", 0x82, STXT("Exception taken, Supervisor Call")) },
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{ I("exc_taken", 0x9, STXT("Exception taken")) },
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{ I("exc_trap_dabort", 0x8c,
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STXT("Exception taken, Data Abort or SError not taken locally")) },
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{ I("exc_trap_fiq", 0x8f, STXT("Exception taken, FIQ not taken locally")) },
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{ I("exc_trap_irq", 0x8e, STXT("Exception taken, IRQ not taken locally")) },
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{ I("exc_trap_other", 0x8d,
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STXT("Exception taken, Other traps not taken locally")) },
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{ I("exc_trap_pabort", 0x8b,
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STXT("Exception taken, Instruction Abort not taken locally")) },
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{ I("exc_undef", 0x81, STXT("Exception taken, Other synchronous")) },
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/* instruction: */
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{ I("ase_spec", 0x74,
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STXT("Operation speculatively executed, Advanced SIMD instruction")) },
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{ I("br_mis_pred_retired", 0x22,
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STXT("Instruction architecturally executed, mispredicted branch")) },
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{ I("br_retired", 0x21,
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STXT("Instruction architecturally executed, branch")) },
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{ I("cid_write_retired", 0xb, STXT("Write to CONTEXTIDR")) },
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{ I("crypto_spec", 0x77,
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STXT("Operation speculatively executed, Cryptographic instruction")) },
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{ I("dmb_spec", 0x7e, STXT("Barrier speculatively executed, DMB")) },
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{ I("dp_spec", 0x73,
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STXT("Operation speculatively executed, integer data processing")) },
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{ I("dsb_spec", 0x7d, STXT("Barrier speculatively executed, DSB")) },
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{ I("inst_retired", 0x8, STXT("Instruction architecturally executed")) },
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{ I("inst_spec", 0x1b, STXT("Operation speculatively executed")) },
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{ I("isb_spec", 0x7c, STXT("Barrier speculatively executed, ISB")) },
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{ I("ld_spec", 0x70, STXT("Operation speculatively executed, load")) },
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{ I("ldst_spec", 0x72,
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STXT("Operation speculatively executed, load or store")) },
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{ I("nop_spec", 0x100, STXT("Speculatively executed, NOP")) },
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{ I("pc_write_spec", 0x76,
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STXT("Operation speculatively executed, software change of the PC")) },
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{ I("rc_ld_spec", 0x90,
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STXT("Release consistency operation speculatively executed, Load-Acquire")) },
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{ I("rc_st_spec", 0x91,
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STXT("Release consistency operation speculatively executed, Store-Release")) },
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{ I("st_spec", 0x71, STXT("Operation speculatively executed, store")) },
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{ I("sw_incr", 0, STXT("Software increment")) },
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{ I("ttbr_write_retired", 0x1c,
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STXT("Instruction architecturally executed, Condition code check pass, write"
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" to TTBR")) },
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{ I("vfp_spec", 0x75,
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STXT("Operation speculatively executed, floating-point instruction")) },
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/* intrinsic: */
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{ I("ldrex_spec", 0x6c,
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STXT("Exclusive operation speculatively executed, LDREX or LDX")) },
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{ I("strex_fail_spec", 0x6e,
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STXT("Exclusive operation speculatively executed, STREX or STX fail")) },
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{ I("strex_pass_spec", 0x6d,
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STXT("Exclusive operation speculatively executed, STREX or STX pass")) },
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{ I("strex_spec", 0x6f,
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STXT("Exclusive operation speculatively executed, STREX or STX")) },
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/* memory: */
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{ I("mem_access", 0x13, STXT("Data memory access")) },
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{ I("mem_access_rd", 0x66, STXT("Data memory access, read")) },
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{ I("mem_access_wr", 0x67, STXT("Data memory access, write")) },
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{ I("memory_error", 0x1a, STXT("Local memory error")) },
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{ I("unaligned_ld_spec", 0x68, STXT("Unaligned access, read")) },
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{ I("unaligned_ldst_spec", 0x6a, STXT("Unaligned access")) },
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{ I("unaligned_st_spec", 0x69, STXT("Unaligned access, write")) },
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/* pipeline: */
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{ I("bx_stall", 0x10c, STXT("BX stalled")) },
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{ I("decode_stall", 0x108, STXT("Decode starved")) },
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{ I("dispatch_stall", 0x109, STXT("Dispatch stalled")) },
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{ I("fx_stall", 0x10f, STXT("FX stalled")) },
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{ I("ixa_stall", 0x10a, STXT("IXA stalled")) },
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{ I("ixb_stall", 0x10b, STXT("IXB stalled")) },
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{ I("lx_stall", 0x10d, STXT("LX stalled")) },
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{ I("sx_stall", 0x10e, STXT("SX stalled")) },
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{ NULL, NULL, 0, NULL }
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};
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#undef I
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#endif
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