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Move the ``set mask-address'' command to remote-mips.c. Disable

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address masking in mips-tdep.c.
This commit is contained in:
Andrew Cagney 2000-07-11 09:25:22 +00:00
parent e2ad119d2f
commit 4014092b58
3 changed files with 139 additions and 59 deletions
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20
gdb/ChangeLog
View File

@ -1,3 +1,23 @@
Tue Jul 11 19:06:29 2000 Andrew Cagney <cagney@b1.cygnus.com>
* remote-mips.c (mips_request): Change all arguments to ULONGEST.
(mips_exit_debug, mips_resume, mips_initialize, mips_wait,
mips_fetch_registers, mips_store_registers, mips_fetch_word):
Update.
(mips_xfer_memory): When mask_address_p, mask MEMADDR down to just
32 bits.
(_initialize_remote_mips): Add ``set mask-address'' command.
* mips-tdep.c (_initialize_mips_tdep): Replace "set mask-address"
with "set mips mask-address". Implement using
add_set_auto_boolean_cmd.
(struct gdbarch_tdep): Add default_mask_address_p.
(mips_mask_address_p, show_mask_address): New functions.
(mips_addr_bits_remove): Use mips_mask_address_p() to determine if
masking is needed.
(mips_gdbarch_init): Set default_mask_address_p to zero.
(mips_dump_tdep): Print value of mask_address_p.
Tue Jul 11 18:32:40 2000 Andrew Cagney <cagney@b1.cygnus.com>
* printcmd.c (print_scalar_formatted): Move masking of 'a' address

86
gdb/mips-tdep.c
View File

@ -124,6 +124,7 @@ struct gdbarch_tdep
int mips_regs_have_home_p;
int mips_default_stack_argsize;
int gdb_target_is_mips64;
int default_mask_address_p;
};
#if GDB_MULTI_ARCH
@ -466,7 +467,46 @@ mips_register_convert_to_raw (virtual_type, n, virt_buf, raw_buf)
}
/* Should the upper word of 64-bit addresses be zeroed? */
static int mask_address_p = 1;
enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO;
static int
mips_mask_address_p (void)
{
switch (mask_address_var)
{
case CMD_AUTO_BOOLEAN_TRUE:
return 1;
case CMD_AUTO_BOOLEAN_FALSE:
return 0;
break;
case CMD_AUTO_BOOLEAN_AUTO:
return gdbarch_tdep (current_gdbarch)->default_mask_address_p;
default:
internal_error ("mips_mask_address_p: bad switch");
return -1;
}
}
static void
show_mask_address (char *cmd, int from_tty)
{
switch (mask_address_var)
{
case CMD_AUTO_BOOLEAN_TRUE:
printf_filtered ("The 32 bit mips address mask is enabled\n");
break;
case CMD_AUTO_BOOLEAN_FALSE:
printf_filtered ("The 32 bit mips address mask is disabled\n");
break;
case CMD_AUTO_BOOLEAN_AUTO:
printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
mips_mask_address_p () ? "enabled" : "disabled");
break;
default:
internal_error ("show_mask_address: bad switch");
break;
}
}
/* Should call_function allocate stack space for a struct return? */
int
@ -1315,7 +1355,7 @@ mips_addr_bits_remove (addr)
{
if (GDB_TARGET_IS_MIPS64)
{
if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
{
/* This hack is a work-around for existing boards using
PMON, the simulator, and any other 64-bit targets that
@ -1324,17 +1364,22 @@ mips_addr_bits_remove (addr)
hardware. Thus, the PC or SP are likely to have been
sign extended to all 1s by instruction sequences that
load 32-bit addresses. For example, a typical piece of
code that loads an address is this: lui $r2, <upper 16
bits> ori $r2, <lower 16 bits> But the lui sign-extends
the value such that the upper 32 bits may be all 1s. The
workaround is simply to mask off these bits. In the
future, gcc may be changed to support true 64-bit
addressing, and this masking will have to be disabled. */
code that loads an address is this:
lui $r2, <upper 16 bits>
ori $r2, <lower 16 bits>
But the lui sign-extends the value such that the upper 32
bits may be all 1s. The workaround is simply to mask off
these bits. In the future, gcc may be changed to support
true 64-bit addressing, and this masking will have to be
disabled. */
addr &= (CORE_ADDR) 0xffffffff;
}
}
else
else if (mips_mask_address_p ())
{
/* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
masking off bits, instead, the actual target should be asking
for the address to be converted to a valid pointer. */
/* Even when GDB is configured for some 32-bit targets
(e.g. mips-elf), BFD is configured to handle 64-bit targets,
so CORE_ADDR is 64 bits. So we still have to mask off
@ -4046,6 +4091,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
tdep->gdb_target_is_mips64 = 0;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4058,6 +4104,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
tdep->gdb_target_is_mips64 = 1;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4070,6 +4117,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
tdep->gdb_target_is_mips64 = 0;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4082,6 +4130,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
tdep->gdb_target_is_mips64 = 1;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4094,6 +4143,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
tdep->gdb_target_is_mips64 = 0;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4106,6 +4156,7 @@ mips_gdbarch_init (info, arches)
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 1;
tdep->gdb_target_is_mips64 = 0;
tdep->default_mask_address_p = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
@ -4252,6 +4303,10 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
fprintf_unfiltered (file,
"mips_dump_tdep: tdep->mips_abi = %d\n",
tdep->mips_abi);
fprintf_unfiltered (file,
"mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
mips_mask_address_p (),
tdep->default_mask_address_p);
}
fprintf_unfiltered (file,
"mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
@ -4732,12 +4787,13 @@ search. The only need to set it is when debugging a stripped executable.",
/* Allow the user to control whether the upper bits of 64-bit
addresses should be zeroed. */
add_show_from_set
(add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p,
"Set zeroing of upper 32 bits of 64-bit addresses.\n\
Use \"on\" to enable the masking, and \"off\" to disable it.\n\
Without an argument, zeroing of upper address bits is enabled.", &setlist),
&showlist);
c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var,
"Set zeroing of upper 32 bits of 64-bit addresses.\n\
Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
the correct value.\n",
&setmipscmdlist);
add_cmd ("mask-address", no_class, show_mask_address,
"Show current mask-address value", &showmipscmdlist);
/* Allow the user to control the size of 32 bit registers within the
raw remote packet. */

92
gdb/remote-mips.c
View File

@ -77,9 +77,8 @@ static void mips_send_command (const char *cmd, int prompt);
static int mips_receive_packet (char *buff, int throw_error, int timeout);
static CORE_ADDR mips_request (int cmd, CORE_ADDR addr,
CORE_ADDR data, int *perr, int timeout,
char *buff);
static ULONGEST mips_request (int cmd, ULONGEST addr, ULONGEST data,
int *perr, int timeout, char *buff);
static void mips_initialize (void);
@ -1247,14 +1246,13 @@ mips_receive_packet (buff, throw_error, timeout)
occurs, it sets *PERR to 1 and sets errno according to what the
target board reports. */
static CORE_ADDR
mips_request (cmd, addr, data, perr, timeout, buff)
int cmd;
CORE_ADDR addr;
CORE_ADDR data;
int *perr;
int timeout;
char *buff;
static ULONGEST
mips_request (int cmd,
ULONGEST addr,
ULONGEST data,
int *perr,
int timeout,
char *buff)
{
char myBuff[DATA_MAXLEN + 1];
int len;
@ -1377,15 +1375,13 @@ mips_exit_debug ()
{
/* The DDB (NEC) and MiniRISC (LSI) versions of PMON exit immediately,
so we do not get a reply to this command: */
mips_request ('x', (unsigned int) 0, (unsigned int) 0, NULL,
mips_receive_wait, NULL);
mips_request ('x', 0, 0, NULL, mips_receive_wait, NULL);
mips_need_reply = 0;
if (!mips_expect (" break!"))
return -1;
}
else
mips_request ('x', (unsigned int) 0, (unsigned int) 0, &err,
mips_receive_wait, NULL);
mips_request ('x', 0, 0, &err, mips_receive_wait, NULL);
if (!mips_expect (mips_monitor_prompt))
return -1;
@ -1525,8 +1521,7 @@ mips_initialize ()
/* If this doesn't call error, we have connected; we don't care if
the request itself succeeds or fails. */
mips_request ('r', (unsigned int) 0, (unsigned int) 0, &err,
mips_receive_wait, NULL);
mips_request ('r', 0, 0, &err, mips_receive_wait, NULL);
set_current_frame (create_new_frame (read_fp (), read_pc ()));
select_frame (get_current_frame (), 0);
}
@ -1763,9 +1758,7 @@ mips_resume (pid, step, siggnal)
/* LSI PMON requires returns a reply packet "0x1 s 0x0 0x57f" after
a single step, so we wait for that. */
mips_request (step ? 's' : 'c',
(unsigned int) 1,
(unsigned int) siggnal,
mips_request (step ? 's' : 'c', 1, siggnal,
mips_monitor == MON_LSI && step ? &err : (int *) NULL,
mips_receive_wait, NULL);
}
@ -1820,8 +1813,7 @@ mips_wait (pid, status)
/* No timeout; we sit here as long as the program continues to execute. */
mips_wait_flag = 1;
rstatus = mips_request ('\000', (unsigned int) 0, (unsigned int) 0, &err, -1,
buff);
rstatus = mips_request ('\000', 0, 0, &err, -1, buff);
mips_wait_flag = 0;
if (err)
mips_error ("Remote failure: %s", safe_strerror (errno));
@ -2017,11 +2009,11 @@ mips_fetch_registers (regno)
compiled without the 64bit register access commands. This
means we cannot get hold of the full register width. */
if (mips_monitor == MON_DDB)
val = (unsigned) mips_request ('t', (unsigned int) pmon_reg,
(unsigned int) 0, &err, mips_receive_wait, NULL);
val = (unsigned) mips_request ('t', pmon_reg, 0,
&err, mips_receive_wait, NULL);
else
val = mips_request ('r', (unsigned int) pmon_reg,
(unsigned int) 0, &err, mips_receive_wait, NULL);
val = mips_request ('r', pmon_reg, 0,
&err, mips_receive_wait, NULL);
if (err)
mips_error ("Can't read register %d: %s", regno,
safe_strerror (errno));
@ -2061,7 +2053,7 @@ mips_store_registers (regno)
return;
}
mips_request ('R', (unsigned int) mips_map_regno (regno),
mips_request ('R', mips_map_regno (regno),
read_register (regno),
&err, mips_receive_wait, NULL);
if (err)
@ -2077,14 +2069,11 @@ mips_fetch_word (addr)
unsigned int val;
int err;
/* FIXME! addr was cast to uint! */
val = mips_request ('d', addr, (unsigned int) 0, &err,
mips_receive_wait, NULL);
val = mips_request ('d', addr, 0, &err, mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
/* FIXME! addr was cast to uint! */
val = mips_request ('i', addr, (unsigned int) 0, &err,
val = mips_request ('i', addr, 0, &err,
mips_receive_wait, NULL);
if (err)
mips_error ("Can't read address 0x%s: %s",
@ -2107,14 +2096,12 @@ mips_store_word (addr, val, old_contents)
int err;
unsigned int oldcontents;
oldcontents = mips_request ('D', addr, (unsigned int) val,
&err,
oldcontents = mips_request ('D', addr, val, &err,
mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
oldcontents = mips_request ('I', addr,
(unsigned int) val, &err,
oldcontents = mips_request ('I', addr, val, &err,
mips_receive_wait, NULL);
if (err)
return errno;
@ -2131,6 +2118,8 @@ mips_store_word (addr, val, old_contents)
for a longword, since it transfers values in ASCII. We want the
byte values, so we have to swap the longword values. */
static int mask_address_p = 1;
static int
mips_xfer_memory (memaddr, myaddr, len, write, ignore)
CORE_ADDR memaddr;
@ -2139,16 +2128,24 @@ mips_xfer_memory (memaddr, myaddr, len, write, ignore)
int write;
struct target_ops *ignore;
{
register int i;
/* Round starting address down to longword boundary. */
register CORE_ADDR addr = memaddr & ~3;
/* Round ending address up; get number of longwords that makes. */
register int count = (((memaddr + len) - addr) + 3) / 4;
/* Allocate buffer of that many longwords. */
register char *buffer = alloca (count * 4);
int i;
CORE_ADDR addr;
int count;
char *buffer;
int status;
/* PMON targets do not cope well with 64 bit addresses. Mask the
value down to 32 bits. */
if (mask_address_p)
memaddr &= (CORE_ADDR) 0xffffffff;
/* Round starting address down to longword boundary. */
addr = memaddr & ~3;
/* Round ending address up; get number of longwords that makes. */
count = (((memaddr + len) - addr) + 3) / 4;
/* Allocate buffer of that many longwords. */
buffer = alloca (count * 4);
if (write)
{
/* Fill start and end extra bytes of buffer with existing data. */
@ -3697,4 +3694,11 @@ synchronize with the remote system. A value of -1 means that there is no limit\
add_com ("pmon <command>", class_obscure, pmon_command,
"Send a packet to PMON (must be in debug mode).");
add_show_from_set (add_set_cmd ("mask-address", no_class,
var_boolean, &mask_address_p,
"Set zeroing of upper 32 bits of 64-bit addresses when talking to PMON targets.\n\
Use \"on\" to enable the masking and \"off\" to disable it.\n",
&setlist),
&showlist);
}