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[ARM][GAS] Fix invalid arm-wince-pe tests.
There are a number of failures for the arm-wince-pe targets, most are due to the test being invalid for the target. This patch adjusts the invalid tests to either make them valid or to set them as skipped for arm-wince-pe targets. gas/testsuite 2015-11-24 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/armv7e-m+fpv5-d16.d: Skip test for *-*-pe, *-wince-* and for *-*-coff targets. * gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise. * gas/arm/blx-bl-convert.d: Likewise. * gas/arm/ldst-offset0.d: Likewise. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Likewise. * gas/arm/armv8-a+pan.s: Adjust test to make it valid for non-ELF targets. * gas/arm/wince.d: Add assembler option "-mccs". * gas/arm/wince_inst.d: Update expected output. Change-Id: I33a356e97eace3f8e1d581a46ec6413898105bef
This commit is contained in:
Matthew Wahab
parent
2e8cf49e13
commit
3ff0b31dc6
@ -1,3 +1,16 @@
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2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
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* gas/arm/armv7e-m+fpv5-d16.d: Skip test for *-*-pe, *-wince-* and
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for *-*-coff targets.
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* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.
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* gas/arm/blx-bl-convert.d: Likewise.
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* gas/arm/ldst-offset0.d: Likewise.
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* gas/arm/thumb2_ldr_immediate_armv6t2.d: Likewise.
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* gas/arm/armv8-a+pan.s: Adjust test to make it
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valid for non-ELF targets.
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* gas/arm/wince.d: Add assembler option "-mccs".
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* gas/arm/wince_inst.d: Update expected output.
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2015-11-20 Maciej W. Rozycki <macro@imgtec.com>
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* gas/mips/nan-legacy-1.d: Remove MIPS ABI flags match patterns.
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@ -1,5 +1,6 @@
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#name: Valid v7e-m+fpv5-d16
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-* *-*-coff
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.*: +file format .*arm.*
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@ -1,4 +1,5 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-* *-*-coff
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.*: +file format .*arm.*
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@ -2,13 +2,13 @@
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.arch armv8-a
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.arch_extension pan
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A1:
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.arm
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A1:
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setpan #0
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setpan #1
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T1:
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.thumb
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T1:
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setpan #0
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setpan #1
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@ -1,6 +1,7 @@
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#name: blx->bl convert under no -march/cpu
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#error-output: blx-bl-convert.l
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#objdump: -d
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#skip: *-*-pe *-wince-* *-*-coff
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.*: file format .*
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@ -1,6 +1,7 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARM load/store with 0 offset
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#as:
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#skip: *-*-pe *-wince-* *-*-coff
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# Test the standard ARM instructions:
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@ -1,6 +1,7 @@
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# name: Ldr immediate on armv6
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# as: -march=armv6t2
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# objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-* *-*-coff
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.*: +file format .*arm.*
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@ -1,6 +1,6 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARM WinCE basic tests
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#as: -mcpu=arm7m -EL
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#as: -mcpu=arm7m -EL -mccs
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#source: wince.s
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#not-skip: *-wince-*
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@ -97,22 +97,22 @@ Disassembly of section .text:
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0+14c <[^>]*> e1720004 ? cmn r2, r4
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0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
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0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
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0+158 <[^>]*> e330f00a ? teq r0, #10
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0+15c <[^>]*> e132f004 ? teq r2, r4
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0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5
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0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1
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0+168 <[^>]*> e370f00a ? cmn r0, #10
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0+16c <[^>]*> e172f004 ? cmn r2, r4
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0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5
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0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1
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0+178 <[^>]*> e350f00a ? cmp r0, #10
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0+17c <[^>]*> e152f004 ? cmp r2, r4
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0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5
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0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1
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0+188 <[^>]*> e310f00a ? tst r0, #10
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0+18c <[^>]*> e112f004 ? tst r2, r4
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0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5
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0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1
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0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
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0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
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0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
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0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
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0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
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0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
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0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
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0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
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0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
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0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
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0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
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0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
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0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
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0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
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0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
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0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
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0+198 <[^>]*> e0000291 ? mul r0, r1, r2
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0+19c <[^>]*> e0110392 ? muls r1, r2, r3
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0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
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@ -132,7 +132,7 @@ Disassembly of section .text:
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0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8
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0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*>
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0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\]
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0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\]
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0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0
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0+1e8 <[^>]*> e5810000 ? str r0, \[r1\]
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0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\]
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0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]!
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@ -144,7 +144,7 @@ Disassembly of section .text:
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0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8
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0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*>
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0+210 <[^>]*> e5c71000 ? strb r1, \[r7\]
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0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\]
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0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0
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0+218 <[^>]*> e8900002 ? ldm r0, {r1}
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0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5}
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0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
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@ -163,13 +163,13 @@ Disassembly of section .text:
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0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^
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0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456
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0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033
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0+260 <[^>]*> eb000000 ? bl 0.* <[^>]*>
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0+260 <[^>]*> eb...... ? bl 0[0123456789abcdef]+ <[^>]*>
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[ ]*260:.*_wombat.*
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0+264 <[^>]*> 5b000000 ? blpl 0.* <[^>]*>
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[ ]*264:.*ARM.*hohum
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0+268 <[^>]*> ea000000 ? b 0.* <[^>]*>
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0+264 <[^>]*> 5b...... ? blpl 0[0123456789abcdef]+ <[^>]*>
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[ ]*264:.*ARM.*hohum.*
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0+268 <[^>]*> ea...... ? b 0[0123456789abcdef]+ <[^>]*>
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[ ]*268:.*_wibble.*
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0+26c <[^>]*> da000000 ? ble 0.* <[^>]*>
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0+26c <[^>]*> da...... ? ble 0[0123456789abcdef]+ <[^>]*>
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[ ]*26c:.*testerfunc.*
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0+270 <[^>]*> e1a01102 ? lsl r1, r2, #2
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0+274 <[^>]*> e1a01002 ? mov r1, r2
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@ -203,3 +203,4 @@ Disassembly of section .text:
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0+2e4 <[^>]*> e1a01fe2 ? ror r1, r2, #31
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0+2e8 <[^>]*> e1a01372 ? ror r1, r2, r3
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0+2ec <[^>]*> e1a01062 ? rrx r1, r2
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0+2f0 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
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