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x86-64: generalize OP_G()'s EVEX.R' handling

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EVEX.R' is invalid to be clear not only for mask registers, but also for
GPRs - IOW everything handled in this function.
This commit is contained in:
Jan Beulich 2021-07-22 13:02:54 +02:00
parent be2f8fcd9d
commit 3fa77affb0
4 changed files with 14 additions and 1 deletions
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2
gas/testsuite/gas/i386/evex.d
View File

@ -16,4 +16,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%eax
+[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
#pass

2
gas/testsuite/gas/i386/evex.s
View File

@ -12,3 +12,5 @@ _start:
.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
.byte 0x62, 0xe1, 0x7e, 0x08, 0x2d, 0xc0
.byte 0x62, 0xe1, 0x7c, 0x08, 0xc2, 0xc0, 0x00

2
gas/testsuite/gas/i386/x86-64-evex.d
View File

@ -17,4 +17,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,\(bad\)
+[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\)
#pass

9
opcodes/i386-dis.c
View File

@ -11934,6 +11934,13 @@ OP_G (int bytemode, int sizeflag)
{
int add = 0;
const char **names;
if (vex.evex && !vex.r && address_mode == mode_64bit)
{
oappend ("(bad)");
return;
}
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
@ -12012,7 +12019,7 @@ OP_G (int bytemode, int sizeflag)
break;
case mask_bd_mode:
case mask_mode:
if (add || (vex.evex && !vex.r))
if (add)
{
oappend ("(bad)");
return;