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New port: National Semiconductor's CR16

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This commit is contained in:
Nick Clifton 2007-06-29 14:09:34 +00:00
parent 7c3e1d1299
commit 3d3d428f04
126 changed files with 11202 additions and 24 deletions
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14
bfd/ChangeLog
View File

@ -1,3 +1,17 @@
2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
* Makefile.am: Add cr16 related entry
* Makefile.in: Regenerate
* archures.c: Add bfd_cr16_arch
* bfd-in2.h: Regenerate
* config.bfd: Add cr16-elf
* configure.in: Add bfd_elf32_cr16_vec
* configure: Regenerate.
* targets.c: Added cr16 related information
* cpu-cr16.c: New file.
* elf32-cr16.c: New file.
* reloc.c: Added cr16 relocs.
2007-06-29 Alan Modra <amodra@bigpond.net.au>
* elflink.c (_bfd_elf_link_assign_sym_version): Improve error

13
bfd/Makefile.am
View File

@ -64,6 +64,7 @@ ALL_MACHINES = \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
cpu-cr16.lo \
cpu-cr16c.lo \
cpu-cris.lo \
cpu-crx.lo \
@ -129,6 +130,7 @@ ALL_MACHINES_CFILES = \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
cpu-cr16.c \
cpu-cris.c \
cpu-cr16c.c \
cpu-crx.c \
@ -242,6 +244,7 @@ BFD32_BACKENDS = \
elf32-arm.lo \
elf32-avr.lo \
elf32-bfin.lo \
elf32-cr16.lo \
elf32-cr16c.lo \
elf32-cris.lo \
elf32-crx.lo \
@ -419,6 +422,7 @@ BFD32_BACKENDS_CFILES = \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
elf32-cr16.c \
elf32-cr16c.c \
elf32-cris.c \
elf32-crx.c \
@ -1054,6 +1058,7 @@ cpu-arm.lo: cpu-arm.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(INCDIR)/libiberty.h
cpu-avr.lo: cpu-avr.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-bfin.lo: cpu-bfin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cr16.lo: cpu-cr16.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cris.lo: cpu-cris.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cr16c.lo: cpu-cr16c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-crx.lo: cpu-crx.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
@ -1316,10 +1321,16 @@ elf32-bfin.lo: elf32-bfin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/bfin.h \
$(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/dwarf2.h \
elf32-target.h
elf32-cr16.lo: elf32-cr16.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16.h \
$(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h \
$(INCDIR)/libiberty.h
elf32-cr16c.lo: elf32-cr16c.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16c.h \
$(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h \
$(INCDIR)/libiberty.h
elf32-cris.lo: elf32-cris.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cris.h \

21
bfd/Makefile.in
View File

@ -312,6 +312,7 @@ ALL_MACHINES = \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
cpu-cr16.lo \
cpu-cr16c.lo \
cpu-cris.lo \
cpu-crx.lo \
@ -377,6 +378,7 @@ ALL_MACHINES_CFILES = \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
cpu-cr16.c \
cpu-cris.c \
cpu-cr16c.c \
cpu-crx.c \
@ -491,6 +493,7 @@ BFD32_BACKENDS = \
elf32-arm.lo \
elf32-avr.lo \
elf32-bfin.lo \
elf32-cr16.lo \
elf32-cr16c.lo \
elf32-cris.lo \
elf32-crx.lo \
@ -668,6 +671,7 @@ BFD32_BACKENDS_CFILES = \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
elf32-cr16.c \
elf32-cr16c.c \
elf32-cris.c \
elf32-crx.c \
@ -972,15 +976,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__confi
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
cd $(srcdir) && $(AUTOMAKE) --cygnus \
echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
cd $(srcdir) && $(AUTOMAKE) --foreign \
&& exit 0; \
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile'; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
cd $(top_srcdir) && \
$(AUTOMAKE) --cygnus Makefile
$(AUTOMAKE) --foreign Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \
@ -1633,6 +1637,7 @@ cpu-arm.lo: cpu-arm.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(INCDIR)/libiberty.h
cpu-avr.lo: cpu-avr.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-bfin.lo: cpu-bfin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cr16.lo: cpu-cr16.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cris.lo: cpu-cris.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-cr16c.lo: cpu-cr16c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-crx.lo: cpu-crx.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
@ -1895,10 +1900,16 @@ elf32-bfin.lo: elf32-bfin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/bfin.h \
$(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/dwarf2.h \
elf32-target.h
elf32-cr16.lo: elf32-cr16.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16.h \
$(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h \
$(INCDIR)/libiberty.h
elf32-cr16c.lo: elf32-cr16c.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16c.h \
$(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-target.h \
$(INCDIR)/libiberty.h
elf32-cris.lo: elf32-cris.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cris.h \

4
bfd/archures.c
View File

@ -347,6 +347,8 @@ DESCRIPTION
.#define bfd_mach_avr6 6
. bfd_arch_bfin, {* ADI Blackfin *}
.#define bfd_mach_bfin 1
. bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}
.#define bfd_mach_cr16 1
. bfd_arch_cr16c, {* National Semiconductor CompactRISC. *}
.#define bfd_mach_cr16c 1
. bfd_arch_crx, {* National Semiconductor CRX. *}
@ -436,6 +438,7 @@ extern const bfd_arch_info_type bfd_arc_arch;
extern const bfd_arch_info_type bfd_arm_arch;
extern const bfd_arch_info_type bfd_avr_arch;
extern const bfd_arch_info_type bfd_bfin_arch;
extern const bfd_arch_info_type bfd_cr16_arch;
extern const bfd_arch_info_type bfd_cr16c_arch;
extern const bfd_arch_info_type bfd_cris_arch;
extern const bfd_arch_info_type bfd_crx_arch;
@ -506,6 +509,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_arm_arch,
&bfd_avr_arch,
&bfd_bfin_arch,
&bfd_cr16_arch,
&bfd_cr16c_arch,
&bfd_cris_arch,
&bfd_crx_arch,

31
bfd/bfd-in2.h
View File

@ -2011,6 +2011,8 @@ enum bfd_architecture
#define bfd_mach_avr6 6
bfd_arch_bfin, /* ADI Blackfin */
#define bfd_mach_bfin 1
bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
#define bfd_mach_cr16 1
bfd_arch_cr16c, /* National Semiconductor CompactRISC. */
#define bfd_mach_cr16c 1
bfd_arch_crx, /* National Semiconductor CRX. */
@ -4103,6 +4105,35 @@ This is the 5 bits of a value. */
BFD_RELOC_16C_IMM32,
BFD_RELOC_16C_IMM32_C,
/* NS CR16 Relocations. */
BFD_RELOC_CR16_NUM8,
BFD_RELOC_CR16_NUM16,
BFD_RELOC_CR16_NUM32,
BFD_RELOC_CR16_NUM32a,
BFD_RELOC_CR16_REGREL0,
BFD_RELOC_CR16_REGREL4,
BFD_RELOC_CR16_REGREL4a,
BFD_RELOC_CR16_REGREL14,
BFD_RELOC_CR16_REGREL14a,
BFD_RELOC_CR16_REGREL16,
BFD_RELOC_CR16_REGREL20,
BFD_RELOC_CR16_REGREL20a,
BFD_RELOC_CR16_ABS20,
BFD_RELOC_CR16_ABS24,
BFD_RELOC_CR16_IMM4,
BFD_RELOC_CR16_IMM8,
BFD_RELOC_CR16_IMM16,
BFD_RELOC_CR16_IMM20,
BFD_RELOC_CR16_IMM24,
BFD_RELOC_CR16_IMM32,
BFD_RELOC_CR16_IMM32a,
BFD_RELOC_CR16_DISP4,
BFD_RELOC_CR16_DISP8,
BFD_RELOC_CR16_DISP16,
BFD_RELOC_CR16_DISP20,
BFD_RELOC_CR16_DISP24,
BFD_RELOC_CR16_DISP24a,
/* NS CRX Relocations. */
BFD_RELOC_CRX_REL4,
BFD_RELOC_CRX_REL8,

6
bfd/config.bfd
View File

@ -76,6 +76,7 @@ bfin*) targ_archs=bfd_bfin_arch ;;
c30*) targ_archs=bfd_tic30_arch ;;
c4x*) targ_archs=bfd_tic4x_arch ;;
c54x*) targ_archs=bfd_tic54x_arch ;;
cr16*) targ_archs=bfd_cr16_arch ;;
crisv32) targ_archs=bfd_cris_arch ;;
crx*) targ_archs=bfd_crx_arch ;;
dlx*) targ_archs=bfd_dlx_arch ;;
@ -353,6 +354,11 @@ case "${targ}" in
targ_underscore=yes
;;
cr16-*-elf*)
targ_defvec=bfd_elf32_cr16_vec
targ_underscore=yes
;;
cr16c-*-elf*)
targ_defvec=bfd_elf32_cr16c_vec
targ_underscore=yes

1
bfd/configure vendored
View File

@ -18627,6 +18627,7 @@ do
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_bigmips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_cr16_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;;
bfd_elf32_cr16c_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
bfd_elf32_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
bfd_elf32_crx_vec) tb="$tb elf32-crx.lo elf32.lo $elf" ;;

1
bfd/configure.in
View File

@ -618,6 +618,7 @@ do
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_bigmips_vxworks_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_cr16_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;;
bfd_elf32_cr16c_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
bfd_elf32_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;;
bfd_elf32_crx_vec) tb="$tb elf32-crx.lo elf32.lo $elf" ;;

40
bfd/cpu-cr16.c Normal file
View File

@ -0,0 +1,40 @@
/* BFD support for the CR16 processor.
Copyright 2007 Free Software Foundation, Inc.
Written by M R Swami Reddy
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_cr16_arch =
{
16, /* 16 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_cr16, /* enum bfd_architecture arch. */
bfd_mach_cr16,
"cr16", /* Arch name. */
"cr16", /* Printable name. */
1, /* Unsigned int section alignment power. */
TRUE, /* The one and only. */
bfd_default_compatible,
bfd_default_scan ,
0,
};

5
bfd/doc/Makefile.in
View File

@ -107,6 +107,7 @@ CPP = @CPP@
CPPFLAGS = @CPPFLAGS@
CYGPATH_W = @CYGPATH_W@
DATADIRNAME = @DATADIRNAME@
DEBUGDIR = @DEBUGDIR@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
DUMPBIN = @DUMPBIN@
@ -353,9 +354,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__confi
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus doc/Makefile'; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign doc/Makefile'; \
cd $(top_srcdir) && \
$(AUTOMAKE) --cygnus doc/Makefile
$(AUTOMAKE) --foreign doc/Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \

1433
bfd/elf32-cr16.c Normal file
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File diff suppressed because it is too large Load Diff

27
bfd/libbfd.h
View File

@ -1805,6 +1805,33 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_16C_IMM24_C",
"BFD_RELOC_16C_IMM32",
"BFD_RELOC_16C_IMM32_C",
"BFD_RELOC_CR16_NUM8",
"BFD_RELOC_CR16_NUM16",
"BFD_RELOC_CR16_NUM32",
"BFD_RELOC_CR16_NUM32a",
"BFD_RELOC_CR16_REGREL0",
"BFD_RELOC_CR16_REGREL4",
"BFD_RELOC_CR16_REGREL4a",
"BFD_RELOC_CR16_REGREL14",
"BFD_RELOC_CR16_REGREL14a",
"BFD_RELOC_CR16_REGREL16",
"BFD_RELOC_CR16_REGREL20",
"BFD_RELOC_CR16_REGREL20a",
"BFD_RELOC_CR16_ABS20",
"BFD_RELOC_CR16_ABS24",
"BFD_RELOC_CR16_IMM4",
"BFD_RELOC_CR16_IMM8",
"BFD_RELOC_CR16_IMM16",
"BFD_RELOC_CR16_IMM20",
"BFD_RELOC_CR16_IMM24",
"BFD_RELOC_CR16_IMM32",
"BFD_RELOC_CR16_IMM32a",
"BFD_RELOC_CR16_DISP4",
"BFD_RELOC_CR16_DISP8",
"BFD_RELOC_CR16_DISP16",
"BFD_RELOC_CR16_DISP20",
"BFD_RELOC_CR16_DISP24",
"BFD_RELOC_CR16_DISP24a",
"BFD_RELOC_CRX_REL4",
"BFD_RELOC_CRX_REL8",
"BFD_RELOC_CRX_REL8_CMP",

57
bfd/reloc.c
View File

@ -4515,6 +4515,63 @@ ENUMX
ENUMDOC
NS CR16C Relocations.
ENUM
BFD_RELOC_CR16_NUM8
ENUMX
BFD_RELOC_CR16_NUM16
ENUMX
BFD_RELOC_CR16_NUM32
ENUMX
BFD_RELOC_CR16_NUM32a
ENUMX
BFD_RELOC_CR16_REGREL0
ENUMX
BFD_RELOC_CR16_REGREL4
ENUMX
BFD_RELOC_CR16_REGREL4a
ENUMX
BFD_RELOC_CR16_REGREL14
ENUMX
BFD_RELOC_CR16_REGREL14a
ENUMX
BFD_RELOC_CR16_REGREL16
ENUMX
BFD_RELOC_CR16_REGREL20
ENUMX
BFD_RELOC_CR16_REGREL20a
ENUMX
BFD_RELOC_CR16_ABS20
ENUMX
BFD_RELOC_CR16_ABS24
ENUMX
BFD_RELOC_CR16_IMM4
ENUMX
BFD_RELOC_CR16_IMM8
ENUMX
BFD_RELOC_CR16_IMM16
ENUMX
BFD_RELOC_CR16_IMM20
ENUMX
BFD_RELOC_CR16_IMM24
ENUMX
BFD_RELOC_CR16_IMM32
ENUMX
BFD_RELOC_CR16_IMM32a
ENUMX
BFD_RELOC_CR16_DISP4
ENUMX
BFD_RELOC_CR16_DISP8
ENUMX
BFD_RELOC_CR16_DISP16
ENUMX
BFD_RELOC_CR16_DISP20
ENUMX
BFD_RELOC_CR16_DISP24
ENUMX
BFD_RELOC_CR16_DISP24a
ENUMDOC
NS CR16 Relocations.
ENUM
BFD_RELOC_CRX_REL4
ENUMX

2
bfd/targets.c
View File

@ -572,6 +572,7 @@ extern const bfd_target bfd_elf32_bigarm_symbian_vec;
extern const bfd_target bfd_elf32_bigarm_vxworks_vec;
extern const bfd_target bfd_elf32_bigmips_vec;
extern const bfd_target bfd_elf32_bigmips_vxworks_vec;
extern const bfd_target bfd_elf32_cr16_vec;
extern const bfd_target bfd_elf32_cr16c_vec;
extern const bfd_target bfd_elf32_cris_vec;
extern const bfd_target bfd_elf32_crx_vec;
@ -896,6 +897,7 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf32_bigarm_vxworks_vec,
&bfd_elf32_bigmips_vec,
&bfd_elf32_bigmips_vxworks_vec,
&bfd_elf32_cr16_vec,
&bfd_elf32_cr16c_vec,
&bfd_elf32_cris_vec,
&bfd_elf32_crx_vec,

13
gas/ChangeLog
View File

@ -1,3 +1,16 @@
2007-06-29 M R Swami Reddy <MR.Swami.Redd@nsc.com>
* Makefile.am: Add CR16 related entry.
* Makefile.in: Regenerate.
* config/tc-cr16.h: New file
* config/tc-cr16.c: New file
* doc/c-cr16.texi: New file for cr16
* doc/all.texi: Entry for cr16
* doc/Makefile.am: Added c-cr16.texi
* doc/Makefile.in: Regenerate
* doc/as.texinfo: Entry for CR16 target
* NEWS: Announce the support for the new target.
2007-06-26 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (parse_operands): Accept generic coprocessor regs

18
gas/Makefile.am
View File

@ -48,6 +48,7 @@ CPU_TYPES = \
arm \
avr \
bfin \
cr16 \
cris \
crx \
d10v \
@ -240,6 +241,7 @@ TARGET_CPU_CFILES = \
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
config/tc-d10v.c \
@ -294,6 +296,7 @@ TARGET_CPU_HFILES = \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
config/tc-d10v.h \
@ -1053,6 +1056,11 @@ DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
$(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
$(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
$(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
@ -1482,6 +1490,11 @@ DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
$(INCDIR)/obstack.h
@ -1838,6 +1851,11 @@ DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
$(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h
DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h
DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \

29
gas/Makefile.in
View File

@ -293,6 +293,7 @@ CPU_TYPES = \
arm \
avr \
bfin \
cr16 \
cris \
crx \
d10v \
@ -483,6 +484,7 @@ TARGET_CPU_CFILES = \
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
config/tc-d10v.c \
@ -537,6 +539,7 @@ TARGET_CPU_HFILES = \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
config/tc-d10v.h \
@ -824,6 +827,12 @@ DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
$(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
$(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
@ -1332,6 +1341,12 @@ DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
$(INCDIR)/obstack.h
@ -1767,6 +1782,12 @@ DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h
DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
$(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h
DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@ -2124,15 +2145,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__confi
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
cd $(srcdir) && $(AUTOMAKE) --cygnus \
echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
cd $(srcdir) && $(AUTOMAKE) --foreign \
&& exit 0; \
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile'; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
cd $(top_srcdir) && \
$(AUTOMAKE) --cygnus Makefile
$(AUTOMAKE) --foreign Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \

2
gas/NEWS
View File

@ -1,4 +1,6 @@
-*- text -*-
* Support for the National Semiconductor CR16 target has been added.
* Added gas .reloc pseudo. This is a low-level interface for creating
relocations.

2444
gas/config/tc-cr16.c Normal file
View File

File diff suppressed because it is too large Load Diff

73
gas/config/tc-cr16.h Normal file
View File

@ -0,0 +1,73 @@
/* tc-cr16.h -- Header file for tc-cr16.c, the CR16 GAS port.
Copyright 2007 Free Software Foundation, Inc.
Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef TC_CR16_H
#define TC_CR16_H
#define TC_CR16 1
#define TARGET_BYTES_BIG_ENDIAN 0
#define TARGET_FORMAT "elf32-cr16"
#define TARGET_ARCH bfd_arch_cr16
#define WORKING_DOT_WORD
#define LOCAL_LABEL_PREFIX '.'
#define md_undefined_symbol(s) 0
#define md_number_to_chars number_to_chars_littleendian
/* We do relaxing in the assembler as well as the linker. */
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
/* We do not want to adjust any relocations to make implementation of
linker relaxations easier. */
#define tc_fix_adjustable(fixP) 0
/* We need to force out some relocations when relaxing. */
#define TC_FORCE_RELOCATION(FIXP) cr16_force_relocation (FIXP)
extern int cr16_force_relocation (struct fix *);
/* Fixup debug sections since we will never relax them. */
#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
/* CR16 instructions, with operands included, are a multiple
of two bytes long. */
#define DWARF2_LINE_MIN_INSN_LENGTH 2
extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *);
/* This is called by emit_expr when creating a reloc for a cons.
We could use the definition there, except that we want to handle
the CR16 reloc type specially, rather than the BFD_RELOC type. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
cr16_cons_fix_new (FRAG, OFF, LEN, EXP)
/* Give an error if a frag containing code is not aligned to a 2-byte
boundary. */
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
&& (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 1) != 0) \
as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line, \
_("instruction address is not a multiple of 2"));
#endif /* TC_CR16_H */

2
gas/configure.tgt
View File

@ -35,6 +35,7 @@ case ${cpu} in
arm*) cpu_type=arm endian=little ;;
bfin*) cpu_type=bfin endian=little ;;
c4x*) cpu_type=tic4x ;;
cr16*) cpu_type=cr16 endian=little ;;
crisv32) cpu_type=cris arch=crisv32 ;;
crx*) cpu_type=crx endian=little ;;
fido) cpu_type=m68k ;;
@ -126,6 +127,7 @@ case ${generic_target} in
avr-*-*) fmt=elf bfd_gas=yes ;;
bfin-*-*) fmt=elf bfd_gas=yes ;;
bfin-*elf) fmt=elf ;;
cr16-*-elf*) fmt=elf ;;
cris-*-linux-* | crisv32-*-linux-*)
fmt=multi em=linux ;;

1
gas/doc/Makefile.am
View File

@ -34,6 +34,7 @@ CPU_DOCS = \
c-arm.texi \
c-avr.texi \
c-bfin.texi \
c-cr16.texi \
c-d10v.texi \
c-cris.texi \
c-h8300.texi \

5
gas/doc/Makefile.in
View File

@ -237,6 +237,7 @@ CPU_DOCS = \
c-arm.texi \
c-avr.texi \
c-bfin.texi \
c-cr16.texi \
c-d10v.texi \
c-cris.texi \
c-h8300.texi \
@ -294,9 +295,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__confi
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus doc/Makefile'; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign doc/Makefile'; \
cd $(top_srcdir) && \
$(AUTOMAKE) --cygnus doc/Makefile
$(AUTOMAKE) --foreign doc/Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \

1
gas/doc/all.texi
View File

@ -31,6 +31,7 @@
@set ARM
@set AVR
@set BFIN
@set CR16
@set CRIS
@set D10V
@set D30V

7
gas/doc/as.texinfo
View File

@ -6351,6 +6351,9 @@ subject, see the hardware manufacturer's manual.
@ifset BFIN
* BFIN-Dependent:: BFIN Dependent Features
@end ifset
@ifset CR16
* CR16-Dependent:: CR16 Dependent Features
@end ifset
@ifset CRIS
* CRIS-Dependent:: CRIS Dependent Features
@end ifset
@ -6472,6 +6475,10 @@ subject, see the hardware manufacturer's manual.
@include c-bfin.texi
@end ifset
@ifset CR16
@include c-cr16.texi
@end ifset
@ifset CRIS
@include c-cris.texi
@end ifset

80
gas/doc/c-cr16.texi Normal file
View File

@ -0,0 +1,80 @@
@c Copyright 2007 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node CR16-Dependent
@chapter CR16 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter CR16 Dependent Features
@end ifclear
@cindex CR16 support
@menu
* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
@end menu
@node CR16 Operand Qualifiers
@section CR16 Operand Qualifiers
@cindex CR16 Operand Qualifiers
The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
@table @code
@item s
- @code{Specifies expression operand type as small}
@item m
- @code{Specifies expression operand type as medium}
@item l
- @code{Specifies expression operand type as large}
@item c
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
@end table
CR16 target operand qualifiers and its size (in bits):
@table @samp
@item Immediate Operand
- s ---- 4 bits
@item
- m ---- 16 bits, for movb and movw instructions.
@item
- m ---- 20 bits, movd instructions.
@item
- l ---- 32 bits
@item Absolute Operand
- s ---- Illegal specifier for this operand.
@item
- m ---- 20 bits, movd instructions.
@item Displacement Operand
- s ---- 8 bits
@item
- m ---- 16 bits
@item
- l ---- 24 bits
@end table
For example:
@example
1 @code{movw $_myfun@@c,r1}
This loads the address of _myfun, shifted right by 1, into r1.
2 @code{movd $_myfun@@c,(r2,r1)}
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
3 @code{_myfun_ptr:}
@code{.long _myfun@@c}
@code{loadd _myfun_ptr, (r1,r0)}
@code{jal (r1,r0)}
This .long directive, the address of _myfunc, shifted right by 1 at link time.
@end example

42
gas/testsuite/ChangeLog
View File

@ -1,3 +1,45 @@
2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
* gas/cr16: New directory
* gas/cr16.exp: New file
* add_test.d and add_test.s: New files
* and_test.d and and_test.s: New files
* ash_test.d and ash_test.s: New files
* bal_test.d and bal_test.s: New files
* bcc_test.d and bcc_test.s: New files
* beq0_test.d and beq0_test.s: New files
* cbitb_test.d and cbitb_test.s: New files
* cbitw_test.d and cbitw_test.s: New files
* cinv_test.d and cinv_test.s: New files
* cmp_test.d and cmp_test.s: New files
* excp_test.d and excp_test.s: New files
* jal_test.d and jal_test.s: New files
* jcc_test.d and jcc_test.s: New files
* loadb_test.d and loadb_test.s: New files
* loadd_test.d and loadd_test.s: New files
* loadm_test.d and loadm_test.s: New files
* loadw_test.d and loadw_test.s: New files
* lpsp_test.d and lpsp_test.s: New files
* lsh_test.d and lsh_test.s: New files
* mov_test.d and mov_test.s: New files
* mul_test.d and mul_test.s: New files
* or_test.d and or_test.s: New files
* popret_test.d and popret_test.s: New files
* pop_test.d and pop_test.s: New files
* push_test.d and push_test.s: New files
* sbitb_test.d and sbitb_test.s: New files
* sbitw_test.d and sbitw_test.s: New files
* scc_test.d and scc_test.s: New files
* storb_test.d and storb_test.s: New files
* stord_test.d and stord_test.s: New files
* storm_test.d and storm_test.s: New files
* storw_test.d and storw_test.s: New files
* sub_test.d and sub_test.s: New files
* tbitb_test.d and tbitb_test.s: New files
* tbit_test.d and tbit_test.s: New files
* tbitw_test.d and tbitw_test.s: New files
* xor_test.d and xor_test.s: New files
2007-06-26 Paul Brook <paul@codesourcery.com>
* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.

4
gas/testsuite/gas/all/gas.exp
View File

@ -89,12 +89,12 @@ case $target_triplet in {
# symbol `sym' required but not present
setup_xfail "*c30*-*-*" "*c4x*-*-*" "*arm*-*-*aout*" "*arm*-*-*coff" \
"*arm*-*-pe" "crx*-*-*" "h8300*-*-*" "m68hc*-*-*" "maxq-*-*" \
"mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*"
"mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*" "cr16-*-*"
run_dump_test redef2
setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \
"bfin-*-*" "*c4x*-*-*" "crx*-*-*" "h8300*-*-*" "hppa*-*-hpux*" \
"m68hc*-*-*" "maxq-*-*" "mn10300-*-*" "or32-*-*" "pdp11-*-*" \
"vax*-*-*" "z8k-*-*"
"vax*-*-*" "z8k-*-*" "cr16-*-*"
run_dump_test redef3
setup_xfail "*c4x*-*-*"
gas_test_error "redef4.s" "" ".set for symbol already used as label"

71
gas/testsuite/gas/cr16/add_test.d Normal file
View File

@ -0,0 +1,71 @@
#as:
#objdump: -dr
#name: add_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 30 addb \$0xf:s,r1
2: b2 30 ff 00 addb \$0xff:m,r2
6: b1 30 ff 0f addb \$0xfff:m,r1
a: b1 30 14 00 addb \$0x14:m,r1
e: a2 30 addb \$0xa:s,r2
10: b2 30 0b 00 addb \$0xb:m,r2
14: 12 31 addb r1,r2
16: 23 31 addb r2,r3
18: 34 31 addb r3,r4
1a: 56 31 addb r5,r6
1c: 67 31 addb r6,r7
1e: 78 31 addb r7,r8
20: f1 34 addcb \$0xf:s,r1
22: b2 34 ff 00 addcb \$0xff:m,r2
26: b1 34 ff 0f addcb \$0xfff:m,r1
2a: b1 34 14 00 addcb \$0x14:m,r1
2e: a2 34 addcb \$0xa:s,r2
30: b2 34 0b 00 addcb \$0xb:m,r2
34: 12 35 addcb r1,r2
36: 23 35 addcb r2,r3
38: 34 35 addcb r3,r4
3a: 56 35 addcb r5,r6
3c: 67 35 addcb r6,r7
3e: 78 35 addcb r7,r8
40: f1 36 addcw \$0xf:s,r1
42: b2 36 ff 00 addcw \$0xff:m,r2
46: b1 36 ff 0f addcw \$0xfff:m,r1
4a: b1 36 14 00 addcw \$0x14:m,r1
4e: a2 36 addcw \$0xa:s,r2
50: b2 36 0b 00 addcw \$0xb:m,r2
54: 12 37 addcw r1,r2
56: 23 37 addcw r2,r3
58: 34 37 addcw r3,r4
5a: 56 37 addcw r5,r6
5c: 67 37 addcw r6,r7
5e: 78 37 addcw r7,r8
60: f1 32 addw \$0xf:s,r1
62: b2 32 ff 00 addw \$0xff:m,r2
66: b1 32 ff 0f addw \$0xfff:m,r1
6a: b1 32 14 00 addw \$0x14:m,r1
6e: a2 32 addw \$0xa:s,r2
70: 12 33 addw r1,r2
72: 23 33 addw r2,r3
74: 34 33 addw r3,r4
76: 56 33 addw r5,r6
78: 67 33 addw r6,r7
7a: 78 33 addw r7,r8
7c: f1 60 addd \$0xf:s,\(r2,r1\)
7e: b1 60 0b 00 addd \$0xb:m,\(r2,r1\)
82: b1 60 ff 00 addd \$0xff:m,\(r2,r1\)
86: b1 60 ff 0f addd \$0xfff:m,\(r2,r1\)
8a: 10 04 ff ff addd \$0xffff:m,\(r2,r1\)
8e: 1f 04 ff ff addd \$0xfffff:m,\(r2,r1\)
92: 21 00 ff 0f addd \$0xfffffff:l,\(r2,r1\)
96: ff ff
98: 91 60 addd \$-1:s,\(r2,r1\)
9a: 31 61 addd \(r4,r3\),\(r2,r1\)
9c: 31 61 addd \(r4,r3\),\(r2,r1\)
9e: af 60 addd \$0xa:s,\(sp\)
a0: ef 60 addd \$0xe:s,\(sp\)
a2: bf 60 0b 00 addd \$0xb:m,\(sp\)
a6: 8f 60 addd \$0x8:s,\(sp\)

98
gas/testsuite/gas/cr16/add_test.s Normal file
View File

@ -0,0 +1,98 @@
.text
.global main
main:
###########
# ADDB imm4/imm16, reg
###########
addb $0xf,r1
addb $0xff,r2
addb $0xfff,r1
#addb $0xffff,r2 // CHECK WITH CRASM 4.1
addb $20,r1
addb $10,r2
addb $11,r2
###########
# ADDB reg, reg
###########
addb r1,r2
addb r2,r3
addb r3,r4
addb r5,r6
addb r6,r7
addb r7,r8
###########
# ADDCB imm4/imm16, reg
###########
addcb $0xf,r1
addcb $0xff,r2
addcb $0xfff,r1
#addcb $0xffff,r2 // CHECK WITH CRASM 4.1
addcb $20,r1
addcb $10,r2
addcb $11,r2
###########
# ADDCB reg, reg
###########
addcb r1,r2
addcb r2,r3
addcb r3,r4
addcb r5,r6
addcb r6,r7
addcb r7,r8
###########
# ADDCW imm4/imm16, reg
###########
addcw $0xf,r1
addcw $0xff,r2
addcw $0xfff,r1
#addcw $0xffff,r2 # check with CRASM 4.1
addcw $20,r1
addcw $10,r2
addcw $11,r2
###########
# ADDCW reg, reg
###########
addcw r1,r2
addcw r2,r3
addcw r3,r4
addcw r5,r6
addcw r6,r7
addcw r7,r8
###########
# ADDW imm4/imm16, reg
###########
addw $0xf,r1
addw $0xff,r2
addw $0xfff,r1
#addw $0xffff,r2 // CHECK WITH CRASM 4.1
addw $20,r1
addw $10,r2
###########
# ADDW reg, reg
###########
addw r1,r2
addw r2,r3
addw r3,r4
addw r5,r6
addw r6,r7
addw r7,r8
###########
# ADDD imm4/imm16/imm20/imm32, regp
###########
addd $0xf,(r2,r1)
addd $0xB,(r2,r1)
addd $0xff,(r2,r1)
addd $0xfff,(r2,r1)
addd $0xffff,(r2,r1)
addd $0xfffff,(r2,r1)
addd $0xfffffff,(r2,r1)
addd $0xffffffff,(r2,r1)
###########
# ADDD regp, regp
###########
addd (r4,r3),(r2,r1)
addd (r4,r3),(r2,r1)
addd $10,(sp)
addd $14,(sp)
addd $11,(sp)
addd $8,(sp)

55
gas/testsuite/gas/cr16/and_test.d Normal file
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#as:
#objdump: -dr
#name: and_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 20 andb \$0xf:s,r1
2: b2 20 ff 00 andb \$0xff:m,r2
6: b1 20 ff 0f andb \$0xfff:m,r1
a: b2 20 ff ff andb \$0xffff:m,r2
e: b1 20 14 00 andb \$0x14:m,r1
12: a2 20 andb \$0xa:s,r2
14: 12 21 andb r1,r2
16: 23 21 andb r2,r3
18: 34 21 andb r3,r4
1a: 56 21 andb r5,r6
1c: 67 21 andb r6,r7
1e: 78 21 andb r7,r8
20: f1 22 andw \$0xf:s,r1
22: b2 22 ff 00 andw \$0xff:m,r2
26: b1 22 ff 0f andw \$0xfff:m,r1
2a: b2 22 ff ff andw \$0xffff:m,r2
2e: b1 22 14 00 andw \$0x14:m,r1
32: a2 22 andw \$0xa:s,r2
34: 12 23 andw r1,r2
36: 23 23 andw r2,r3
38: 34 23 andw r3,r4
3a: 56 23 andw r5,r6
3c: 67 23 andw r6,r7
3e: 78 23 andw r7,r8
40: 41 00 00 00 andd \$0xf:l,\(r2,r1\)
44: 0f 00
46: 41 00 00 00 andd \$0xff:l,\(r2,r1\)
4a: ff 00
4c: 41 00 00 00 andd \$0xfff:l,\(r2,r1\)
50: ff 0f
52: 41 00 00 00 andd \$0xffff:l,\(r2,r1\)
56: ff ff
58: 41 00 0f 00 andd \$0xfffff:l,\(r2,r1\)
5c: ff ff
5e: 41 00 ff 0f andd \$0xfffffff:l,\(r2,r1\)
62: ff ff
64: 41 00 ff ff andd \$0xffffffff:l,\(r2,r1\)
68: ff ff
6a: 14 00 31 b0 andd \(r4,r3\),\(r2,r1\)
6e: 14 00 31 b0 andd \(r4,r3\),\(r2,r1\)
72: 4f 00 00 00 andd \$0xa:l,\(sp\)
76: 0a 00
78: 4f 00 00 00 andd \$0xe:l,\(sp\)
7c: 0e 00
7e: 4f 00 00 00 andd \$0x8:l,\(sp\)
82: 08 00

57
gas/testsuite/gas/cr16/and_test.s Normal file
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.text
.global main
main:
###########
# ANDB imm4/imm16, reg
###########
andb $0xf,r1
andb $0xff,r2
andb $0xfff,r1
andb $0xffff,r2
andb $20,r1
andb $10,r2
###########
# ANDB reg, reg
###########
andb r1,r2
andb r2,r3
andb r3,r4
andb r5,r6
andb r6,r7
andb r7,r8
###########
# ANDW imm4/imm16, reg
###########
andw $0xf,r1
andw $0xff,r2
andw $0xfff,r1
andw $0xffff,r2
andw $20,r1
andw $10,r2
###########
# ANDW reg, reg
###########
andw r1,r2
andw r2,r3
andw r3,r4
andw r5,r6
andw r6,r7
andw r7,r8
###########
# ANDD imm4/imm16/imm32, regp
###########
andd $0xf,(r2,r1)
andd $0xff,(r2,r1)
andd $0xfff,(r2,r1)
andd $0xffff,(r2,r1)
andd $0xfffff,(r2,r1)
andd $0xfffffff,(r2,r1)
andd $0xffffffff,(r2,r1)
###########
# ANDD regp, regp
###########
andd (r4,r3),(r2,r1)
andd (r4,r3),(r2,r1)
andd $10,(sp)
andd $14,(sp)
andd $8,(sp)

47
gas/testsuite/gas/cr16/ash_test.d Normal file
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#as:
#objdump: -dr
#name: ash_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 71 40 ashub \$7:s,r1
2: 91 40 ashub \$-7:s,r1
4: 41 40 ashub \$4:s,r1
6: c1 40 ashub \$-4:s,r1
8: 81 40 ashub \$-8:s,r1
a: 31 40 ashub \$3:s,r1
c: d1 40 ashub \$-3:s,r1
e: 21 41 ashub r2,r1
10: 34 41 ashub r3,r4
12: 56 41 ashub r5,r6
14: 8a 41 ashub r8,r10
16: 71 42 ashuw \$7:s,r1
18: 91 43 ashuw \$-7:s,r1
1a: 41 42 ashuw \$4:s,r1
1c: c1 43 ashuw \$-4:s,r1
1e: 81 42 ashuw \$8:s,r1
20: 81 43 ashuw \$-8:s,r1
22: 31 42 ashuw \$3:s,r1
24: d1 43 ashuw \$-3:s,r1
26: 21 45 ashuw r2,r1
28: 34 45 ashuw r3,r4
2a: 56 45 ashuw r5,r6
2c: 8a 45 ashuw r8,r10
2e: 72 4c ashud \$7:s,\(r3,r2\)
30: 92 4f ashud \$-7:s,\(r3,r2\)
32: 82 4c ashud \$8:s,\(r3,r2\)
34: 82 4f ashud \$-8:s,\(r3,r2\)
36: 42 4c ashud \$4:s,\(r3,r2\)
38: c2 4f ashud \$-4:s,\(r3,r2\)
3a: c2 4c ashud \$12:s,\(r3,r2\)
3c: 42 4f ashud \$-12:s,\(r3,r2\)
3e: 31 4c ashud \$3:s,\(r2,r1\)
40: d1 4f ashud \$-3:s,\(r2,r1\)
42: 41 48 ashud r4,\(r2,r1\)
44: 51 48 ashud r5,\(r2,r1\)
46: 61 48 ashud r6,\(r2,r1\)
48: 81 48 ashud r8,\(r2,r1\)
4a: 11 48 ashud r1,\(r2,r1\)

59
gas/testsuite/gas/cr16/ash_test.s Normal file
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.text
.global main
main:
#####################################
# ASHUB cnt(left +)/cnt (right -), reg
#####################################
ashub $7,r1
ashub $-7,r1
ashub $4,r1
ashub $-4,r1
ashub $-8,r1
ashub $3,r1
ashub $-3,r1
#####################################
# ASHUB reg, reg
#####################################
ashub r2,r1
ashub r3,r4
ashub r5,r6
ashub r8,r10
#####################################
# ASHUW cnt(left +)/cnt (right -), reg
#####################################
ashuw $7,r1
ashuw $-7,r1
ashuw $4,r1
ashuw $-4,r1
ashuw $8,r1
ashuw $-8,r1
ashuw $3,r1
ashuw $-3,r1
#####################################
# ASHUW reg, reg
#####################################
ashuw r2,r1
ashuw r3,r4
ashuw r5,r6
ashuw r8,r10
#####################################
# ASHUD cnt(left +)/cnt (right -), regp
#####################################
ashud $7, (r3,r2)
ashud $-7, (r3,r2)
ashud $8, (r3,r2)
ashud $-8, (r3,r2)
ashud $4, (r3,r2)
ashud $-4, (r3,r2)
ashud $12,(r3,r2)
ashud $-12,(r3,r2)
ashud $3,(r2,r1)
ashud $-3,(r2,r1)
#####################################
# ASHUD reg, regp
#####################################
ashud r4,(r2,r1)
ashud r5,(r2,r1)
ashud r6,(r2,r1)
ashud r8,(r2,r1)
ashud r1,(r2,r1)

25
gas/testsuite/gas/cr16/bal_test.d Normal file
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#as:
#objdump: -dr
#name: bal_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 0f c0 22 f1 bal \(ra\),\*\+0xff122 <main\+0xff122>:m
4: ff c0 26 f1 bal \(ra\),\*\+0xfff12a <main\+0xfff12a>:m
8: 00 c0 22 00 bal \(ra\),\*\+0x2a <main\+0x2a>:m
c: 00 c0 22 01 bal \(ra\),\*\+0x12e <main\+0x12e>:m
10: 00 c0 22 f1 bal \(ra\),\*\+0xf132 <main\+0xf132>:m
14: 00 c0 2a 81 bal \(ra\),\*\+0x813e <main\+0x813e>:m
18: 10 00 00 20 bal \(r1,r0\),\*\+0x13a <main\+0x13a>:l
1c: 22 01
1e: 10 00 ac 2f bal \(r11,r10\),\*\+0xcff140 <main\+0xcff140>:l
22: 22 f1
24: 10 00 6a 2f bal \(r7,r6\),\*\+0xaff146 <main\+0xaff146>:l
28: 22 f1
2a: 10 00 38 2f bal \(r4,r3\),\*\+0x8ff14c <main\+0x8ff14c>:l
2e: 22 f1
30: 10 00 7f 2f bal \(r8,r7\),\*\+0xfff152 <main\+0xfff152>:l
34: 22 f1

14
gas/testsuite/gas/cr16/bal_test.s Normal file
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.text
.global main
main:
bal (ra),*+0xff122
bal (ra),*+0xfff126
bal (ra),*+0x22
bal (ra),*+0x122
bal (ra),*+0xf122
bal (ra),*+0x812a
bal (r1,r0),*+0x122
bal (r11,r10),*+0xcff122
bal (r7,r6),*+0xaff122
bal (r4,r3),*+0x8ff122
bal (r8,r7),*+0xfff122

69
gas/testsuite/gas/cr16/bcc_test.d Normal file
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#as:
#objdump: -dr
#name: bcc_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 01 11 beq \*\+0x22 <main\+0x22>:s
2: 19 11 bne \*\+0x34 <main\+0x34>:s
4: 32 12 bcc \*\+0x48 <main\+0x48>:s
6: 3a 12 bcc \*\+0x5a <main\+0x5a>:s
8: 43 13 bhi \*\+0x6e <main\+0x6e>:s
a: cb 13 blt \*\+0x80 <main\+0x80>:s
c: 64 14 bgt \*\+0x94 <main\+0x94>:s
e: 8d 14 bfs \*\+0xa8 <main\+0xa8>:s
10: 95 15 bfc \*\+0xba <main\+0xba>:s
12: a0 18 bc 01 blo \*\+0x1ce <main\+0x1ce>:m
16: 40 18 cc 01 bhi \*\+0x1e2 <main\+0x1e2>:m
1a: c0 18 d6 01 blt \*\+0x1f0 <main\+0x1f0>:m
1e: d0 18 e6 01 bge \*\+0x204 <main\+0x204>:m
22: eb 17 br \*\+0x118 <main\+0x118>:s
24: 00 18 12 01 beq \*\+0x136 <main\+0x136>:m
28: 00 18 12 1f beq \*\+0x1f3a <main\+0x1f3a>:m
2c: 00 18 22 0f beq \*\+0xf4e <main\+0xf4e>:m
30: 10 18 34 0f bne \*\+0xf64 <main\+0xf64>:m
34: 30 18 44 0f bcc \*\+0xf78 <main\+0xf78>:m
38: 30 18 56 0f bcc \*\+0xf8e <main\+0xf8e>:m
3c: 40 18 66 0f bhi \*\+0xfa2 <main\+0xfa2>:m
40: c0 18 78 0f blt \*\+0xfb8 <main\+0xfb8>:m
44: 60 18 88 0f bgt \*\+0xfcc <main\+0xfcc>:m
48: 80 18 9a 0f bfs \*\+0xfe2 <main\+0xfe2>:m
4c: 90 18 aa 0f bfc \*\+0xff6 <main\+0xff6>:m
50: a0 18 bc 1f blo \*\+0x200c <main\+0x200c>:m
54: 40 18 cc 1f bhi \*\+0x2020 <main\+0x2020>:m
58: c0 18 da 1f blt \*\+0x2032 <main\+0x2032>:m
5c: d0 18 ea 1f bge \*\+0x2046 <main\+0x2046>:m
60: e0 18 fa ff br \*\+0x1005a <main\+0x1005a>:m
64: 10 00 0f 0f beq \*\+0xff1f76 <main\+0xff1f76>:l
68: 12 1f
6a: 10 00 0a 0a beq \*\+0xaa0f8c <main\+0xaa0f8c>:l
6e: 22 0f
70: 10 00 1b 0b bne \*\+0xbb0fa4 <main\+0xbb0fa4>:l
74: 34 0f
76: 10 00 3c 0c bcc \*\+0xcc0fba <main\+0xcc0fba>:l
7a: 44 0f
7c: 10 00 3d 0d bcc \*\+0xdd0fd2 <main\+0xdd0fd2>:l
80: 56 0f
82: 10 00 49 09 bhi \*\+0x990fe8 <main\+0x990fe8>:l
86: 66 0f
88: 10 00 c8 08 blt \*\+0x881000 <main\+0x881000>:l
8c: 78 0f
8e: 10 00 67 07 bgt \*\+0x771016 <main\+0x771016>:l
92: 88 0f
94: 10 00 86 06 bfs \*\+0x66102e <main\+0x66102e>:l
98: 9a 0f
9a: 10 00 95 05 bfc \*\+0x551044 <main\+0x551044>:l
9e: aa 0f
a0: 10 00 a4 04 blo \*\+0x44205c <main\+0x44205c>:l
a4: bc 1f
a6: 10 00 43 03 bhi \*\+0x332072 <main\+0x332072>:l
aa: cc 1f
ac: 10 00 c2 02 blt \*\+0x22208a <main\+0x22208a>:l
b0: de 1f
b2: 10 00 d1 01 bge \*\+0x1120a0 <main\+0x1120a0>:l
b6: ee 1f
b8: 10 00 e0 0f br \*\+0x1000b6 <main\+0x1000b6>:l
bc: fe ff

59
gas/testsuite/gas/cr16/bcc_test.s Normal file
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.text
.global main
main:
###################
# bcc disp9/disp17/disp25
###################
# bcc disp9
###################
beq *+0x022
bne *+0x032
bcc *+0x044
bcc *+0x054
bhi *+0x066
blt *+0x076
bgt *+0x088
bfs *+0x09a
bfc *+0x0aa
blo *+0x1bc
bhi *+0x1cc
blt *+0x1d6
bge *+0x1e6
br *+0x0f6
###################
# bcc disp17
###################
beq *+0x112
beq *+0x1f12
beq *+0x0f22
bne *+0x0f34
bcc *+0x0f44
bcc *+0x0f56
bhi *+0x0f66
blt *+0x0f78
bgt *+0x0f88
bfs *+0x0f9a
bfc *+0x0faa
blo *+0x1fbc
bhi *+0x1fcc
blt *+0x1fda
bge *+0x1fea
br *+0xfffa
###################
# bcc disp25
###################
beq *+0xff1f12
beq *+0xaa0f22
bne *+0xbb0f34
bcc *+0xcc0f44
bcc *+0xdd0f56
bhi *+0x990f66
blt *+0x880f78
bgt *+0x770f88
bfs *+0x660f9a
bfc *+0x550faa
blo *+0x441fbc
bhi *+0x331fcc
blt *+0x221fde
bge *+0x111fee
br *+0x0ffffe

15
gas/testsuite/gas/cr16/beq0_test.d Normal file
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#as:
#objdump: -dr
#name: beq0_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 71 0c beq0b r1,\*\+0x10 <main\+0x10>:s
2: b1 0c beq0b r1,\*\+0x18 <main\+0x18>:s
4: e1 0c beq0b r1,\*\+0x1e <main\+0x1e>:s
6: 71 0e beq0w r1,\*\+0x10 <main\+0x10>:s
8: b1 0e beq0w r1,\*\+0x18 <main\+0x18>:s
a: e1 0e beq0w r1,\*\+0x1e <main\+0x1e>:s

15
gas/testsuite/gas/cr16/beq0_test.s Normal file
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.text
.global main
main:
###################
# beq0b reg, dispu5
###################
beq0b r1,*+16
beq0b r1,*+24
beq0b r1,*+30
###################
# beq0w reg, dispu5
###################
beq0w r1,*+16
beq0w r1,*+24
beq0w r1,*+30

82
gas/testsuite/gas/cr16/cbitb_test.d Normal file
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#as:
#objdump: -dr
#name: cbitb_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: c0 6b cd 0b cbitb \$0x4,0xbcd <main\+0xbcd>:m
4: da 6b cd ab cbitb \$0x5,0xaabcd <main\+0xaabcd>:m
8: 10 00 3f 7a cbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: 50 68 14 00 cbitb \$0x5,\[r12\]0x14:m
12: c0 68 fc ab cbitb \$0x4,\[r13\]0xabfc:m
16: 30 68 34 12 cbitb \$0x3,\[r12\]0x1234:m
1a: b0 68 34 12 cbitb \$0x3,\[r13\]0x1234:m
1e: 30 68 34 00 cbitb \$0x3,\[r12\]0x34:m
22: b0 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\)
26: b1 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\)
2a: b6 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\)
2e: b2 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\)
32: b7 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\)
36: b3 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\)
3a: b4 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\)
3e: b5 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\)
42: b8 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\)
46: b9 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\)
4a: be 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\)
4e: ba 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\)
52: bf 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\)
56: bb 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\)
5a: bc 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\)
5e: bd 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\)
62: be 6a 5a 4b cbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\)
66: b7 6a 1a 41 cbitb \$0x1,\[r12\]0x17a:m\(r6,r5\)
6a: bf 6a 14 01 cbitb \$0x1,\[r13\]0x134:m\(r6,r5\)
6e: 10 00 36 6a cbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\)
72: de bc
74: 10 00 5e 60 cbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\)
78: cd ab
7a: 10 00 37 60 cbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\)
7e: cd ab
80: 10 00 3f 60 cbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\)
84: de bc
86: 10 00 52 40 cbitb \$0x5,0x0:l\(r2\)
8a: 00 00
8c: 3c 6b 34 00 cbitb \$0x3,0x34:m\(r12\)
90: 3d 6b ab 00 cbitb \$0x3,0xab:m\(r13\)
94: 10 00 51 40 cbitb \$0x5,0xad:l\(r1\)
98: ad 00
9a: 10 00 52 40 cbitb \$0x5,0xcd:l\(r2\)
9e: cd 00
a0: 10 00 50 40 cbitb \$0x5,0xfff:l\(r0\)
a4: ff 0f
a6: 10 00 34 40 cbitb \$0x3,0xbcd:l\(r4\)
aa: cd 0b
ac: 3c 6b ff 0f cbitb \$0x3,0xfff:m\(r12\)
b0: 3d 6b ff 0f cbitb \$0x3,0xfff:m\(r13\)
b4: 3d 6b ff ff cbitb \$0x3,0xffff:m\(r13\)
b8: 3c 6b 43 23 cbitb \$0x3,0x2343:m\(r12\)
bc: 10 00 32 41 cbitb \$0x3,0x2345:l\(r2\)
c0: 45 23
c2: 10 00 38 44 cbitb \$0x3,0xabcd:l\(r8\)
c6: cd ab
c8: 10 00 3d 5f cbitb \$0x3,0xfabcd:l\(r13\)
cc: cd ab
ce: 10 00 38 4f cbitb \$0x3,0xabcd:l\(r8\)
d2: cd ab
d4: 10 00 39 4f cbitb \$0x3,0xabcd:l\(r9\)
d8: cd ab
da: 10 00 39 44 cbitb \$0x3,0xabcd:l\(r9\)
de: cd ab
e0: 31 6a cbitb \$0x3,0x0:s\(r2,r1\)
e2: 51 6b 01 00 cbitb \$0x5,0x1:m\(r2,r1\)
e6: 41 6b 34 12 cbitb \$0x4,0x1234:m\(r2,r1\)
ea: 31 6b 34 12 cbitb \$0x3,0x1234:m\(r2,r1\)
ee: 10 00 31 51 cbitb \$0x3,0x12345:l\(r2,r1\)
f2: 45 23
f4: 31 6b 23 01 cbitb \$0x3,0x123:m\(r2,r1\)
f8: 10 00 31 51 cbitb \$0x3,0x12345:l\(r2,r1\)
fc: 45 23

62
gas/testsuite/gas/cr16/cbitb_test.s Normal file
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.text
.global main
main:
cbitb $4,0xbcd
cbitb $5,0xaabcd
cbitb $3,0xfaabcd
cbitb $5,[r12]0x14
cbitb $4,[r13]0xabfc
cbitb $3,[r12]0x1234
cbitb $3,[r13]0x1234
cbitb $3,[r12]0x34
cbitb $3,[r12]0xa7a(r1,r0)
cbitb $3,[r12]0xa7a(r3,r2)
cbitb $3,[r12]0xa7a(r4,r3)
cbitb $3,[r12]0xa7a(r5,r4)
cbitb $3,[r12]0xa7a(r6,r5)
cbitb $3,[r12]0xa7a(r7,r6)
cbitb $3,[r12]0xa7a(r9,r8)
cbitb $3,[r12]0xa7a(r11,r10)
cbitb $3,[r13]0xa7a(r1,r0)
cbitb $3,[r13]0xa7a(r3,r2)
cbitb $3,[r13]0xa7a(r4,r3)
cbitb $3,[r13]0xa7a(r5,r4)
cbitb $3,[r13]0xa7a(r6,r5)
cbitb $3,[r13]0xa7a(r7,r6)
cbitb $3,[r13]0xa7a(r9,r8)
cbitb $3,[r13]0xa7a(r11,r10)
cbitb $5,[r13]0xb7a(r4,r3)
cbitb $1,[r12]0x17a(r6,r5)
cbitb $1,[r13]0x134(r6,r5)
cbitb $3,[r12]0xabcde(r4,r3)
cbitb $5,[r13]0xabcd(r4,r3)
cbitb $3,[r12]0xabcd(r6,r5)
cbitb $3,[r13]0xbcde(r6,r5)
cbitb $5,0x0(r2)
cbitb $3,0x34(r12)
cbitb $3,0xab(r13)
cbitb $5,0xad(r1)
cbitb $5,0xcd(r2)
cbitb $5,0xfff(r0)
cbitb $3,0xbcd(r4)
cbitb $3,0xfff(r12)
cbitb $3,0xfff(r13)
cbitb $3,0xffff(r13)
cbitb $3,0x2343(r12)
cbitb $3,0x12345(r2)
cbitb $3,0x4abcd(r8)
cbitb $3,0xfabcd(r13)
cbitb $3,0xfabcd(r8)
cbitb $3,0xfabcd(r9)
cbitb $3,0x4abcd(r9)
cbitb $3,0x0(r2,r1)
cbitb $5,0x1(r2,r1)
cbitb $4,0x1234(r2,r1)
cbitb $3,0x1234(r2,r1)
cbitb $3,0x12345(r2,r1)
cbitb $3,0x123(r2,r1)
cbitb $3,0x12345(r2,r1)

155
gas/testsuite/gas/cr16/cbitw_test.d Normal file
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@ -0,0 +1,155 @@
#as:
#objdump: -dr
#name: cbitw_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 40 6f cd 0b cbitw \$0x4:s,0xbcd <main\+0xbcd>:m
4: 5a 6f cd ab cbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m
8: 11 00 3f 7a cbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: a0 6f cd 0b cbitw \$0xa:s,0xbcd <main\+0xbcd>:m
12: fa 6f cd ab cbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m
16: 11 00 ef 7a cbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l
1a: cd ab
1c: 50 6c 14 00 cbitw \$0x5:s,\[r13\]0x14:m
20: 40 6d fc ab cbitw \$0x4:s,\[r13\]0xabfc:m
24: 30 6c 34 12 cbitw \$0x3:s,\[r12\]0x1234:m
28: 30 6d 34 12 cbitw \$0x3:s,\[r12\]0x1234:m
2c: 30 6c 34 00 cbitw \$0x3:s,\[r12\]0x34:m
30: f0 6c 14 00 cbitw \$0xf:s,\[r13\]0x14:m
34: e0 6d fc ab cbitw \$0xe:s,\[r13\]0xabfc:m
38: d0 6c 34 12 cbitw \$0xd:s,\[r13\]0x1234:m
3c: d0 6d 34 12 cbitw \$0xd:s,\[r13\]0x1234:m
40: b0 6c 34 00 cbitw \$0xb:s,\[r12\]0x34:m
44: f0 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
48: f1 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
4c: f6 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
50: f2 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
54: f7 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
58: f3 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
5c: f4 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
60: f5 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
64: f8 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
68: f9 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
6c: fe 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
70: fa 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
74: ff 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
78: fb 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
7c: fc 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
80: fd 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
84: fe 6a 5a 4b cbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
88: f7 6a 1a 41 cbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\)
8c: ff 6a 14 01 cbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\)
90: 11 00 36 6a cbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
94: de bc
96: 11 00 5e 60 cbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
9a: cd ab
9c: 11 00 37 60 cbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
a0: cd ab
a2: 11 00 3f 60 cbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
a6: de bc
a8: f0 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\)
ac: f1 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\)
b0: f6 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\)
b4: f2 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\)
b8: f7 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\)
bc: f3 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\)
c0: f4 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\)
c4: f5 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\)
c8: f8 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\)
cc: f9 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\)
d0: fe 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\)
d4: fa 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\)
d8: ff 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\)
dc: fb 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\)
e0: fc 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\)
e4: fd 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\)
e8: fe 6a fa 4b cbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
ec: f7 6a ba 41 cbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
f0: ff 6a b4 01 cbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
f4: 11 00 d6 6a cbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
f8: de bc
fa: 11 00 fe 60 cbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
fe: cd ab
100: 11 00 d7 60 cbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
104: cd ab
106: 11 00 df 60 cbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
10a: de bc
10c: 11 00 52 40 cbitw \$0x5:s,0x0:l\(r2\)
110: 00 00
112: 3c 69 34 00 cbitw \$0x3:s,0x34:m\(r12\)
116: 3d 69 ab 00 cbitw \$0x3:s,0xab:m\(r13\)
11a: 11 00 51 40 cbitw \$0x5:s,0xad:l\(r1\)
11e: ad 00
120: 11 00 52 40 cbitw \$0x5:s,0xcd:l\(r2\)
124: cd 00
126: 11 00 50 40 cbitw \$0x5:s,0xfff:l\(r0\)
12a: ff 0f
12c: 11 00 34 40 cbitw \$0x3:s,0xbcd:l\(r4\)
130: cd 0b
132: 3c 69 ff 0f cbitw \$0x3:s,0xfff:m\(r12\)
136: 3d 69 ff 0f cbitw \$0x3:s,0xfff:m\(r13\)
13a: 3d 69 ff ff cbitw \$0x3:s,0xffff:m\(r13\)
13e: 3c 69 43 23 cbitw \$0x3:s,0x2343:m\(r12\)
142: 11 00 32 41 cbitw \$0x3:s,0x2345:l\(r2\)
146: 45 23
148: 11 00 38 44 cbitw \$0x3:s,0xabcd:l\(r8\)
14c: cd ab
14e: 11 00 3d 5f cbitw \$0x3:s,0xfabcd:l\(r13\)
152: cd ab
154: 11 00 38 4f cbitw \$0x3:s,0xabcd:l\(r8\)
158: cd ab
15a: 11 00 39 4f cbitw \$0x3:s,0xabcd:l\(r9\)
15e: cd ab
160: 11 00 39 44 cbitw \$0x3:s,0xabcd:l\(r9\)
164: cd ab
166: 11 00 f2 40 cbitw \$0xf:s,0x0:l\(r2\)
16a: 00 00
16c: dc 69 34 00 cbitw \$0xd:s,0x34:m\(r12\)
170: dd 69 ab 00 cbitw \$0xd:s,0xab:m\(r13\)
174: 11 00 f1 40 cbitw \$0xf:s,0xad:l\(r1\)
178: ad 00
17a: 11 00 f2 40 cbitw \$0xf:s,0xcd:l\(r2\)
17e: cd 00
180: 11 00 f0 40 cbitw \$0xf:s,0xfff:l\(r0\)
184: ff 0f
186: 11 00 d4 40 cbitw \$0xd:s,0xbcd:l\(r4\)
18a: cd 0b
18c: dc 69 ff 0f cbitw \$0xd:s,0xfff:m\(r12\)
190: dd 69 ff 0f cbitw \$0xd:s,0xfff:m\(r13\)
194: dd 69 ff ff cbitw \$0xd:s,0xffff:m\(r13\)
198: dc 69 43 23 cbitw \$0xd:s,0x2343:m\(r12\)
19c: 11 00 d2 41 cbitw \$0xd:s,0x2345:l\(r2\)
1a0: 45 23
1a2: 11 00 d8 44 cbitw \$0xd:s,0xabcd:l\(r8\)
1a6: cd ab
1a8: 11 00 dd 5f cbitw \$0xd:s,0xfabcd:l\(r13\)
1ac: cd ab
1ae: 11 00 d8 4f cbitw \$0xd:s,0xabcd:l\(r8\)
1b2: cd ab
1b4: 11 00 d9 4f cbitw \$0xd:s,0xabcd:l\(r9\)
1b8: cd ab
1ba: 11 00 d9 44 cbitw \$0xd:s,0xabcd:l\(r9\)
1be: cd ab
1c0: 31 6e cbitw \$0x3:s,0x0:s\(r2,r1\)
1c2: 51 69 01 00 cbitw \$0x5:s,0x1:m\(r2,r1\)
1c6: 41 69 34 12 cbitw \$0x4:s,0x1234:m\(r2,r1\)
1ca: 31 69 34 12 cbitw \$0x3:s,0x1234:m\(r2,r1\)
1ce: 11 00 31 51 cbitw \$0x3:s,0x12345:l\(r2,r1\)
1d2: 45 23
1d4: 31 69 23 01 cbitw \$0x3:s,0x123:m\(r2,r1\)
1d8: 11 00 31 51 cbitw \$0x3:s,0x12345:l\(r2,r1\)
1dc: 45 23
1de: d1 6e cbitw \$0xd:s,0x0:s\(r2,r1\)
1e0: f1 69 01 00 cbitw \$0xf:s,0x1:m\(r2,r1\)
1e4: e1 69 34 12 cbitw \$0xe:s,0x1234:m\(r2,r1\)
1e8: d1 69 34 12 cbitw \$0xd:s,0x1234:m\(r2,r1\)
1ec: 11 00 d1 51 cbitw \$0xd:s,0x12345:l\(r2,r1\)
1f0: 45 23
1f2: d1 69 23 01 cbitw \$0xd:s,0x123:m\(r2,r1\)
1f6: 11 00 d1 51 cbitw \$0xd:s,0x12345:l\(r2,r1\)
1fa: 45 23

117
gas/testsuite/gas/cr16/cbitw_test.s Normal file
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.text
.global main
main:
cbitw $4,0xbcd
cbitw $5,0xaabcd
cbitw $3,0xfaabcd
cbitw $10,0xbcd
cbitw $15,0xaabcd
cbitw $14,0xfaabcd
cbitw $5,[r12]0x14
cbitw $4,[r13]0xabfc
cbitw $3,[r12]0x1234
cbitw $3,[r13]0x1234
cbitw $3,[r12]0x34
cbitw $15,[r12]0x14
cbitw $14,[r13]0xabfc
cbitw $13,[r12]0x1234
cbitw $13,[r13]0x1234
cbitw $11,[r12]0x34
cbitw $3,[r12]0xa7a(r1,r0)
cbitw $3,[r12]0xa7a(r3,r2)
cbitw $3,[r12]0xa7a(r4,r3)
cbitw $3,[r12]0xa7a(r5,r4)
cbitw $3,[r12]0xa7a(r6,r5)
cbitw $3,[r12]0xa7a(r7,r6)
cbitw $3,[r12]0xa7a(r9,r8)
cbitw $3,[r12]0xa7a(r11,r10)
cbitw $3,[r13]0xa7a(r1,r0)
cbitw $3,[r13]0xa7a(r3,r2)
cbitw $3,[r13]0xa7a(r4,r3)
cbitw $3,[r13]0xa7a(r5,r4)
cbitw $3,[r13]0xa7a(r6,r5)
cbitw $3,[r13]0xa7a(r7,r6)
cbitw $3,[r13]0xa7a(r9,r8)
cbitw $3,[r13]0xa7a(r11,r10)
cbitw $5,[r13]0xb7a(r4,r3)
cbitw $1,[r12]0x17a(r6,r5)
cbitw $1,[r13]0x134(r6,r5)
cbitw $3,[r12]0xabcde(r4,r3)
cbitw $5,[r13]0xabcd(r4,r3)
cbitw $3,[r12]0xabcd(r6,r5)
cbitw $3,[r13]0xbcde(r6,r5)
cbitw $13,[r12]0xa7a(r1,r0)
cbitw $13,[r12]0xa7a(r3,r2)
cbitw $13,[r12]0xa7a(r4,r3)
cbitw $13,[r12]0xa7a(r5,r4)
cbitw $13,[r12]0xa7a(r6,r5)
cbitw $13,[r12]0xa7a(r7,r6)
cbitw $13,[r12]0xa7a(r9,r8)
cbitw $13,[r12]0xa7a(r11,r10)
cbitw $13,[r13]0xa7a(r1,r0)
cbitw $13,[r13]0xa7a(r3,r2)
cbitw $13,[r13]0xa7a(r4,r3)
cbitw $13,[r13]0xa7a(r5,r4)
cbitw $13,[r13]0xa7a(r6,r5)
cbitw $13,[r13]0xa7a(r7,r6)
cbitw $13,[r13]0xa7a(r9,r8)
cbitw $13,[r13]0xa7a(r11,r10)
cbitw $15,[r13]0xb7a(r4,r3)
cbitw $11,[r12]0x17a(r6,r5)
cbitw $11,[r13]0x134(r6,r5)
cbitw $13,[r12]0xabcde(r4,r3)
cbitw $15,[r13]0xabcd(r4,r3)
cbitw $13,[r12]0xabcd(r6,r5)
cbitw $13,[r13]0xbcde(r6,r5)
cbitw $5,0x0(r2)
cbitw $3,0x34(r12)
cbitw $3,0xab(r13)
cbitw $5,0xad(r1)
cbitw $5,0xcd(r2)
cbitw $5,0xfff(r0)
cbitw $3,0xbcd(r4)
cbitw $3,0xfff(r12)
cbitw $3,0xfff(r13)
cbitw $3,0xffff(r13)
cbitw $3,0x2343(r12)
cbitw $3,0x12345(r2)
cbitw $3,0x4abcd(r8)
cbitw $3,0xfabcd(r13)
cbitw $3,0xfabcd(r8)
cbitw $3,0xfabcd(r9)
cbitw $3,0x4abcd(r9)
cbitw $15,0x0(r2)
cbitw $13,0x34(r12)
cbitw $13,0xab(r13)
cbitw $15,0xad(r1)
cbitw $15,0xcd(r2)
cbitw $15,0xfff(r0)
cbitw $13,0xbcd(r4)
cbitw $13,0xfff(r12)
cbitw $13,0xfff(r13)
cbitw $13,0xffff(r13)
cbitw $13,0x2343(r12)
cbitw $13,0x12345(r2)
cbitw $13,0x4abcd(r8)
cbitw $13,0xfabcd(r13)
cbitw $13,0xfabcd(r8)
cbitw $13,0xfabcd(r9)
cbitw $13,0x4abcd(r9)
cbitw $3,0x0(r2,r1)
cbitw $5,0x1(r2,r1)
cbitw $4,0x1234(r2,r1)
cbitw $3,0x1234(r2,r1)
cbitw $3,0x12345(r2,r1)
cbitw $3,0x123(r2,r1)
cbitw $3,0x12345(r2,r1)
cbitw $13,0x0(r2,r1)
cbitw $15,0x1(r2,r1)
cbitw $14,0x1234(r2,r1)
cbitw $13,0x1234(r2,r1)
cbitw $13,0x12345(r2,r1)
cbitw $13,0x123(r2,r1)
cbitw $13,0x12345(r2,r1)

15
gas/testsuite/gas/cr16/cinv_test.d Normal file
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#as:
#objdump: -dr
#name: cinv_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 0a 00 cinv \[i\]
2: 0b 00 cinv \[i,u\]
4: 0c 00 cinv \[d\]
6: 0d 00 cinv \[d,u\]
8: 0e 00 cinv \[d,i\]
a: 0f 00 cinv \[d,i,u\]

12
gas/testsuite/gas/cr16/cinv_test.s Normal file
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.text
.global main
main:
##############################
# cin [i/i,u/d/d,u/d,i/d,i,u]
##############################
cinv [i]
cinv [i,u]
cinv [d]
cinv [d,u]
cinv [d,i]
cinv [d,i,u]

51
gas/testsuite/gas/cr16/cmp_test.d Normal file
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#as:
#objdump: -dr
#name: cmp_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 50 cmpb \$0xf:s,r1
2: b2 50 ff 00 cmpb \$0xff:m,r2
6: b1 50 ff 0f cmpb \$0xfff:m,r1
a: b1 50 14 00 cmpb \$0x14:m,r1
e: a2 50 cmpb \$0xa:s,r2
10: b2 50 0b 00 cmpb \$0xb:m,r2
14: 12 51 cmpb r1,r2
16: 23 51 cmpb r2,r3
18: 34 51 cmpb r3,r4
1a: 56 51 cmpb r5,r6
1c: 67 51 cmpb r6,r7
1e: 78 51 cmpb r7,r8
20: f1 52 cmpw \$0xf:s,r1
22: b1 52 0b 00 cmpw \$0xb:m,r1
26: b2 52 ff 00 cmpw \$0xff:m,r2
2a: b1 52 ff 0f cmpw \$0xfff:m,r1
2e: b1 52 14 00 cmpw \$0x14:m,r1
32: a2 52 cmpw \$0xa:s,r2
34: b2 52 0b 00 cmpw \$0xb:m,r2
38: 12 53 cmpw r1,r2
3a: 23 53 cmpw r2,r3
3c: 34 53 cmpw r3,r4
3e: 56 53 cmpw r5,r6
40: 67 53 cmpw r6,r7
42: 78 53 cmpw r7,r8
44: f1 56 cmpd \$0xf:s,\(r2,r1\)
46: b1 56 0b 00 cmpd \$0xb:m,\(r2,r1\)
4a: b1 56 ff 00 cmpd \$0xff:m,\(r2,r1\)
4e: b1 56 ff 0f cmpd \$0xfff:m,\(r2,r1\)
52: 91 00 00 00 cmpd \$0xffff:l,\(r2,r1\)
56: ff ff
58: 91 00 0f 00 cmpd \$0xfffff:l,\(r2,r1\)
5c: ff ff
5e: 91 00 ff 0f cmpd \$0xfffffff:l,\(r2,r1\)
62: ff ff
64: 91 56 cmpd \$-1:s,\(r2,r1\)
66: 31 57 cmpd \(r4,r3\),\(r2,r1\)
68: 31 57 cmpd \(r4,r3\),\(r2,r1\)
6a: af 56 cmpd \$0xa:s,\(sp\)
6c: ef 56 cmpd \$0xe:s,\(sp\)
6e: bf 56 0b 00 cmpd \$0xb:m,\(sp\)
72: 8f 56 cmpd \$0x8:s,\(sp\)

62
gas/testsuite/gas/cr16/cmp_test.s Normal file
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.text
.global main
main:
###########
# CMPB imm4/imm16, reg
###########
cmpb $0xf,r1
cmpb $0xff,r2
cmpb $0xfff,r1
#cmpb $0xffff,r2 // CHCEFK WITH CRASM 4.1
cmpb $20,r1
cmpb $10,r2
cmpb $11,r2
###########
# CMPB reg, reg
###########
cmpb r1,r2
cmpb r2,r3
cmpb r3,r4
cmpb r5,r6
cmpb r6,r7
cmpb r7,r8
###########
# CMPW imm4/imm16, reg
###########
cmpw $0xf,r1
cmpw $0xB,r1
cmpw $0xff,r2
cmpw $0xfff,r1
#cmpw $0xffff,r2 // CHECK WITH CRASM 4.1
cmpw $20,r1
cmpw $10,r2
cmpw $11,r2
###########
# CMPW reg, reg
###########
cmpw r1,r2
cmpw r2,r3
cmpw r3,r4
cmpw r5,r6
cmpw r6,r7
cmpw r7,r8
###########
# CMPD imm4/imm16/imm32, regp
###########
cmpd $0xf,(r2,r1)
cmpd $0xB,(r2,r1)
cmpd $0xff,(r2,r1)
cmpd $0xfff,(r2,r1)
cmpd $0xffff,(r2,r1)
cmpd $0xfffff,(r2,r1)
cmpd $0xfffffff,(r2,r1)
cmpd $0xffffffff,(r2,r1)
###########
# CMPD regp, regp
###########
cmpd (r4,r3),(r2,r1)
cmpd (r4,r3),(r2,r1)
cmpd $10,(sp)
cmpd $14,(sp)
cmpd $11,(sp)
cmpd $8,(sp)

27
gas/testsuite/gas/cr16/cr16.exp Normal file
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#
# Driver for CR16 assembler testsuite
#
proc run_list_test { name opts } {
global srcdir subdir
set testname "cr16 $name"
set file $srcdir/$subdir/$name
gas_run ${name}.s $opts ">&dump.out"
if {[regexp_diff "dump.out" "${file}.l"] } {
fail $testname
verbose "output is [file_contents "dump.out"]" 2
return
}
pass $testname
}
if ![istarget cr16-*-*] {
return
}
set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach test $test_list {
# We need to strip the ".d", but can leave the dirname.
verbose [file rootname $test]
run_dump_test [file rootname $test]
}

18
gas/testsuite/gas/cr16/excp_test.d Normal file
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#as:
#objdump: -dr
#name: excp_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: c5 00 excp svc
2: c6 00 excp dvz
4: c7 00 excp flg
6: c8 00 excp bpt
8: c9 00 excp trc
a: ca 00 excp und
c: cc 00 excp iad
e: ce 00 excp dbg
10: cf 00 excp ise

15
gas/testsuite/gas/cr16/excp_test.s Normal file
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.text
.global main
main:
##########################################
# excp svc/dvz/flg/bpt/trc/und/iad/dbg/ise
##########################################
excp svc
excp dvz
excp flg
excp bpt
excp trc
excp und
excp iad
excp dbg
excp ise

14
gas/testsuite/gas/cr16/jal_test.d Normal file
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#as:
#objdump: -dr
#name: jal_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: d1 00 jal \(r2,r1\)
2: 14 00 15 80 jal \(r6,r5\),\(r2,r1\)
6: 14 00 32 80 jal \(r3,r2\),\(r4,r3\)
a: 14 00 30 80 jal \(r1,r0\),\(r4,r3\)
e: 14 00 72 80 jal \(r3,r2\),\(r8,r7\)

11
gas/testsuite/gas/cr16/jal_test.s Normal file
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.text
.global main
main:
################
# JAL regp regp
################
jal (r2,r1)
jal (r6,r5),(r2,r1)
jal (r3,r2),(r4,r3)
jal (r1,r0), (r4,r3)
jal (r3,r2), (r8,r7)

24
gas/testsuite/gas/cr16/jcc_test.d Normal file
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#as:
#objdump: -dr
#name: jcc_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 0a jeq \(r1,r0\)
2: 11 0a jne \(r2,r1\)
4: 32 0a jcc \(r3,r2\)
6: 33 0a jcc \(r4,r3\)
8: 44 0a jhi \(r5,r4\)
a: c5 0a jlt \(r6,r5\)
c: 66 0a jgt \(r7,r6\)
e: 87 0a jfs \(r8,r7\)
10: 98 0a jfc \(r9,r8\)
12: a9 0a jlo \(r10,r9\)
14: 4a 0a jhi \(r11,r10\)
16: c0 0a jlt \(r1,r0\)
18: d2 0a jge \(r3,r2\)
1a: e5 0a jump \(r6,r5\)
1c: f5 0a jusr \(r6,r5\)

21
gas/testsuite/gas/cr16/jcc_test.s Normal file
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.text
.global main
main:
##########
# JCond regp
##########
jeq (r1,r0)
jne (r2,r1)
jcc (r3,r2)
jcc (r4,r3)
jhi (r5,r4)
jlt (r6,r5)
jgt (r7,r6)
jfs (r8,r7)
jfc (r9,r8)
jlo (r10,r9)
jhi (r11,r10)
jlt (r1,r0)
jge (r3,r2)
jump (r6,r5)
jusr (r6,r5)

79
gas/testsuite/gas/cr16/loadb_test.d Normal file
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#as:
#objdump: -dr
#name: loadd_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 88 00 00 loadb 0x0 <main>:m,r0
4: 10 88 ff 00 loadb 0xff <main\+0xff>:m,r1
8: 30 88 ff 0f loadb 0xfff <main\+0xfff>:m,r3
c: 40 88 34 12 loadb 0x1234 <main\+0x1234>:m,r4
10: 50 88 34 12 loadb 0x1234 <main\+0x1234>:m,r5
14: 12 00 07 7a loadb 0x7a1234 <main\+0x7a1234>:l,r0
18: 34 12
1a: 12 00 1b 7a loadb 0xba1234 <main\+0xba1234>:l,r1
1e: 34 12
20: 2f 88 ff ff loadb 0xfffff <main\+0xfffff>:m,r2
24: 00 8a 00 00 loadb \[r12\]0x0:m,r0
28: 00 8b 00 00 loadb \[r12\]0x0:m,r0
2c: 10 8a ff 00 loadb \[r12\]0xff:m,r1
30: 10 8b ff 00 loadb \[r12\]0xff:m,r1
34: 30 8a ff 0f loadb \[r12\]0xfff:m,r3
38: 30 8b ff 0f loadb \[r12\]0xfff:m,r3
3c: 40 8a 34 12 loadb \[r13\]0x1234:m,r4
40: 40 8b 34 12 loadb \[r13\]0x1234:m,r4
44: 50 8a 34 12 loadb \[r13\]0x1234:m,r5
48: 50 8b 34 12 loadb \[r13\]0x1234:m,r5
4c: 20 8a 67 45 loadb \[r12\]0x4567:m,r2
50: 2a 8b 34 12 loadb \[r12\]0xa1234:m,r2
54: 10 b4 loadb 0x4:s\(r1,r0\),r1
56: 32 b4 loadb 0x4:s\(r3,r2\),r3
58: 40 bf 34 12 loadb 0x1234:m\(r1,r0\),r4
5c: 52 bf 34 12 loadb 0x1234:m\(r3,r2\),r5
60: 12 00 60 5a loadb 0xa1234:l\(r1,r0\),r6
64: 34 12
66: 18 00 10 5f loadb 0xffffc:l\(r1,r0\),r1
6a: fc ff
6c: 18 00 32 5f loadb 0xffffc:l\(r3,r2\),r3
70: fc ff
72: 18 00 40 5f loadb 0xfedcc:l\(r1,r0\),r4
76: cc ed
78: 18 00 52 5f loadb 0xfedcc:l\(r3,r2\),r5
7c: cc ed
7e: 18 00 60 55 loadb 0x5edcc:l\(r1,r0\),r6
82: cc ed
84: 00 b0 loadb 0x0:s\(r1,r0\),r0
86: 10 b0 loadb 0x0:s\(r1,r0\),r1
88: 00 bf 0f 00 loadb 0xf:m\(r1,r0\),r0
8c: 10 bf 0f 00 loadb 0xf:m\(r1,r0\),r1
90: 20 bf 34 12 loadb 0x1234:m\(r1,r0\),r2
94: 32 bf cd ab loadb 0xabcd:m\(r3,r2\),r3
98: 43 bf ff af loadb 0xafff:m\(r4,r3\),r4
9c: 12 00 55 5a loadb 0xa1234:l\(r6,r5\),r5
a0: 34 12
a2: 18 00 00 5f loadb 0xffff1:l\(r1,r0\),r0
a6: f1 ff
a8: 18 00 10 5f loadb 0xffff1:l\(r1,r0\),r1
ac: f1 ff
ae: 18 00 20 5f loadb 0xfedcc:l\(r1,r0\),r2
b2: cc ed
b4: 18 00 32 5f loadb 0xf5433:l\(r3,r2\),r3
b8: 33 54
ba: 18 00 43 5f loadb 0xf5001:l\(r4,r3\),r4
be: 01 50
c0: 18 00 55 55 loadb 0x5edcc:l\(r6,r5\),r5
c4: cc ed
c6: 00 be loadb \[r12\]0x0:s\(r1,r0\),r0
c8: 18 be loadb \[r13\]0x0:s\(r1,r0\),r1
ca: 70 86 04 12 loadb \[r12\]0x234:m\(r1,r0\),r7
ce: 12 00 38 61 loadb \[r13\]0x1abcd:l\(r1,r0\),r3
d2: cd ab
d4: 12 00 40 6a loadb \[r12\]0xa1234:l\(r1,r0\),r4
d8: 34 12
da: 12 00 58 6b loadb \[r13\]0xb1234:l\(r1,r0\),r5
de: 34 12
e0: 12 00 68 6f loadb \[r13\]0xfffff:l\(r1,r0\),r6
e4: ff ff

72
gas/testsuite/gas/cr16/loadb_test.s Normal file
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.text
.global main
main:
######################
# loadb abs20/24 reg
######################
loadb 0x0,r0
loadb 0xff,r1
loadb 0xfff,r3
loadb 0x1234,r4
loadb 0x1234,r5
loadb 0x7A1234,r0
loadb 0xBA1234,r1
loadb 0xffffff,r2
######################
# loadb abs20 rel reg
######################
loadb [r12]0x0,r0
loadb [r13]0x0,r0
loadb [r12]0xff,r1
loadb [r13]0xff,r1
loadb [r12]0xfff,r3
loadb [r13]0xfff,r3
loadb [r12]0x1234,r4
loadb [r13]0x1234,r4
loadb [r12]0x1234,r5
loadb [r13]0x1234,r5
loadb [r12]0x4567,r2
loadb [r13]0xA1234,r2
###################################
# loadb rbase(disp20/-disp20) reg
###################################
loadb 0x4(r1,r0),r1
loadb 0x4(r3,r2),r3
loadb 0x1234(r1,r0),r4
loadb 0x1234(r3,r2),r5
loadb 0xA1234(r1,r0),r6
loadb -0x4(r1,r0),r1
loadb -0x4(r3,r2),r3
loadb -0x1234(r1,r0),r4
loadb -0x1234(r3,r2),r5
loadb -0xA1234(r1,r0),r6
#################################################
# loadb rpbase(disp4/disp16/disp20/-disp20) reg
#################################################
loadb 0x0(r1,r0),r0
loadb 0x0(r1,r0),r1
loadb 0xf(r1,r0),r0
loadb 0xf(r1,r0),r1
loadb 0x1234(r1,r0),r2
loadb 0xabcd(r3,r2),r3
loadb 0xAfff(r4,r3),r4
loadb 0xA1234(r6,r5),r5
loadb -0xf(r1,r0),r0
loadb -0xf(r1,r0),r1
loadb -0x1234(r1,r0),r2
loadb -0xabcd(r3,r2),r3
loadb -0xAfff(r4,r3),r4
loadb -0xA1234(r6,r5),r5
####################################
# loadb rbase(disp0/disp14) rel reg
####################################
loadb [r12]0x0(r1,r0),r0
loadb [r13]0x0(r1,r0),r1
loadb [r12]0x1234(r1,r0),r2
loadb [r13]0x1abcd(r1,r0),r3
#################################
# loadb rpbase(disp20) rel reg
#################################
loadb [r12]0xA1234(r1,r0),r4
loadb [r13]0xB1234(r1,r0),r5
loadb [r13]0xfffff(r1,r0),r6

79
gas/testsuite/gas/cr16/loadd_test.d Normal file
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#as:
#objdump: -dr
#name: loadd_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 87 00 00 loadd 0x0 <main>:m,\(r1,r0\)
4: 00 87 ff 00 loadd 0xff <main\+0xff>:m,\(r1,r0\)
8: 20 87 ff 0f loadd 0xfff <main\+0xfff>:m,\(r3,r2\)
c: 30 87 34 12 loadd 0x1234 <main\+0x1234>:m,\(r4,r3\)
10: 40 87 34 12 loadd 0x1234 <main\+0x1234>:m,\(r5,r4\)
14: 12 00 07 ba loadd 0x7a1234 <main\+0x7a1234>:l,\(r1,r0\)
18: 34 12
1a: 12 00 0b ba loadd 0xba1234 <main\+0xba1234>:l,\(r1,r0\)
1e: 34 12
20: 1f 87 ff ff loadd 0xfffff <main\+0xfffff>:m,\(r2,r1\)
24: 00 8c 00 00 loadd \[r12\]0x0:m,\(r1,r0\)
28: 00 8d 00 00 loadd \[r12\]0x0:m,\(r1,r0\)
2c: 00 8c ff 00 loadd \[r12\]0xff:m,\(r1,r0\)
30: 00 8d ff 00 loadd \[r12\]0xff:m,\(r1,r0\)
34: 20 8c ff 0f loadd \[r12\]0xfff:m,\(r3,r2\)
38: 20 8d ff 0f loadd \[r12\]0xfff:m,\(r3,r2\)
3c: 30 8c 34 12 loadd \[r12\]0x1234:m,\(r4,r3\)
40: 30 8d 34 12 loadd \[r12\]0x1234:m,\(r4,r3\)
44: 40 8c 34 12 loadd \[r13\]0x1234:m,\(r5,r4\)
48: 40 8d 34 12 loadd \[r13\]0x1234:m,\(r5,r4\)
4c: 10 8c 67 45 loadd \[r12\]0x4567:m,\(r2,r1\)
50: 1a 8d 34 12 loadd \[r12\]0xa1234:m,\(r2,r1\)
54: 10 a2 loadd 0x4:s\(r1,r0\),\(r2,r1\)
56: 22 a2 loadd 0x4:s\(r3,r2\),\(r3,r2\)
58: 30 af 34 12 loadd 0x1234:m\(r1,r0\),\(r4,r3\)
5c: 42 af 34 12 loadd 0x1234:m\(r3,r2\),\(r5,r4\)
60: 12 00 50 9a loadd 0xa1234:l\(r1,r0\),\(r6,r5\)
64: 34 12
66: 18 00 10 9f loadd 0xffffc:l\(r1,r0\),\(r2,r1\)
6a: fc ff
6c: 18 00 22 9f loadd 0xffffc:l\(r3,r2\),\(r3,r2\)
70: fc ff
72: 18 00 30 9f loadd 0xfedcc:l\(r1,r0\),\(r4,r3\)
76: cc ed
78: 18 00 42 9f loadd 0xfedcc:l\(r3,r2\),\(r5,r4\)
7c: cc ed
7e: 18 00 50 95 loadd 0x5edcc:l\(r1,r0\),\(r6,r5\)
82: cc ed
84: 00 a0 loadd 0x0:s\(r1,r0\),\(r1,r0\)
86: 00 a0 loadd 0x0:s\(r1,r0\),\(r1,r0\)
88: 00 af 0f 00 loadd 0xf:m\(r1,r0\),\(r1,r0\)
8c: 00 af 0f 00 loadd 0xf:m\(r1,r0\),\(r1,r0\)
90: 10 af 34 12 loadd 0x1234:m\(r1,r0\),\(r2,r1\)
94: 22 af cd ab loadd 0xabcd:m\(r3,r2\),\(r3,r2\)
98: 33 af ff af loadd 0xafff:m\(r4,r3\),\(r4,r3\)
9c: 12 00 65 9a loadd 0xa1234:l\(r6,r5\),\(r7,r6\)
a0: 34 12
a2: 18 00 00 9f loadd 0xffff1:l\(r1,r0\),\(r1,r0\)
a6: f1 ff
a8: 18 00 00 9f loadd 0xffff1:l\(r1,r0\),\(r1,r0\)
ac: f1 ff
ae: 18 00 10 9f loadd 0xfedcc:l\(r1,r0\),\(r2,r1\)
b2: cc ed
b4: 18 00 22 9f loadd 0xf5433:l\(r3,r2\),\(r3,r2\)
b8: 33 54
ba: 18 00 43 9f loadd 0xf5001:l\(r4,r3\),\(r5,r4\)
be: 01 50
c0: 18 00 45 95 loadd 0x5edcc:l\(r6,r5\),\(r5,r4\)
c4: cc ed
c6: 00 ae loadd \[r12\]0x0:s\(r1,r0\),\(r1,r0\)
c8: 08 ae loadd \[r13\]0x0:s\(r1,r0\),\(r1,r0\)
ca: b0 86 04 12 loadd \[r12\]0x234:m\(r1,r0\),\(r12,r11\)
ce: 12 00 28 a1 loadd \[r13\]0x1abcd:l\(r1,r0\),\(r3,r2\)
d2: cd ab
d4: 12 00 20 aa loadd \[r12\]0xa1234:l\(r1,r0\),\(r3,r2\)
d8: 34 12
da: 12 00 38 ab loadd \[r13\]0xb1234:l\(r1,r0\),\(r4,r3\)
de: 34 12
e0: 12 00 48 af loadd \[r13\]0xfffff:l\(r1,r0\),\(r5,r4\)
e4: ff ff

72
gas/testsuite/gas/cr16/loadd_test.s Normal file
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.text
.global main
main:
######################
# loadd abs20/24 regp
######################
loadd 0x0,(r1,r0)
loadd 0xff,(r1,r0)
loadd 0xfff,(r3,r2)
loadd 0x1234,(r4,r3)
loadd 0x1234,(r5,r4)
loadd 0x7A1234,(r1,r0)
loadd 0xBA1234,(r1,r0)
loadd 0xffffff,(r2,r1)
######################
# loadd abs20 rel regp
######################
loadd [r12]0x0,(r1,r0)
loadd [r13]0x0,(r1,r0)
loadd [r12]0xff,(r1,r0)
loadd [r13]0xff,(r1,r0)
loadd [r12]0xfff,(r3,r2)
loadd [r13]0xfff,(r3,r2)
loadd [r12]0x1234,(r4,r3)
loadd [r13]0x1234,(r4,r3)
loadd [r12]0x1234,(r5,r4)
loadd [r13]0x1234,(r5,r4)
loadd [r12]0x4567,(r2,r1)
loadd [r13]0xA1234,(r2,r1)
###################################
# loadd rbase(disp20/-disp20) regp
###################################
loadd 0x4(r1,r0),(r2,r1)
loadd 0x4(r3,r2),(r3,r2)
loadd 0x1234(r1,r0),(r4,r3)
loadd 0x1234(r3,r2),(r5,r4)
loadd 0xA1234(r1,r0),(r6,r5)
loadd -0x4(r1,r0),(r2,r1)
loadd -0x4(r3,r2),(r3,r2)
loadd -0x1234(r1,r0),(r4,r3)
loadd -0x1234(r3,r2),(r5,r4)
loadd -0xA1234(r1,r0),(r6,r5)
#################################################
# loadd rpbase(disp4/disp16/disp20/-disp20) reg
#################################################
loadd 0x0(r1,r0),(r1,r0)
loadd 0x0(r1,r0),(r1,r0)
loadd 0xf(r1,r0),(r1,r0)
loadd 0xf(r1,r0),(r1,r0)
loadd 0x1234(r1,r0),(r2,r1)
loadd 0xabcd(r3,r2),(r3,r2)
loadd 0xAfff(r4,r3),(r4,r3)
loadd 0xA1234(r6,r5),(r7,r6)
loadd -0xf(r1,r0),(r1,r0)
loadd -0xf(r1,r0),(r1,r0)
loadd -0x1234(r1,r0),(r2,r1)
loadd -0xabcd(r3,r2),(r3,r2)
loadd -0xAfff(r4,r3),(r5,r4)
loadd -0xA1234(r6,r5),(r5,r4)
####################################
# loadd rbase(disp0/disp14) rel reg
####################################
loadd [r12]0x0(r1,r0),(r1,r0)
loadd [r13]0x0(r1,r0),(r1,r0)
loadd [r12]0x1234(r1,r0),(r2,r1)
loadd [r13]0x1abcd(r1,r0),(r3,r2)
#################################
# loadd rpbase(disp20) rel reg
#################################
loadd [r12]0xA1234(r1,r0),(r3,r2)
loadd [r13]0xB1234(r1,r0),(r4,r3)
loadd [r13]0xfffff(r1,r0),(r5,r4)

25
gas/testsuite/gas/cr16/loadm_test.d Normal file
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#as:
#objdump: -dr
#name: loadm_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: a0 00 loadm \$0x1,r0
2: a1 00 loadm \$0x2,r0
4: a2 00 loadm \$0x3,r0
6: a3 00 loadm \$0x4,r0
8: a4 00 loadm \$0x5,r0
a: a5 00 loadm \$0x6,r0
c: a6 00 loadm \$0x7,r0
e: a7 00 loadm \$0x8,r0
10: a8 00 loadmp \$0x1,r0
12: a9 00 loadmp \$0x2,r0
14: aa 00 loadmp \$0x3,r0
16: ab 00 loadmp \$0x4,r0
18: ac 00 loadmp \$0x5,r0
1a: ad 00 loadmp \$0x6,r0
1c: ae 00 loadmp \$0x7,r0
1e: af 00 loadmp \$0x8,r0

25
gas/testsuite/gas/cr16/loadm_test.s Normal file
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.text
.global main
main:
##############
# loadm cnt
##############
loadm $1
loadm $2
loadm $3
loadm $4
loadm $5
loadm $6
loadm $7
loadm $8
##############
# loadmp cnt
##############
loadmp $1
loadmp $2
loadmp $3
loadmp $4
loadmp $5
loadmp $6
loadmp $7
loadmp $8

79
gas/testsuite/gas/cr16/loadw_test.d Normal file
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#as:
#objdump: -dr
#name: loadw_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 89 00 00 loadw 0x0 <main>:m,r0
4: 10 89 ff 00 loadw 0xff <main\+0xff>:m,r1
8: 30 89 ff 0f loadw 0xfff <main\+0xfff>:m,r3
c: 40 89 34 12 loadw 0x1234 <main\+0x1234>:m,r4
10: 50 89 34 12 loadw 0x1234 <main\+0x1234>:m,r5
14: 12 00 07 fa loadw 0x7a1234 <main\+0x7a1234>:l,r0
18: 34 12
1a: 12 00 1b fa loadw 0xba1234 <main\+0xba1234>:l,r1
1e: 34 12
20: 2f 89 ff ff loadw 0xfffff <main\+0xfffff>:m,r2
24: 00 8e 00 00 loadw \[r12\]0x0:m,r0
28: 00 8f 00 00 loadw \[r12\]0x0:m,r0
2c: 10 8e ff 00 loadw \[r12\]0xff:m,r1
30: 10 8f ff 00 loadw \[r12\]0xff:m,r1
34: 30 8e ff 0f loadw \[r12\]0xfff:m,r3
38: 30 8f ff 0f loadw \[r12\]0xfff:m,r3
3c: 40 8e 34 12 loadw \[r13\]0x1234:m,r4
40: 40 8f 34 12 loadw \[r13\]0x1234:m,r4
44: 50 8e 34 12 loadw \[r13\]0x1234:m,r5
48: 50 8f 34 12 loadw \[r13\]0x1234:m,r5
4c: 20 8e 67 45 loadw \[r12\]0x4567:m,r2
50: 2a 8f 34 12 loadw \[r12\]0xa1234:m,r2
54: 10 92 loadw 0x4:s\(r1,r0\),r1
56: 32 92 loadw 0x4:s\(r3,r2\),r3
58: 40 9f 34 12 loadw 0x1234:m\(r1,r0\),r4
5c: 52 9f 34 12 loadw 0x1234:m\(r3,r2\),r5
60: 12 00 60 da loadw 0xa1234:l\(r1,r0\),r6
64: 34 12
66: 18 00 10 df loadw 0xffffc:l\(r1,r0\),r1
6a: fc ff
6c: 18 00 32 df loadw 0xffffc:l\(r3,r2\),r3
70: fc ff
72: 18 00 40 df loadw 0xfedcc:l\(r1,r0\),r4
76: cc ed
78: 18 00 52 df loadw 0xfedcc:l\(r3,r2\),r5
7c: cc ed
7e: 18 00 60 d5 loadw 0x5edcc:l\(r1,r0\),r6
82: cc ed
84: 00 90 loadw 0x0:s\(r1,r0\),r0
86: 10 90 loadw 0x0:s\(r1,r0\),r1
88: 00 9f 0f 00 loadw 0xf:m\(r1,r0\),r0
8c: 10 9f 0f 00 loadw 0xf:m\(r1,r0\),r1
90: 20 9f 34 12 loadw 0x1234:m\(r1,r0\),r2
94: 32 9f cd ab loadw 0xabcd:m\(r3,r2\),r3
98: 43 9f ff af loadw 0xafff:m\(r4,r3\),r4
9c: 12 00 55 da loadw 0xa1234:l\(r6,r5\),r5
a0: 34 12
a2: 18 00 00 df loadw 0xffff1:l\(r1,r0\),r0
a6: f1 ff
a8: 18 00 10 df loadw 0xffff1:l\(r1,r0\),r1
ac: f1 ff
ae: 18 00 20 df loadw 0xfedcc:l\(r1,r0\),r2
b2: cc ed
b4: 18 00 32 df loadw 0xf5433:l\(r3,r2\),r3
b8: 33 54
ba: 18 00 43 df loadw 0xf5001:l\(r4,r3\),r4
be: 01 50
c0: 18 00 55 d5 loadw 0x5edcc:l\(r6,r5\),r5
c4: cc ed
c6: 00 9e loadw \[r12\]0x0:s\(r1,r0\),r0
c8: 18 9e loadw \[r13\]0x0:s\(r1,r0\),r1
ca: f0 86 04 12 loadw \[r12\]0x234:m\(r1,r0\),r15
ce: 12 00 38 e1 loadw \[r13\]0x1abcd:l\(r1,r0\),r3
d2: cd ab
d4: 12 00 40 ea loadw \[r12\]0xa1234:l\(r1,r0\),r4
d8: 34 12
da: 12 00 58 eb loadw \[r13\]0xb1234:l\(r1,r0\),r5
de: 34 12
e0: 12 00 68 ef loadw \[r13\]0xfffff:l\(r1,r0\),r6
e4: ff ff

72
gas/testsuite/gas/cr16/loadw_test.s Normal file
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.text
.global main
main:
######################
# loadw abs20/24 reg
######################
loadw 0x0,r0
loadw 0xff,r1
loadw 0xfff,r3
loadw 0x1234,r4
loadw 0x1234,r5
loadw 0x7A1234,r0
loadw 0xBA1234,r1
loadw 0xffffff,r2
######################
# loadw abs20 rel reg
######################
loadw [r12]0x0,r0
loadw [r13]0x0,r0
loadw [r12]0xff,r1
loadw [r13]0xff,r1
loadw [r12]0xfff,r3
loadw [r13]0xfff,r3
loadw [r12]0x1234,r4
loadw [r13]0x1234,r4
loadw [r12]0x1234,r5
loadw [r13]0x1234,r5
loadw [r12]0x4567,r2
loadw [r13]0xA1234,r2
###################################
# loadw rbase(disp20/-disp20) reg
###################################
loadw 0x4(r1,r0),r1
loadw 0x4(r3,r2),r3
loadw 0x1234(r1,r0),r4
loadw 0x1234(r3,r2),r5
loadw 0xA1234(r1,r0),r6
loadw -0x4(r1,r0),r1
loadw -0x4(r3,r2),r3
loadw -0x1234(r1,r0),r4
loadw -0x1234(r3,r2),r5
loadw -0xA1234(r1,r0),r6
#################################################
# loadw rpbase(disp4/disp16/disp20/-disp20) reg
#################################################
loadw 0x0(r1,r0),r0
loadw 0x0(r1,r0),r1
loadw 0xf(r1,r0),r0
loadw 0xf(r1,r0),r1
loadw 0x1234(r1,r0),r2
loadw 0xabcd(r3,r2),r3
loadw 0xAfff(r4,r3),r4
loadw 0xA1234(r6,r5),r5
loadw -0xf(r1,r0),r0
loadw -0xf(r1,r0),r1
loadw -0x1234(r1,r0),r2
loadw -0xabcd(r3,r2),r3
loadw -0xAfff(r4,r3),r4
loadw -0xA1234(r6,r5),r5
####################################
# loadw rbase(disp0/disp14) rel reg
####################################
loadw [r12]0x0(r1,r0),r0
loadw [r13]0x0(r1,r0),r1
loadw [r12]0x1234(r1,r0),r2
loadw [r13]0x1abcd(r1,r0),r3
#################################
# loadw rpbase(disp20) rel reg
#################################
loadw [r12]0xA1234(r1,r0),r4
loadw [r13]0xB1234(r1,r0),r5
loadw [r13]0xfffff(r1,r0),r6

57
gas/testsuite/gas/cr16/lpsp_test.d Normal file
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#as:
#objdump: -dr
#name: lpsp_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 14 00 91 00 lpr r1,psr
4: 14 00 82 00 lpr r2,cfg
8: 14 00 a2 00 lpr r2,intbasel
c: 14 00 b3 00 lpr r3,intbaseh
10: 14 00 c4 00 lpr r4,ispl
14: 14 00 d5 00 lpr r5,isph
18: 14 00 e6 00 lpr r6,uspl
1c: 14 00 f7 00 lpr r7,usph
20: 14 00 18 00 lpr r8,dsr
24: 14 00 29 00 lpr r9,dcrl
28: 14 00 3a 00 lpr r10,dcrh
2c: 14 00 4b 00 lpr r11,car0l
30: 14 00 50 00 lpr r0,car0h
34: 14 00 61 00 lpr r1,car1l
38: 14 00 73 00 lpr r3,car1h
3c: 14 00 90 10 lprd \(r1,r0\),psr
40: 14 00 81 10 lprd \(r2,r1\),cfg
44: 14 00 a2 10 lprd \(r3,r2\),intbase
48: 14 00 c3 10 lprd \(r4,r3\),isp
4c: 14 00 e4 10 lprd \(r5,r4\),usp
50: 14 00 15 10 lprd \(r6,r5\),dsr
54: 14 00 26 10 lprd \(r7,r6\),dcr
58: 14 00 47 10 lprd \(r8,r7\),car0
5c: 14 00 68 10 lprd \(r9,r8\),car1
60: 14 00 90 20 spr psr,r0
64: 14 00 81 20 spr cfg,r1
68: 14 00 a2 20 spr intbasel,r2
6c: 14 00 b3 20 spr intbaseh,r3
70: 14 00 c4 20 spr ispl,r4
74: 14 00 d5 20 spr isph,r5
78: 14 00 e6 20 spr uspl,r6
7c: 14 00 f7 20 spr usph,r7
80: 14 00 18 20 spr dsr,r8
84: 14 00 29 20 spr dcrl,r9
88: 14 00 3a 20 spr dcrh,r10
8c: 14 00 4b 20 spr car0l,r11
90: 14 00 50 20 spr car0h,r0
94: 14 00 61 20 spr car1l,r1
98: 14 00 72 20 spr car1h,r2
9c: 14 00 90 30 sprd psr,\(r1,r0\)
a0: 14 00 81 30 sprd cfg,\(r2,r1\)
a4: 14 00 a2 30 sprd intbase,\(r3,r2\)
a8: 14 00 c3 30 sprd isp,\(r4,r3\)
ac: 14 00 e4 30 sprd usp,\(r5,r4\)
b0: 14 00 15 30 sprd dsr,\(r6,r5\)
b4: 14 00 26 30 sprd dcr,\(r7,r6\)
b8: 14 00 47 30 sprd car0,\(r8,r7\)
bc: 14 00 68 30 sprd car1,\(r9,r8\)

63
gas/testsuite/gas/cr16/lpsp_test.s Normal file
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.text
.global main
main:
################
# lpr reg, preg
################
lpr r1,psr
lpr r2,cfg
lpr r2,intbasel
lpr r3,intbaseh
lpr r4,ispl
lpr r5,isph
lpr r6,uspl
lpr r7,usph
lpr r8,dsr
lpr r9,dcrl
lpr r10,dcrh
lpr r11,car0l
lpr r0,car0h
lpr r1,car1l
lpr r3,car1h
#################
# lprd regp, preg
#################
lprd (r1,r0),psr
lprd (r2,r1),cfg
lprd (r3,r2),intbase
lprd (r4,r3),isp
lprd (r5,r4),usp
lprd (r6,r5),dsr
lprd (r7,r6),dcr
lprd (r8,r7),car0
lprd (r9,r8),car1
#################
# spr preg, reg
#################
spr psr,r0
spr cfg,r1
spr intbasel,r2
spr intbaseh,r3
spr ispl,r4
spr isph,r5
spr uspl,r6
spr usph,r7
spr dsr,r8
spr dcrl,r9
spr dcrh,r10
spr car0l,r11
spr car0h,r0
spr car1l,r1
spr car1h,r2
#################
# sprd preg, regp
#################
sprd psr,(r1,r0)
sprd cfg,(r2,r1)
sprd intbase,(r3,r2)
sprd isp,(r4,r3)
sprd usp,(r5,r4)
sprd dsr,(r6,r5)
sprd dcr,(r7,r6)
sprd car0,(r8,r7)
sprd car1,(r9,r8)

47
gas/testsuite/gas/cr16/lsh_test.d Normal file
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#as:
#objdump: -dr
#name: lsh_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 71 40 ashub \$7:s,r1
2: 91 09 lshb \$-7:s,r1
4: 41 40 ashub \$4:s,r1
6: c1 09 lshb \$-4:s,r1
8: 81 09 lshb \$-8:s,r1
a: 31 40 ashub \$3:s,r1
c: d1 09 lshb \$-3:s,r1
e: 21 44 lshb r2,r1
10: 34 44 lshb r3,r4
12: 56 44 lshb r5,r6
14: 8a 44 lshb r8,r10
16: 71 42 ashuw \$7:s,r1
18: 91 49 lshw \$-7:s,r1
1a: 41 42 ashuw \$4:s,r1
1c: c1 49 lshw \$-4:s,r1
1e: 81 42 ashuw \$8:s,r1
20: 81 49 lshw \$-8:s,r1
22: 31 42 ashuw \$3:s,r1
24: d1 49 lshw \$-3:s,r1
26: 21 46 lshw r2,r1
28: 34 46 lshw r3,r4
2a: 56 46 lshw r5,r6
2c: 8a 46 lshw r8,r10
2e: 72 4c ashud \$7:s,\(r3,r2\)
30: 92 4b lshd \$-7:s,\(r3,r2\)
32: 82 4c ashud \$8:s,\(r3,r2\)
34: 82 4b lshd \$-8:s,\(r3,r2\)
36: 42 4c ashud \$4:s,\(r3,r2\)
38: c2 4b lshd \$-4:s,\(r3,r2\)
3a: c2 4c ashud \$12:s,\(r3,r2\)
3c: 42 4b lshd \$-12:s,\(r3,r2\)
3e: 31 4c ashud \$3:s,\(r2,r1\)
40: d1 4b lshd \$-3:s,\(r2,r1\)
42: 41 47 lshd r4,\(r2,r1\)
44: 51 47 lshd r5,\(r2,r1\)
46: 61 47 lshd r6,\(r2,r1\)
48: 81 47 lshd r8,\(r2,r1\)
4a: 11 47 lshd r1,\(r2,r1\)

59
gas/testsuite/gas/cr16/lsh_test.s Normal file
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.text
.global main
main:
###########################
# LSHB cnt(right -), reg
###########################
lshb $7,r1
lshb $-7,r1
lshb $4,r1
lshb $-4,r1
lshb $-8,r1
lshb $3,r1
lshb $-3,r1
###########################
# LSHB reg, reg
###########################
lshb r2,r1
lshb r3,r4
lshb r5,r6
lshb r8,r10
###########################
# LSHW cnt (right -), reg
###########################
lshw $7,r1
lshw $-7,r1
lshw $4,r1
lshw $-4,r1
lshw $8,r1
lshw $-8,r1
lshw $3,r1
lshw $-3,r1
##########################
# LSHW reg, reg
##########################
lshw r2,r1
lshw r3,r4
lshw r5,r6
lshw r8,r10
###########################
# LSHD cnt (right -), regp
############################
lshd $7, (r3,r2)
lshd $-7, (r3,r2)
lshd $8, (r3,r2)
lshd $-8, (r3,r2)
lshd $4, (r3,r2)
lshd $-4, (r3,r2)
lshd $12,(r3,r2)
lshd $-12,(r3,r2)
lshd $3,(r2,r1)
lshd $-3,(r2,r1)
#################
# LSHD reg, regp
#################
lshd r4,(r2,r1)
lshd r5,(r2,r1)
lshd r6,(r2,r1)
lshd r8,(r2,r1)
lshd r1,(r2,r1)

69
gas/testsuite/gas/cr16/mov_test.d Normal file
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#as:
#objdump: -dr
#name: mov_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 58 movb \$0xf:s,r1
2: b2 58 ff 00 movb \$0xff:m,r2
6: b1 58 ff 0f movb \$0xfff:m,r1
a: b1 58 14 00 movb \$0x14:m,r1
e: a2 58 movb \$0xa:s,r2
10: b2 58 0b 00 movb \$0xb:m,r2
14: 12 59 movb r1,r2
16: 23 59 movb r2,r3
18: 34 59 movb r3,r4
1a: 56 59 movb r5,r6
1c: 67 59 movb r6,r7
1e: 78 59 movb r7,r8
20: f1 5a movw \$0xf:s,r1
22: b1 5a 0b 00 movw \$0xb:m,r1
26: b2 5a ff 00 movw \$0xff:m,r2
2a: b1 5a ff 0f movw \$0xfff:m,r1
2e: b1 5a 14 00 movw \$0x14:m,r1
32: a2 5a movw \$0xa:s,r2
34: b2 5a 0b 00 movw \$0xb:m,r2
38: 12 5b movw r1,r2
3a: 23 5b movw r2,r3
3c: 34 5b movw r3,r4
3e: 56 5b movw r5,r6
40: 67 5b movw r6,r7
42: 78 5b movw r7,r8
44: f1 54 movd \$0xf:s,\(r2,r1\)
46: b1 54 0b 00 movd \$0xb:m,\(r2,r1\)
4a: b1 54 ff 00 movd \$0xff:m,\(r2,r1\)
4e: b1 54 ff 0f movd \$0xfff:m,\(r2,r1\)
52: 10 05 ff ff movd \$0xffff:m,\(r2,r1\)
56: 1f 05 ff ff movd \$0xfffff:m,\(r2,r1\)
5a: 71 00 ff 0f movd \$0xfffffff:l,\(r2,r1\)
5e: ff ff
60: 91 54 movd \$-1:s,\(r2,r1\)
62: 31 55 movd \(r4,r3\),\(r2,r1\)
64: 31 55 movd \(r4,r3\),\(r2,r1\)
66: af 54 movd \$0xa:s,\(sp\)
68: ef 54 movd \$0xe:s,\(sp\)
6a: bf 54 0b 00 movd \$0xb:m,\(sp\)
6e: 8f 54 movd \$0x8:s,\(sp\)
70: 12 5c movxb r1,r2
72: 34 5c movxb r3,r4
74: 56 5c movxb r5,r6
76: 78 5c movxb r7,r8
78: 9a 5c movxb r9,r10
7a: 12 5e movxw r1,\(r3,r2\)
7c: 33 5e movxw r3,\(r4,r3\)
7e: 55 5e movxw r5,\(r6,r5\)
80: 77 5e movxw r7,\(r8,r7\)
82: 98 5e movxw r9,\(r9,r8\)
84: 12 5d movzb r1,r2
86: 34 5d movzb r3,r4
88: 56 5d movzb r5,r6
8a: 78 5d movzb r7,r8
8c: 9a 5d movzb r9,r10
8e: 12 5f movzw r1,\(r3,r2\)
90: 33 5f movzw r3,\(r4,r3\)
92: 55 5f movzw r5,\(r6,r5\)
94: 77 5f movzw r7,\(r8,r7\)
96: 98 5f movzw r9,\(r9,r8\)

94
gas/testsuite/gas/cr16/mov_test.s Normal file
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.text
.global main
main:
###########
# MOVB imm4/imm16, reg
###########
movb $0xf,r1
movb $0xff,r2
movb $0xfff,r1
#movb $0xffff,r2 // CHECK WITH CRASM 4.1
movb $20,r1
movb $10,r2
movb $11,r2
###########
# MOVB reg, reg
###########
movb r1,r2
movb r2,r3
movb r3,r4
movb r5,r6
movb r6,r7
movb r7,r8
###########
# MOVW imm4/imm16, reg
###########
movw $0xf,r1
movw $0xB,r1
movw $0xff,r2
movw $0xfff,r1
#movw $0xffff,r2 // CHECK WITH CRASM 4.1
movw $20,r1
movw $10,r2
movw $11,r2
###########
# MOVW reg, reg
###########
movw r1,r2
movw r2,r3
movw r3,r4
movw r5,r6
movw r6,r7
movw r7,r8
###########
# MOVD imm4/imm16/imm20/imm32, regp
###########
movd $0xf,(r2,r1)
movd $0xB,(r2,r1)
movd $0xff,(r2,r1)
movd $0xfff,(r2,r1)
movd $0xffff,(r2,r1)
movd $0xfffff,(r2,r1)
movd $0xfffffff,(r2,r1)
movd $0xffffffff,(r2,r1)
###########
# MOVD regp, regp
###########
movd (r4,r3),(r2,r1)
movd (r4,r3),(r2,r1)
movd $10,(sp)
movd $14,(sp)
movd $11,(sp)
movd $8,(sp)
###########
# MOVXB reg, reg
###########
movxb r1,r2
movxb r3,r4
movxb r5,r6
movxb r7,r8
movxb r9,r10
###########
# MOVXW reg, regp
###########
movxw r1,(r3,r2)
movxw r3,(r4,r3)
movxw r5,(r6,r5)
movxw r7,(r8,r7)
movxw r9,(r9,r8)
###########
# MOVZB reg, reg
###########
movzb r1,r2
movzb r3,r4
movzb r5,r6
movzb r7,r8
movzb r9,r10
###########
# MOVZW reg, regp
###########
movzw r1,(r3,r2)
movzw r3,(r4,r3)
movzw r5,(r6,r5)
movzw r7,(r8,r7)
movzw r9,(r9,r8)

47
gas/testsuite/gas/cr16/mul_test.d Normal file
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#as:
#objdump: -dr
#name: mul_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 64 mulb \$0xf:s,r1
2: b2 64 ff 00 mulb \$0xff:m,r2
6: b1 64 ff 0f mulb \$0xfff:m,r1
a: b1 64 14 00 mulb \$0x14:m,r1
e: a2 64 mulb \$0xa:s,r2
10: 12 65 mulb r1,r2
12: 23 65 mulb r2,r3
14: 34 65 mulb r3,r4
16: 56 65 mulb r5,r6
18: 67 65 mulb r6,r7
1a: 78 65 mulb r7,r8
1c: f1 66 mulw \$0xf:s,r1
1e: b2 66 ff 00 mulw \$0xff:m,r2
22: b1 66 ff 0f mulw \$0xfff:m,r1
26: b1 66 14 00 mulw \$0x14:m,r1
2a: a2 66 mulw \$0xa:s,r2
2c: 12 67 mulw r1,r2
2e: 23 67 mulw r2,r3
30: 34 67 mulw r3,r4
32: 56 67 mulw r5,r6
34: 67 67 mulw r6,r7
36: 78 67 mulw r7,r8
38: 12 0b mulsb r1,r2
3a: 34 0b mulsb r3,r4
3c: 56 0b mulsb r5,r6
3e: 78 0b mulsb r7,r8
40: 9a 0b mulsb r9,r10
42: 12 62 mulsw r1,\(r3,r2\)
44: 33 62 mulsw r3,\(r4,r3\)
46: 55 62 mulsw r5,\(r6,r5\)
48: 77 62 mulsw r7,\(r8,r7\)
4a: 98 62 mulsw r9,\(r9,r8\)
4c: 14 00 12 d2 macqw r1,r2,\(r3,r2\)
50: 14 00 45 d4 macqw r4,r5,\(r5,r4\)
54: 14 00 12 e2 macuw r1,r2,\(r3,r2\)
58: 14 00 45 e7 macuw r4,r5,\(r8,r7\)
5c: 14 00 12 f2 macsw r1,r2,\(r3,r2\)
60: 14 00 45 f6 macsw r4,r5,\(r7,r6\)

64
gas/testsuite/gas/cr16/mul_test.s Normal file
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.text
.global main
main:
###########
# MULB imm4/imm16, reg
###########
mulb $0xf,r1
mulb $0xff,r2
mulb $0xfff,r1
#mulb $0xffff,r2 // CHCEK WITH CRASM 4.1
mulb $20,r1
mulb $10,r2
###########
# MULB reg, reg
###########
mulb r1,r2
mulb r2,r3
mulb r3,r4
mulb r5,r6
mulb r6,r7
mulb r7,r8
###########
# MULW imm4/imm16, reg
###########
mulw $0xf,r1
mulw $0xff,r2
mulw $0xfff,r1
#mulw $0xffff,r2 // CHCEK WITH CRASM 4.1
mulw $20,r1
mulw $10,r2
###########
# MULW reg, reg
###########
mulw r1,r2
mulw r2,r3
mulw r3,r4
mulw r5,r6
mulw r6,r7
mulw r7,r8
###########
# MULSB reg, reg
###########
mulsb r1,r2
mulsb r3,r4
mulsb r5,r6
mulsb r7,r8
mulsb r9,r10
###########
# MULSW reg, regp
###########
mulsw r1,(r3,r2)
mulsw r3,(r4,r3)
mulsw r5,(r6,r5)
mulsw r7,(r8,r7)
mulsw r9,(r9,r8)
#############################
# MUC[q/u/s/]w reg, reg, regp
#############################
macqw r1,r2,(r3,r2)
macqw r4,r5,(r5,r4)
macuw r1,r2,(r3,r2)
macuw r4,r5,(r8,r7)
macsw r1,r2,(r3,r2)
macsw r4,r5,(r7,r6)

49
gas/testsuite/gas/cr16/or_test.d Normal file
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#as:
#objdump: -dr
#name: or_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 24 orb \$0xf:s,r1
2: b2 24 ff 00 orb \$0xff:m,r2
6: b1 24 ff 0f orb \$0xfff:m,r1
a: b2 24 ff ff orb \$0xffff:m,r2
e: b1 24 14 00 orb \$0x14:m,r1
12: a2 24 orb \$0xa:s,r2
14: 12 25 orb r1,r2
16: 23 25 orb r2,r3
18: 34 25 orb r3,r4
1a: 56 25 orb r5,r6
1c: 67 25 orb r6,r7
1e: 78 25 orb r7,r8
20: f1 26 orw \$0xf:s,r1
22: b2 26 ff 00 orw \$0xff:m,r2
26: b1 26 ff 0f orw \$0xfff:m,r1
2a: b2 26 ff ff orw \$0xffff:m,r2
2e: b1 26 14 00 orw \$0x14:m,r1
32: a2 26 orw \$0xa:s,r2
34: 12 27 orw r1,r2
36: 23 27 orw r2,r3
38: 34 27 orw r3,r4
3a: 56 27 orw r5,r6
3c: 67 27 orw r6,r7
3e: 78 27 orw r7,r8
40: 51 00 00 00 ord \$0xf:l,\(r2,r1\)
44: 0f 00
46: 51 00 00 00 ord \$0xff:l,\(r2,r1\)
4a: ff 00
4c: 51 00 00 00 ord \$0xfff:l,\(r2,r1\)
50: ff 0f
52: 51 00 00 00 ord \$0xffff:l,\(r2,r1\)
56: ff ff
58: 51 00 0f 00 ord \$0xfffff:l,\(r2,r1\)
5c: ff ff
5e: 51 00 ff 0f ord \$0xfffffff:l,\(r2,r1\)
62: ff ff
64: 51 00 ff ff ord \$0xffffffff:l,\(r2,r1\)
68: ff ff
6a: 14 00 31 90 ord \(r4,r3\),\(r2,r1\)
6e: 14 00 31 90 ord \(r4,r3\),\(r2,r1\)

57
gas/testsuite/gas/cr16/or_test.s Normal file
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.text
.global main
main:
###########
# ORB imm4/imm16, reg
###########
orb $0xf,r1
orb $0xff,r2
orb $0xfff,r1
orb $0xffff,r2
orb $20,r1
orb $10,r2
###########
# ORB reg, reg
###########
orb r1,r2
orb r2,r3
orb r3,r4
orb r5,r6
orb r6,r7
orb r7,r8
###########
# ORW imm4/imm16, reg
###########
orw $0xf,r1
orw $0xff,r2
orw $0xfff,r1
orw $0xffff,r2
orw $20,r1
orw $10,r2
###########
# ORW reg, reg
###########
orw r1,r2
orw r2,r3
orw r3,r4
orw r5,r6
orw r6,r7
orw r7,r8
###########
# ORD imm32, regp
###########
ord $0xf,(r2,r1)
ord $0xff,(r2,r1)
ord $0xfff,(r2,r1)
ord $0xffff,(r2,r1)
ord $0xfffff,(r2,r1)
ord $0xfffffff,(r2,r1)
ord $0xffffffff,(r2,r1)
###########
# ORD regp, regp
###########
ord (r4,r3),(r2,r1)
ord (r4,r3),(r2,r1)
#ord $10,(sp)
#ord $14,(sp)
#ord $8,(sp)

24
gas/testsuite/gas/cr16/pop_test.d Normal file
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#as:
#objdump: -dr
#name: pop_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 87 02 pop \$0x1,r7,RA
2: 96 02 pop \$0x2,r6,RA
4: a5 02 pop \$0x3,r5,RA
6: b4 02 pop \$0x4,r4,RA
8: c3 02 pop \$0x5,r3,RA
a: d2 02 pop \$0x6,r2,RA
c: e1 02 pop \$0x7,r1,RA
e: 07 02 pop \$0x1,r7
10: 16 02 pop \$0x2,r6
12: 25 02 pop \$0x3,r5
14: 34 02 pop \$0x4,r4
16: 43 02 pop \$0x5,r3
18: 52 02 pop \$0x6,r2
1a: 61 02 pop \$0x7,r1
1c: 1e 02 pop RA

27
gas/testsuite/gas/cr16/pop_test.s Normal file
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.text
.global main
main:
####################
# pop uimm3 regr RA
####################
pop $1,r7,RA
pop $2,r6,RA
pop $3,r5,RA
pop $4,r4,RA
pop $5,r3,RA
pop $6,r2,RA
pop $7,r1,RA
#################
# pop uimm3 regr
#################
pop $1,r7
pop $2,r6
pop $3,r5
pop $4,r4
pop $5,r3
pop $6,r2
pop $7,r1
##########
# pop RA
##########
pop RA

24
gas/testsuite/gas/cr16/popret_test.d Normal file
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#as:
#objdump: -dr
#name: popret_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 87 03 popret \$0x1,r7,RA
2: 96 03 popret \$0x2,r6,RA
4: a5 03 popret \$0x3,r5,RA
6: b4 03 popret \$0x4,r4,RA
8: c3 03 popret \$0x5,r3,RA
a: d2 03 popret \$0x6,r2,RA
c: e1 03 popret \$0x7,r1,RA
e: 07 03 popret \$0x1,r7
10: 16 03 popret \$0x2,r6
12: 25 03 popret \$0x3,r5
14: 34 03 popret \$0x4,r4
16: 43 03 popret \$0x5,r3
18: 52 03 popret \$0x6,r2
1a: 61 03 popret \$0x7,r1
1c: 1e 03 popret RA

27
gas/testsuite/gas/cr16/popret_test.s Normal file
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.text
.global main
main:
####################
# popret uimm3 regr RA
####################
popret $1,r7,RA
popret $2,r6,RA
popret $3,r5,RA
popret $4,r4,RA
popret $5,r3,RA
popret $6,r2,RA
popret $7,r1,RA
#################
# popret uimm3 regr
#################
popret $1,r7
popret $2,r6
popret $3,r5
popret $4,r4
popret $5,r3
popret $6,r2
popret $7,r1
##########
# popret RA
##########
popret RA

26
gas/testsuite/gas/cr16/push_test.d Normal file
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#as:
#objdump: -dr
#name: push_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 87 01 push \$0x1,r7,RA
2: 96 01 push \$0x2,r6,RA
4: a5 01 push \$0x3,r5,RA
6: b4 01 push \$0x4,r4,RA
8: c3 01 push \$0x5,r3,RA
a: d2 01 push \$0x6,r2,RA
c: e1 01 push \$0x7,r1,RA
e: 07 01 push \$0x1,r7
10: 16 01 push \$0x2,r6
12: 25 01 push \$0x3,r5
14: 34 01 push \$0x4,r4
16: 43 01 push \$0x5,r3
18: 52 01 push \$0x6,r2
1a: 61 01 push \$0x7,r1
1c: 5c 01 push \$0x6,r12
1e: 1e 01 push RA
20: 1e 01 push RA

40
gas/testsuite/gas/cr16/push_test.s Normal file
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.text
.global main
main:
####################
# push uimm3 regr RA
####################
push $1,r7,RA
push $2,r6,RA
push $3,r5,RA
push $4,r4,RA
push $5,r3,RA
push $6,r2,RA
push $7,r1,RA
#push $6,r12,RA
#push $7,r13,RA
#push $7,r12,RA
#push $8,r12,RA
#################
# push uimm3 regr
#################
push $1,r7
push $2,r6
push $3,r5
push $4,r4
push $5,r3
push $6,r2
push $7,r1
push $6,r12
#push $7,r13
#push $7,r12
#push $8,r12
#push $6,r13
##########
# push RA
##########
#push r1
#push r4
#push r9
push ra
push RA

82
gas/testsuite/gas/cr16/sbitb_test.d Normal file
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#as:
#objdump: -dr
#name: sbitb_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: c0 73 cd 0b sbitb \$0x4,0xbcd <main\+0xbcd>:m
4: da 73 cd ab sbitb \$0x5,0xaabcd <main\+0xaabcd>:m
8: 10 00 3f ba sbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: 50 70 14 00 sbitb \$0x5,\[r12\]0x14:m
12: c0 70 fc ab sbitb \$0x4,\[r13\]0xabfc:m
16: 30 70 34 12 sbitb \$0x3,\[r12\]0x1234:m
1a: b0 70 34 12 sbitb \$0x3,\[r13\]0x1234:m
1e: 30 70 34 00 sbitb \$0x3,\[r12\]0x34:m
22: b0 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\)
26: b1 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\)
2a: b6 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\)
2e: b2 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\)
32: b7 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\)
36: b3 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\)
3a: b4 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\)
3e: b5 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\)
42: b8 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\)
46: b9 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\)
4a: be 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\)
4e: ba 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\)
52: bf 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\)
56: bb 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\)
5a: bc 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\)
5e: bd 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\)
62: be 72 5a 4b sbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\)
66: b7 72 1a 41 sbitb \$0x1,\[r12\]0x17a:m\(r6,r5\)
6a: bf 72 14 01 sbitb \$0x1,\[r13\]0x134:m\(r6,r5\)
6e: 10 00 36 aa sbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\)
72: de bc
74: 10 00 5e a0 sbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\)
78: cd ab
7a: 10 00 37 a0 sbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\)
7e: cd ab
80: 10 00 3f a0 sbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\)
84: de bc
86: 10 00 52 80 sbitb \$0x5,0x0:l\(r2\)
8a: 00 00
8c: 3c 73 34 00 sbitb \$0x3,0x34:m\(r12\)
90: 3d 73 ab 00 sbitb \$0x3,0xab:m\(r13\)
94: 10 00 51 80 sbitb \$0x5,0xad:l\(r1\)
98: ad 00
9a: 10 00 52 80 sbitb \$0x5,0xcd:l\(r2\)
9e: cd 00
a0: 10 00 50 80 sbitb \$0x5,0xfff:l\(r0\)
a4: ff 0f
a6: 10 00 34 80 sbitb \$0x3,0xbcd:l\(r4\)
aa: cd 0b
ac: 3c 73 ff 0f sbitb \$0x3,0xfff:m\(r12\)
b0: 3d 73 ff 0f sbitb \$0x3,0xfff:m\(r13\)
b4: 3d 73 ff ff sbitb \$0x3,0xffff:m\(r13\)
b8: 3c 73 43 23 sbitb \$0x3,0x2343:m\(r12\)
bc: 10 00 32 81 sbitb \$0x3,0x2345:l\(r2\)
c0: 45 23
c2: 10 00 38 84 sbitb \$0x3,0xabcd:l\(r8\)
c6: cd ab
c8: 10 00 3d 9f sbitb \$0x3,0xfabcd:l\(r13\)
cc: cd ab
ce: 10 00 38 8f sbitb \$0x3,0xabcd:l\(r8\)
d2: cd ab
d4: 10 00 39 8f sbitb \$0x3,0xabcd:l\(r9\)
d8: cd ab
da: 10 00 39 84 sbitb \$0x3,0xabcd:l\(r9\)
de: cd ab
e0: 31 72 sbitb \$0x3,0x0:s\(r2,r1\)
e2: 51 73 01 00 sbitb \$0x5,0x1:m\(r2,r1\)
e6: 41 73 34 12 sbitb \$0x4,0x1234:m\(r2,r1\)
ea: 31 73 34 12 sbitb \$0x3,0x1234:m\(r2,r1\)
ee: 10 00 31 91 sbitb \$0x3,0x12345:l\(r2,r1\)
f2: 45 23
f4: 31 73 23 01 sbitb \$0x3,0x123:m\(r2,r1\)
f8: 10 00 31 91 sbitb \$0x3,0x12345:l\(r2,r1\)
fc: 45 23

62
gas/testsuite/gas/cr16/sbitb_test.s Normal file
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.text
.global main
main:
sbitb $4,0xbcd
sbitb $5,0xaabcd
sbitb $3,0xfaabcd
sbitb $5,[r12]0x14
sbitb $4,[r13]0xabfc
sbitb $3,[r12]0x1234
sbitb $3,[r13]0x1234
sbitb $3,[r12]0x34
sbitb $3,[r12]0xa7a(r1,r0)
sbitb $3,[r12]0xa7a(r3,r2)
sbitb $3,[r12]0xa7a(r4,r3)
sbitb $3,[r12]0xa7a(r5,r4)
sbitb $3,[r12]0xa7a(r6,r5)
sbitb $3,[r12]0xa7a(r7,r6)
sbitb $3,[r12]0xa7a(r9,r8)
sbitb $3,[r12]0xa7a(r11,r10)
sbitb $3,[r13]0xa7a(r1,r0)
sbitb $3,[r13]0xa7a(r3,r2)
sbitb $3,[r13]0xa7a(r4,r3)
sbitb $3,[r13]0xa7a(r5,r4)
sbitb $3,[r13]0xa7a(r6,r5)
sbitb $3,[r13]0xa7a(r7,r6)
sbitb $3,[r13]0xa7a(r9,r8)
sbitb $3,[r13]0xa7a(r11,r10)
sbitb $5,[r13]0xb7a(r4,r3)
sbitb $1,[r12]0x17a(r6,r5)
sbitb $1,[r13]0x134(r6,r5)
sbitb $3,[r12]0xabcde(r4,r3)
sbitb $5,[r13]0xabcd(r4,r3)
sbitb $3,[r12]0xabcd(r6,r5)
sbitb $3,[r13]0xbcde(r6,r5)
sbitb $5,0x0(r2)
sbitb $3,0x34(r12)
sbitb $3,0xab(r13)
sbitb $5,0xad(r1)
sbitb $5,0xcd(r2)
sbitb $5,0xfff(r0)
sbitb $3,0xbcd(r4)
sbitb $3,0xfff(r12)
sbitb $3,0xfff(r13)
sbitb $3,0xffff(r13)
sbitb $3,0x2343(r12)
sbitb $3,0x12345(r2)
sbitb $3,0x4abcd(r8)
sbitb $3,0xfabcd(r13)
sbitb $3,0xfabcd(r8)
sbitb $3,0xfabcd(r9)
sbitb $3,0x4abcd(r9)
sbitb $3,0x0(r2,r1)
sbitb $5,0x1(r2,r1)
sbitb $4,0x1234(r2,r1)
sbitb $3,0x1234(r2,r1)
sbitb $3,0x12345(r2,r1)
sbitb $3,0x123(r2,r1)
sbitb $3,0x12345(r2,r1)

155
gas/testsuite/gas/cr16/sbitw_test.d Normal file
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#as:
#objdump: -dr
#name: sbitw_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 40 77 cd 0b sbitw \$0x4:s,0xbcd <main\+0xbcd>:m
4: 5a 77 cd ab sbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m
8: 11 00 3f ba sbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: a0 77 cd 0b sbitw \$0xa:s,0xbcd <main\+0xbcd>:m
12: fa 77 cd ab sbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m
16: 11 00 ef ba sbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l
1a: cd ab
1c: 50 74 14 00 sbitw \$0x5:s,\[r13\]0x14:m
20: 40 75 fc ab sbitw \$0x4:s,\[r13\]0xabfc:m
24: 30 74 34 12 sbitw \$0x3:s,\[r12\]0x1234:m
28: 30 75 34 12 sbitw \$0x3:s,\[r12\]0x1234:m
2c: 30 74 34 00 sbitw \$0x3:s,\[r12\]0x34:m
30: f0 74 14 00 sbitw \$0xf:s,\[r13\]0x14:m
34: e0 75 fc ab sbitw \$0xe:s,\[r13\]0xabfc:m
38: d0 74 34 12 sbitw \$0xd:s,\[r13\]0x1234:m
3c: d0 75 34 12 sbitw \$0xd:s,\[r13\]0x1234:m
40: b0 74 34 00 sbitw \$0xb:s,\[r12\]0x34:m
44: f0 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
48: f1 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
4c: f6 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
50: f2 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
54: f7 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
58: f3 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
5c: f4 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
60: f5 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
64: f8 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
68: f9 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
6c: fe 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
70: fa 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
74: ff 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
78: fb 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
7c: fc 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
80: fd 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
84: fe 72 5a 4b sbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
88: f7 72 1a 41 sbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\)
8c: ff 72 14 01 sbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\)
90: 11 00 36 aa sbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
94: de bc
96: 11 00 5e a0 sbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
9a: cd ab
9c: 11 00 37 a0 sbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
a0: cd ab
a2: 11 00 3f a0 sbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
a6: de bc
a8: f0 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\)
ac: f1 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\)
b0: f6 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\)
b4: f2 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\)
b8: f7 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\)
bc: f3 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\)
c0: f4 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\)
c4: f5 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\)
c8: f8 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\)
cc: f9 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\)
d0: fe 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\)
d4: fa 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\)
d8: ff 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\)
dc: fb 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\)
e0: fc 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\)
e4: fd 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\)
e8: fe 72 fa 4b sbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
ec: f7 72 ba 41 sbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
f0: ff 72 b4 01 sbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
f4: 11 00 d6 aa sbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
f8: de bc
fa: 11 00 fe a0 sbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
fe: cd ab
100: 11 00 d7 a0 sbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
104: cd ab
106: 11 00 df a0 sbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
10a: de bc
10c: 11 00 52 80 sbitw \$0x5:s,0x0:l\(r2\)
110: 00 00
112: 3c 71 34 00 sbitw \$0x3:s,0x34:m\(r12\)
116: 3d 71 ab 00 sbitw \$0x3:s,0xab:m\(r13\)
11a: 11 00 51 80 sbitw \$0x5:s,0xad:l\(r1\)
11e: ad 00
120: 11 00 52 80 sbitw \$0x5:s,0xcd:l\(r2\)
124: cd 00
126: 11 00 50 80 sbitw \$0x5:s,0xfff:l\(r0\)
12a: ff 0f
12c: 11 00 34 80 sbitw \$0x3:s,0xbcd:l\(r4\)
130: cd 0b
132: 3c 71 ff 0f sbitw \$0x3:s,0xfff:m\(r12\)
136: 3d 71 ff 0f sbitw \$0x3:s,0xfff:m\(r13\)
13a: 3d 71 ff ff sbitw \$0x3:s,0xffff:m\(r13\)
13e: 3c 71 43 23 sbitw \$0x3:s,0x2343:m\(r12\)
142: 11 00 32 81 sbitw \$0x3:s,0x2345:l\(r2\)
146: 45 23
148: 11 00 38 84 sbitw \$0x3:s,0xabcd:l\(r8\)
14c: cd ab
14e: 11 00 3d 9f sbitw \$0x3:s,0xfabcd:l\(r13\)
152: cd ab
154: 11 00 38 8f sbitw \$0x3:s,0xabcd:l\(r8\)
158: cd ab
15a: 11 00 39 8f sbitw \$0x3:s,0xabcd:l\(r9\)
15e: cd ab
160: 11 00 39 84 sbitw \$0x3:s,0xabcd:l\(r9\)
164: cd ab
166: 11 00 f2 80 sbitw \$0xf:s,0x0:l\(r2\)
16a: 00 00
16c: dc 71 34 00 sbitw \$0xd:s,0x34:m\(r12\)
170: dd 71 ab 00 sbitw \$0xd:s,0xab:m\(r13\)
174: 11 00 f1 80 sbitw \$0xf:s,0xad:l\(r1\)
178: ad 00
17a: 11 00 f2 80 sbitw \$0xf:s,0xcd:l\(r2\)
17e: cd 00
180: 11 00 f0 80 sbitw \$0xf:s,0xfff:l\(r0\)
184: ff 0f
186: 11 00 d4 80 sbitw \$0xd:s,0xbcd:l\(r4\)
18a: cd 0b
18c: dc 71 ff 0f sbitw \$0xd:s,0xfff:m\(r12\)
190: dd 71 ff 0f sbitw \$0xd:s,0xfff:m\(r13\)
194: dd 71 ff ff sbitw \$0xd:s,0xffff:m\(r13\)
198: dc 71 43 23 sbitw \$0xd:s,0x2343:m\(r12\)
19c: 11 00 d2 81 sbitw \$0xd:s,0x2345:l\(r2\)
1a0: 45 23
1a2: 11 00 d8 84 sbitw \$0xd:s,0xabcd:l\(r8\)
1a6: cd ab
1a8: 11 00 dd 9f sbitw \$0xd:s,0xfabcd:l\(r13\)
1ac: cd ab
1ae: 11 00 d8 8f sbitw \$0xd:s,0xabcd:l\(r8\)
1b2: cd ab
1b4: 11 00 d9 8f sbitw \$0xd:s,0xabcd:l\(r9\)
1b8: cd ab
1ba: 11 00 d9 84 sbitw \$0xd:s,0xabcd:l\(r9\)
1be: cd ab
1c0: 31 76 sbitw \$0x3:s,0x0:s\(r2,r1\)
1c2: 51 71 01 00 sbitw \$0x5:s,0x1:m\(r2,r1\)
1c6: 41 71 34 12 sbitw \$0x4:s,0x1234:m\(r2,r1\)
1ca: 31 71 34 12 sbitw \$0x3:s,0x1234:m\(r2,r1\)
1ce: 11 00 31 91 sbitw \$0x3:s,0x12345:l\(r2,r1\)
1d2: 45 23
1d4: 31 71 23 01 sbitw \$0x3:s,0x123:m\(r2,r1\)
1d8: 11 00 31 91 sbitw \$0x3:s,0x12345:l\(r2,r1\)
1dc: 45 23
1de: d1 76 sbitw \$0xd:s,0x0:s\(r2,r1\)
1e0: f1 71 01 00 sbitw \$0xf:s,0x1:m\(r2,r1\)
1e4: e1 71 34 12 sbitw \$0xe:s,0x1234:m\(r2,r1\)
1e8: d1 71 34 12 sbitw \$0xd:s,0x1234:m\(r2,r1\)
1ec: 11 00 d1 91 sbitw \$0xd:s,0x12345:l\(r2,r1\)
1f0: 45 23
1f2: d1 71 23 01 sbitw \$0xd:s,0x123:m\(r2,r1\)
1f6: 11 00 d1 91 sbitw \$0xd:s,0x12345:l\(r2,r1\)
1fa: 45 23

117
gas/testsuite/gas/cr16/sbitw_test.s Normal file
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.text
.global main
main:
sbitw $4,0xbcd
sbitw $5,0xaabcd
sbitw $3,0xfaabcd
sbitw $10,0xbcd
sbitw $15,0xaabcd
sbitw $14,0xfaabcd
sbitw $5,[r12]0x14
sbitw $4,[r13]0xabfc
sbitw $3,[r12]0x1234
sbitw $3,[r13]0x1234
sbitw $3,[r12]0x34
sbitw $15,[r12]0x14
sbitw $14,[r13]0xabfc
sbitw $13,[r12]0x1234
sbitw $13,[r13]0x1234
sbitw $11,[r12]0x34
sbitw $3,[r12]0xa7a(r1,r0)
sbitw $3,[r12]0xa7a(r3,r2)
sbitw $3,[r12]0xa7a(r4,r3)
sbitw $3,[r12]0xa7a(r5,r4)
sbitw $3,[r12]0xa7a(r6,r5)
sbitw $3,[r12]0xa7a(r7,r6)
sbitw $3,[r12]0xa7a(r9,r8)
sbitw $3,[r12]0xa7a(r11,r10)
sbitw $3,[r13]0xa7a(r1,r0)
sbitw $3,[r13]0xa7a(r3,r2)
sbitw $3,[r13]0xa7a(r4,r3)
sbitw $3,[r13]0xa7a(r5,r4)
sbitw $3,[r13]0xa7a(r6,r5)
sbitw $3,[r13]0xa7a(r7,r6)
sbitw $3,[r13]0xa7a(r9,r8)
sbitw $3,[r13]0xa7a(r11,r10)
sbitw $5,[r13]0xb7a(r4,r3)
sbitw $1,[r12]0x17a(r6,r5)
sbitw $1,[r13]0x134(r6,r5)
sbitw $3,[r12]0xabcde(r4,r3)
sbitw $5,[r13]0xabcd(r4,r3)
sbitw $3,[r12]0xabcd(r6,r5)
sbitw $3,[r13]0xbcde(r6,r5)
sbitw $13,[r12]0xa7a(r1,r0)
sbitw $13,[r12]0xa7a(r3,r2)
sbitw $13,[r12]0xa7a(r4,r3)
sbitw $13,[r12]0xa7a(r5,r4)
sbitw $13,[r12]0xa7a(r6,r5)
sbitw $13,[r12]0xa7a(r7,r6)
sbitw $13,[r12]0xa7a(r9,r8)
sbitw $13,[r12]0xa7a(r11,r10)
sbitw $13,[r13]0xa7a(r1,r0)
sbitw $13,[r13]0xa7a(r3,r2)
sbitw $13,[r13]0xa7a(r4,r3)
sbitw $13,[r13]0xa7a(r5,r4)
sbitw $13,[r13]0xa7a(r6,r5)
sbitw $13,[r13]0xa7a(r7,r6)
sbitw $13,[r13]0xa7a(r9,r8)
sbitw $13,[r13]0xa7a(r11,r10)
sbitw $15,[r13]0xb7a(r4,r3)
sbitw $11,[r12]0x17a(r6,r5)
sbitw $11,[r13]0x134(r6,r5)
sbitw $13,[r12]0xabcde(r4,r3)
sbitw $15,[r13]0xabcd(r4,r3)
sbitw $13,[r12]0xabcd(r6,r5)
sbitw $13,[r13]0xbcde(r6,r5)
sbitw $5,0x0(r2)
sbitw $3,0x34(r12)
sbitw $3,0xab(r13)
sbitw $5,0xad(r1)
sbitw $5,0xcd(r2)
sbitw $5,0xfff(r0)
sbitw $3,0xbcd(r4)
sbitw $3,0xfff(r12)
sbitw $3,0xfff(r13)
sbitw $3,0xffff(r13)
sbitw $3,0x2343(r12)
sbitw $3,0x12345(r2)
sbitw $3,0x4abcd(r8)
sbitw $3,0xfabcd(r13)
sbitw $3,0xfabcd(r8)
sbitw $3,0xfabcd(r9)
sbitw $3,0x4abcd(r9)
sbitw $15,0x0(r2)
sbitw $13,0x34(r12)
sbitw $13,0xab(r13)
sbitw $15,0xad(r1)
sbitw $15,0xcd(r2)
sbitw $15,0xfff(r0)
sbitw $13,0xbcd(r4)
sbitw $13,0xfff(r12)
sbitw $13,0xfff(r13)
sbitw $13,0xffff(r13)
sbitw $13,0x2343(r12)
sbitw $13,0x12345(r2)
sbitw $13,0x4abcd(r8)
sbitw $13,0xfabcd(r13)
sbitw $13,0xfabcd(r8)
sbitw $13,0xfabcd(r9)
sbitw $13,0x4abcd(r9)
sbitw $3,0x0(r2,r1)
sbitw $5,0x1(r2,r1)
sbitw $4,0x1234(r2,r1)
sbitw $3,0x1234(r2,r1)
sbitw $3,0x12345(r2,r1)
sbitw $3,0x123(r2,r1)
sbitw $3,0x12345(r2,r1)
sbitw $13,0x0(r2,r1)
sbitw $15,0x1(r2,r1)
sbitw $14,0x1234(r2,r1)
sbitw $13,0x1234(r2,r1)
sbitw $13,0x12345(r2,r1)
sbitw $13,0x123(r2,r1)
sbitw $13,0x12345(r2,r1)

22
gas/testsuite/gas/cr16/scc_test.d Normal file
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#as:
#objdump: -dr
#name: scc_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 02 08 seq r2
2: 13 08 sne r3
4: 23 08 scs r3
6: 34 08 scc r4
8: 45 08 shi r5
a: 56 08 sls r6
c: 67 08 sgt r7
e: 88 08 sfs r8
10: 99 08 sfc r9
12: aa 08 slo r10
14: b1 08 shs r1
16: cb 08 slt r11
18: d0 08 sge r0

19
gas/testsuite/gas/cr16/scc_test.s Normal file
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.text
.global main
main:
##########
# SCond reg
##########
seq r2
sne r3
scs r3
scc r4
shi r5
sls r6
sgt r7
sfs r8
sfc r9
slo r10
shs r1
slt r11
sge r0

153
gas/testsuite/gas/cr16/storb_test.d Normal file
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#as:
#objdump: -dr
#name: storb_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 c8 00 00 storb r0,0x0 <main>:m
4: 10 c8 ff 00 storb r1,0xff <main\+0xff>:m
8: 30 c8 ff 0f storb r3,0xfff <main\+0xfff>:m
c: 40 c8 34 12 storb r4,0x1234 <main\+0x1234>:m
10: 50 c8 34 12 storb r5,0x1234 <main\+0x1234>:m
14: 13 00 07 7a storb r0,0x7a1234 <main\+0x7a1234>:l
18: 34 12
1a: 13 00 1b 7a storb r1,0xba1234 <main\+0xba1234>:l
1e: 34 12
20: 13 00 2f 7f storb r2,0xffffff <main\+0xffffff>:l
24: ff ff
26: 00 ca 00 00 storb r0,\[r12\]0x0:m
2a: 00 cb 00 00 storb r0,\[r12\]0x0:m
2e: 10 ca ff 00 storb r1,\[r12\]0xff:m
32: 10 cb ff 00 storb r1,\[r12\]0xff:m
36: 30 ca ff 0f storb r3,\[r12\]0xfff:m
3a: 30 cb ff 0f storb r3,\[r12\]0xfff:m
3e: 40 ca 34 12 storb r4,\[r13\]0x1234:m
42: 40 cb 34 12 storb r4,\[r13\]0x1234:m
46: 50 ca 34 12 storb r5,\[r13\]0x1234:m
4a: 50 cb 34 12 storb r5,\[r13\]0x1234:m
4e: 20 ca 67 45 storb r2,\[r12\]0x4567:m
52: 2a cb 34 12 storb r2,\[r12\]0xa1234:m
56: 10 f4 storb r1,0x4:s\(r1,r0\)
58: 32 f4 storb r3,0x4:s\(r3,r2\)
5a: 40 ff 34 12 storb r4,0x1234:m\(r1,r0\)
5e: 52 ff 34 12 storb r5,0x1234:m\(r3,r2\)
62: 13 00 60 5a storb r6,0xa1234:l\(r1,r0\)
66: 34 12
68: 19 00 10 5f storb r1,0xffffc:l\(r1,r0\)
6c: fc ff
6e: 19 00 32 5f storb r3,0xffffc:l\(r3,r2\)
72: fc ff
74: 19 00 40 5f storb r4,0xfedcc:l\(r1,r0\)
78: cc ed
7a: 19 00 52 5f storb r5,0xfedcc:l\(r3,r2\)
7e: cc ed
80: 19 00 60 55 storb r6,0x5edcc:l\(r1,r0\)
84: cc ed
86: 00 f0 storb r0,0x0:s\(r1,r0\)
88: 00 f0 storb r0,0x0:s\(r1,r0\)
8a: 00 ff 0f 00 storb r0,0xf:m\(r1,r0\)
8e: 10 ff 0f 00 storb r1,0xf:m\(r1,r0\)
92: 20 ff 34 12 storb r2,0x1234:m\(r1,r0\)
96: 32 ff cd ab storb r3,0xabcd:m\(r3,r2\)
9a: 43 ff ff af storb r4,0xafff:m\(r4,r3\)
9e: 13 00 55 5a storb r5,0xa1234:l\(r6,r5\)
a2: 34 12
a4: 19 00 00 5f storb r0,0xffff1:l\(r1,r0\)
a8: f1 ff
aa: 19 00 10 5f storb r1,0xffff1:l\(r1,r0\)
ae: f1 ff
b0: 19 00 20 5f storb r2,0xfedcc:l\(r1,r0\)
b4: cc ed
b6: 19 00 32 5f storb r3,0xf5433:l\(r3,r2\)
ba: 33 54
bc: 19 00 43 5f storb r4,0xf5001:l\(r4,r3\)
c0: 01 50
c2: 19 00 55 55 storb r5,0x5edcc:l\(r6,r5\)
c6: cc ed
c8: 00 fe storb r0,\[r12\]0x0:s\(r1,r0\)
ca: 18 fe storb r1,\[r13\]0x0:s\(r1,r0\)
cc: 70 c6 04 12 storb r7,\[r12\]0x234:m\(r1,r0\)
d0: 13 00 38 61 storb r3,\[r13\]0x1abcd:l\(r1,r0\)
d4: cd ab
d6: 13 00 40 6a storb r4,\[r12\]0xa1234:l\(r1,r0\)
da: 34 12
dc: 13 00 58 6b storb r5,\[r13\]0xb1234:l\(r1,r0\)
e0: 34 12
e2: 13 00 68 6f storb r6,\[r13\]0xfffff:l\(r1,r0\)
e6: ff ff
e8: 40 81 cd 0b storb \$0x4:s,0xbcd <main\+0xbcd>:m
ec: 5a 81 cd ab storb \$0x5:s,0xaabcd <main\+0xaabcd>:m
f0: 12 00 3f 3a storb \$0x3:s,0xfaabcd <main\+0xfaabcd>:l
f4: cd ab
f6: 50 84 14 00 storb \$0x5:s,\[r13\]0x14:m
fa: 40 85 fc ab storb \$0x4:s,\[r13\]0xabfc:m
fe: 30 84 34 12 storb \$0x3:s,\[r12\]0x1234:m
102: 30 85 34 12 storb \$0x3:s,\[r12\]0x1234:m
106: 30 84 34 00 storb \$0x3:s,\[r12\]0x34:m
10a: 30 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
10e: 31 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
112: 36 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
116: 32 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
11a: 37 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
11e: 33 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
122: 34 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
126: 35 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
12a: 38 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
12e: 39 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
132: 3e 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
136: 3a 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
13a: 3f 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
13e: 3b 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
142: 3c 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
146: 3d 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
14a: 3e 86 5a 4b storb \$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
14e: 37 86 1a 41 storb \$0x1:s,\[r12\]0x17a:m\(r6,r5\)
152: 3f 86 14 01 storb \$0x1:s,\[r13\]0x134:m\(r6,r5\)
156: 12 00 36 2a storb \$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
15a: de bc
15c: 12 00 5e 20 storb \$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
160: cd ab
162: 12 00 37 20 storb \$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
166: cd ab
168: 12 00 3f 20 storb \$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
16c: de bc
16e: 12 00 52 00 storb \$0x5:s,0x0:l\(r2\)
172: 00 00
174: 3c 83 34 00 storb \$0x3:s,0x34:m\(r12\)
178: 3d 83 ab 00 storb \$0x3:s,0xab:m\(r13\)
17c: 12 00 51 00 storb \$0x5:s,0xad:l\(r1\)
180: ad 00
182: 12 00 52 00 storb \$0x5:s,0xcd:l\(r2\)
186: cd 00
188: 12 00 50 00 storb \$0x5:s,0xfff:l\(r0\)
18c: ff 0f
18e: 12 00 34 00 storb \$0x3:s,0xbcd:l\(r4\)
192: cd 0b
194: 3c 83 ff 0f storb \$0x3:s,0xfff:m\(r12\)
198: 3d 83 ff 0f storb \$0x3:s,0xfff:m\(r13\)
19c: 3d 83 ff ff storb \$0x3:s,0xffff:m\(r13\)
1a0: 3c 83 43 23 storb \$0x3:s,0x2343:m\(r12\)
1a4: 12 00 32 01 storb \$0x3:s,0x2345:l\(r2\)
1a8: 45 23
1aa: 12 00 38 04 storb \$0x3:s,0xabcd:l\(r8\)
1ae: cd ab
1b0: 12 00 3d 1f storb \$0x3:s,0xfabcd:l\(r13\)
1b4: cd ab
1b6: 12 00 38 0f storb \$0x3:s,0xabcd:l\(r8\)
1ba: cd ab
1bc: 12 00 39 0f storb \$0x3:s,0xabcd:l\(r9\)
1c0: cd ab
1c2: 12 00 39 04 storb \$0x3:s,0xabcd:l\(r9\)
1c6: cd ab
1c8: 31 82 storb \$0x3:s,0x0:s\(r2,r1\)
1ca: 51 83 01 00 storb \$0x5:s,0x1:m\(r2,r1\)
1ce: 41 83 34 12 storb \$0x4:s,0x1234:m\(r2,r1\)
1d2: 31 83 34 12 storb \$0x3:s,0x1234:m\(r2,r1\)
1d6: 12 00 31 11 storb \$0x3:s,0x12345:l\(r2,r1\)
1da: 45 23
1dc: 31 83 23 01 storb \$0x3:s,0x123:m\(r2,r1\)
1e0: 12 00 31 11 storb \$0x3:s,0x12345:l\(r2,r1\)
1e4: 45 23

143
gas/testsuite/gas/cr16/storb_test.s Normal file
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.text
.global main
main:
######################
# storb reg abs20/24
######################
storb r0,0x0
storb r1,0xff
storb r3,0xfff
storb r4,0x1234
storb r5,0x1234
storb r0,0x7A1234
storb r1,0xBA1234
storb r2,0xffffff
######################
# storb abs20 rel reg
######################
storb r0,[r12]0x0
storb r0,[r13]0x0
storb r1,[r12]0xff
storb r1,[r13]0xff
storb r3,[r12]0xfff
storb r3,[r13]0xfff
storb r4,[r12]0x1234
storb r4,[r13]0x1234
storb r5,[r12]0x1234
storb r5,[r13]0x1234
storb r2,[r12]0x4567
storb r2,[r13]0xA1234
###################################
# storb reg rbase(disp20/-disp20)
###################################
storb r1,0x4(r1,r0)
storb r3,0x4(r3,r2)
storb r4,0x1234(r1,r0)
storb r5,0x1234(r3,r2)
storb r6,0xA1234(r1,r0)
storb r1,-0x4(r1,r0)
storb r3,-0x4(r3,r2)
storb r4,-0x1234(r1,r0)
storb r5,-0x1234(r3,r2)
storb r6,-0xA1234(r1,r0)
#################################################
# storb reg rpbase(disp4/disp16/disp20/-disp20)
#################################################
storb r0,0x0(r1,r0)
storb r0,0x0(r1,r0)
storb r0,0xf(r1,r0)
storb r1,0xf(r1,r0)
storb r2,0x1234(r1,r0)
storb r3,0xabcd(r3,r2)
storb r4,0xAfff(r4,r3)
storb r5,0xA1234(r6,r5)
storb r0,-0xf(r1,r0)
storb r1,-0xf(r1,r0)
storb r2,-0x1234(r1,r0)
storb r3,-0xabcd(r3,r2)
storb r4,-0xAfff(r4,r3)
storb r5,-0xA1234(r6,r5)
####################################
# storb rbase(disp0/disp14) rel reg
####################################
storb r0,[r12]0x0(r1,r0)
storb r1,[r13]0x0(r1,r0)
storb r2,[r12]0x1234(r1,r0)
storb r3,[r13]0x1abcd(r1,r0)
#################################
# storb reg rpbase(disp20) rel
#################################
storb r4,[r12]0xA1234(r1,r0)
storb r5,[r13]0xB1234(r1,r0)
storb r6,[r13]0xfffff(r1,r0)
#######################
# storb reg, uimm16/20
######################
storb $4,0xbcd
storb $5,0xaabcd
storb $3,0xfaabcd
#######################
# storb reg, uimm16/20
######################
storb $5,[r12]0x14
storb $4,[r13]0xabfc
storb $3,[r12]0x1234
storb $3,[r13]0x1234
storb $3,[r12]0x34
#######################
# storb imm, index-rbase
######################
storb $3,[r12]0xa7a(r1,r0)
storb $3,[r12]0xa7a(r3,r2)
storb $3,[r12]0xa7a(r4,r3)
storb $3,[r12]0xa7a(r5,r4)
storb $3,[r12]0xa7a(r6,r5)
storb $3,[r12]0xa7a(r7,r6)
storb $3,[r12]0xa7a(r9,r8)
storb $3,[r12]0xa7a(r11,r10)
storb $3,[r13]0xa7a(r1,r0)
storb $3,[r13]0xa7a(r3,r2)
storb $3,[r13]0xa7a(r4,r3)
storb $3,[r13]0xa7a(r5,r4)
storb $3,[r13]0xa7a(r6,r5)
storb $3,[r13]0xa7a(r7,r6)
storb $3,[r13]0xa7a(r9,r8)
storb $3,[r13]0xa7a(r11,r10)
storb $5,[r13]0xb7a(r4,r3)
storb $1,[r12]0x17a(r6,r5)
storb $1,[r13]0x134(r6,r5)
storb $3,[r12]0xabcde(r4,r3)
storb $5,[r13]0xabcd(r4,r3)
storb $3,[r12]0xabcd(r6,r5)
storb $3,[r13]0xbcde(r6,r5)
#######################
# storb imm4, rbase(disp)
######################
storb $5,0x0(r2)
storb $3,0x34(r12)
storb $3,0xab(r13)
storb $5,0xad(r1)
storb $5,0xcd(r2)
storb $5,0xfff(r0)
storb $3,0xbcd(r4)
storb $3,0xfff(r12)
storb $3,0xfff(r13)
storb $3,0xffff(r13)
storb $3,0x2343(r12)
storb $3,0x12345(r2)
storb $3,0x4abcd(r8)
storb $3,0xfabcd(r13)
storb $3,0xfabcd(r8)
storb $3,0xfabcd(r9)
storb $3,0x4abcd(r9)
##########################
# storb imm, disp20(rpbase)
#########################
storb $3,0x0(r2,r1)
storb $5,0x1(r2,r1)
storb $4,0x1234(r2,r1)
storb $3,0x1234(r2,r1)
storb $3,0x12345(r2,r1)
storb $3,0x123(r2,r1)
storb $3,0x12345(r2,r1)

80
gas/testsuite/gas/cr16/stord_test.d Normal file
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#as:
#objdump: -dr
#name: stord_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 c7 00 00 stord \(r1,r0\),0x0 <main>:m
4: 00 c7 ff 00 stord \(r1,r0\),0xff <main\+0xff>:m
8: 20 c7 ff 0f stord \(r3,r2\),0xfff <main\+0xfff>:m
c: 30 c7 34 12 stord \(r4,r3\),0x1234 <main\+0x1234>:m
10: 40 c7 34 12 stord \(r5,r4\),0x1234 <main\+0x1234>:m
14: 13 00 07 ba stord \(r1,r0\),0x7a1234 <main\+0x7a1234>:l
18: 34 12
1a: 13 00 0b ba stord \(r1,r0\),0xba1234 <main\+0xba1234>:l
1e: 34 12
20: 13 00 1f bf stord \(r2,r1\),0xffffff <main\+0xffffff>:l
24: ff ff
26: 00 cc 00 00 stord \(r1,r0\),\[r12\]0x0:m
2a: 00 cd 00 00 stord \(r1,r0\),\[r12\]0x0:m
2e: 00 cc ff 00 stord \(r1,r0\),\[r12\]0xff:m
32: 00 cd ff 00 stord \(r1,r0\),\[r12\]0xff:m
36: 20 cc ff 0f stord \(r3,r2\),\[r12\]0xfff:m
3a: 20 cd ff 0f stord \(r3,r2\),\[r12\]0xfff:m
3e: 30 cc 34 12 stord \(r4,r3\),\[r12\]0x1234:m
42: 30 cd 34 12 stord \(r4,r3\),\[r12\]0x1234:m
46: 40 cc 34 12 stord \(r5,r4\),\[r13\]0x1234:m
4a: 40 cd 34 12 stord \(r5,r4\),\[r13\]0x1234:m
4e: 10 cc 67 45 stord \(r2,r1\),\[r12\]0x4567:m
52: 1a cd 34 12 stord \(r2,r1\),\[r12\]0xa1234:m
56: 10 e2 stord \(r2,r1\),0x4:s\(r1,r0\)
58: 22 e2 stord \(r3,r2\),0x4:s\(r3,r2\)
5a: 30 ef 34 12 stord \(r4,r3\),0x1234:m\(r1,r0\)
5e: 42 ef 34 12 stord \(r5,r4\),0x1234:m\(r3,r2\)
62: 13 00 50 9a stord \(r6,r5\),0xa1234:l\(r1,r0\)
66: 34 12
68: 19 00 10 9f stord \(r2,r1\),0xffffc:l\(r1,r0\)
6c: fc ff
6e: 19 00 22 9f stord \(r3,r2\),0xffffc:l\(r3,r2\)
72: fc ff
74: 19 00 30 9f stord \(r4,r3\),0xfedcc:l\(r1,r0\)
78: cc ed
7a: 19 00 42 9f stord \(r5,r4\),0xfedcc:l\(r3,r2\)
7e: cc ed
80: 19 00 50 95 stord \(r6,r5\),0x5edcc:l\(r1,r0\)
84: cc ed
86: 00 e0 stord \(r1,r0\),0x0:s\(r1,r0\)
88: 00 e0 stord \(r1,r0\),0x0:s\(r1,r0\)
8a: 00 ef 0f 00 stord \(r1,r0\),0xf:m\(r1,r0\)
8e: 00 ef 0f 00 stord \(r1,r0\),0xf:m\(r1,r0\)
92: 10 ef 34 12 stord \(r2,r1\),0x1234:m\(r1,r0\)
96: 22 ef cd ab stord \(r3,r2\),0xabcd:m\(r3,r2\)
9a: 33 ef ff af stord \(r4,r3\),0xafff:m\(r4,r3\)
9e: 13 00 65 9a stord \(r7,r6\),0xa1234:l\(r6,r5\)
a2: 34 12
a4: 19 00 00 9f stord \(r1,r0\),0xffff1:l\(r1,r0\)
a8: f1 ff
aa: 19 00 00 9f stord \(r1,r0\),0xffff1:l\(r1,r0\)
ae: f1 ff
b0: 19 00 10 9f stord \(r2,r1\),0xfedcc:l\(r1,r0\)
b4: cc ed
b6: 19 00 22 9f stord \(r3,r2\),0xf5433:l\(r3,r2\)
ba: 33 54
bc: 19 00 43 9f stord \(r5,r4\),0xf5001:l\(r4,r3\)
c0: 01 50
c2: 19 00 45 95 stord \(r5,r4\),0x5edcc:l\(r6,r5\)
c6: cc ed
c8: 00 ee stord \(r1,r0\),\[r12\]0x0:s\(r1,r0\)
ca: 08 ee stord \(r1,r0\),\[r13\]0x0:s\(r1,r0\)
cc: b0 c6 04 12 stord \(r12,r11\),\[r12\]0x234:m\(r1,r0\)
d0: 13 00 28 a1 stord \(r3,r2\),\[r13\]0x1abcd:l\(r1,r0\)
d4: cd ab
d6: 13 00 20 aa stord \(r3,r2\),\[r12\]0xa1234:l\(r1,r0\)
da: 34 12
dc: 13 00 38 ab stord \(r4,r3\),\[r13\]0xb1234:l\(r1,r0\)
e0: 34 12
e2: 13 00 48 af stord \(r5,r4\),\[r13\]0xfffff:l\(r1,r0\)
e6: ff ff

72
gas/testsuite/gas/cr16/stord_test.s Normal file
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.text
.global main
main:
######################
# stord abs20/24 regp
######################
stord (r1,r0),0x0
stord (r1,r0),0xff
stord (r3,r2),0xfff
stord (r4,r3),0x1234
stord (r5,r4),0x1234
stord (r1,r0),0x7A1234
stord (r1,r0),0xBA1234
stord (r2,r1),0xffffff
######################
# stord abs20 rel regp
######################
stord (r1,r0),[r12]0x0
stord (r1,r0),[r13]0x0
stord (r1,r0),[r12]0xff
stord (r1,r0),[r13]0xff
stord (r3,r2),[r12]0xfff
stord (r3,r2),[r13]0xfff
stord (r4,r3),[r12]0x1234
stord (r4,r3),[r13]0x1234
stord (r5,r4),[r12]0x1234
stord (r5,r4),[r13]0x1234
stord (r2,r1),[r12]0x4567
stord (r2,r1),[r13]0xA1234
###################################
# stord regp rbase(disp20/-disp20)
###################################
stord (r2,r1),0x4(r1,r0)
stord (r3,r2),0x4(r3,r2)
stord (r4,r3),0x1234(r1,r0)
stord (r5,r4),0x1234(r3,r2)
stord (r6,r5),0xA1234(r1,r0)
stord (r2,r1),-0x4(r1,r0)
stord (r3,r2),-0x4(r3,r2)
stord (r4,r3),-0x1234(r1,r0)
stord (r5,r4),-0x1234(r3,r2)
stord (r6,r5),-0xA1234(r1,r0)
#################################################
# stord regp rpbase(disp4/disp16/disp20/-disp20)
#################################################
stord (r1,r0),0x0(r1,r0)
stord (r1,r0),0x0(r1,r0)
stord (r1,r0),0xf(r1,r0)
stord (r1,r0),0xf(r1,r0)
stord (r2,r1),0x1234(r1,r0)
stord (r3,r2),0xabcd(r3,r2)
stord (r4,r3),0xAfff(r4,r3)
stord (r7,r6),0xA1234(r6,r5)
stord (r1,r0),-0xf(r1,r0)
stord (r1,r0),-0xf(r1,r0)
stord (r2,r1),-0x1234(r1,r0)
stord (r3,r2),-0xabcd(r3,r2)
stord (r5,r4),-0xAfff(r4,r3)
stord (r5,r4),-0xA1234(r6,r5)
####################################
# stord rbase(disp0/disp14) rel reg
####################################
stord (r1,r0),[r12]0x0(r1,r0)
stord (r1,r0),[r13]0x0(r1,r0)
stord (r2,r1),[r12]0x1234(r1,r0)
stord (r3,r2),[r13]0x1abcd(r1,r0)
#################################
# stord rpbase(disp20) rel reg
#################################
stord (r3,r2),[r12]0xA1234(r1,r0)
stord (r4,r3),[r13]0xB1234(r1,r0)
stord (r5,r4),[r13]0xfffff(r1,r0)

25
gas/testsuite/gas/cr16/storm_test.d Normal file
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#as:
#objdump: -dr
#name: storm_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: b0 00 storm \$0x1,r0
2: b1 00 storm \$0x2,r0
4: b2 00 storm \$0x3,r0
6: b3 00 storm \$0x4,r0
8: b4 00 storm \$0x5,r0
a: b5 00 storm \$0x6,r0
c: b6 00 storm \$0x7,r0
e: b7 00 storm \$0x8,r0
10: b8 00 stormp \$0x1,r0
12: b9 00 stormp \$0x2,r0
14: ba 00 stormp \$0x3,r0
16: bb 00 stormp \$0x4,r0
18: bc 00 stormp \$0x5,r0
1a: bd 00 stormp \$0x6,r0
1c: be 00 stormp \$0x7,r0
1e: bf 00 stormp \$0x8,r0

25
gas/testsuite/gas/cr16/storm_test.s Normal file
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.text
.global main
main:
##############
# storm cnt
##############
storm $1
storm $2
storm $3
storm $4
storm $5
storm $6
storm $7
storm $8
##############
# stormp cnt
##############
stormp $1
stormp $2
stormp $3
stormp $4
stormp $5
stormp $6
stormp $7
stormp $8

153
gas/testsuite/gas/cr16/storw_test.d Normal file
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#as:
#objdump: -dr
#name: storw_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 c9 00 00 storw r0,0x0 <main>:m
4: 10 c9 ff 00 storw r1,0xff <main\+0xff>:m
8: 30 c9 ff 0f storw r3,0xfff <main\+0xfff>:m
c: 40 c9 34 12 storw r4,0x1234 <main\+0x1234>:m
10: 50 c9 34 12 storw r5,0x1234 <main\+0x1234>:m
14: 13 00 07 fa storw r0,0x7a1234 <main\+0x7a1234>:l
18: 34 12
1a: 13 00 1b fa storw r1,0xba1234 <main\+0xba1234>:l
1e: 34 12
20: 13 00 2f ff storw r2,0xffffff <main\+0xffffff>:l
24: ff ff
26: 00 ce 00 00 storw r0,\[r12\]0x0:m
2a: 00 cf 00 00 storw r0,\[r12\]0x0:m
2e: 10 ce ff 00 storw r1,\[r12\]0xff:m
32: 10 cf ff 00 storw r1,\[r12\]0xff:m
36: 30 ce ff 0f storw r3,\[r12\]0xfff:m
3a: 30 cf ff 0f storw r3,\[r12\]0xfff:m
3e: 40 ce 34 12 storw r4,\[r13\]0x1234:m
42: 40 cf 34 12 storw r4,\[r13\]0x1234:m
46: 50 ce 34 12 storw r5,\[r13\]0x1234:m
4a: 50 cf 34 12 storw r5,\[r13\]0x1234:m
4e: 20 ce 67 45 storw r2,\[r12\]0x4567:m
52: 2a cf 34 12 storw r2,\[r12\]0xa1234:m
56: 10 d2 storw r1,0x4:s\(r1,r0\)
58: 32 d2 storw r3,0x4:s\(r3,r2\)
5a: 40 df 34 12 storw r4,0x1234:m\(r1,r0\)
5e: 52 df 34 12 storw r5,0x1234:m\(r3,r2\)
62: 13 00 60 da storw r6,0xa1234:l\(r1,r0\)
66: 34 12
68: 19 00 10 df storw r1,0xffffc:l\(r1,r0\)
6c: fc ff
6e: 19 00 32 df storw r3,0xffffc:l\(r3,r2\)
72: fc ff
74: 19 00 40 df storw r4,0xfedcc:l\(r1,r0\)
78: cc ed
7a: 19 00 52 df storw r5,0xfedcc:l\(r3,r2\)
7e: cc ed
80: 19 00 60 d5 storw r6,0x5edcc:l\(r1,r0\)
84: cc ed
86: 00 d0 storw r0,0x0:s\(r1,r0\)
88: 00 d0 storw r0,0x0:s\(r1,r0\)
8a: 00 df 0f 00 storw r0,0xf:m\(r1,r0\)
8e: 10 df 0f 00 storw r1,0xf:m\(r1,r0\)
92: 20 df 34 12 storw r2,0x1234:m\(r1,r0\)
96: 32 df cd ab storw r3,0xabcd:m\(r3,r2\)
9a: 43 df ff af storw r4,0xafff:m\(r4,r3\)
9e: 13 00 55 da storw r5,0xa1234:l\(r6,r5\)
a2: 34 12
a4: 19 00 00 df storw r0,0xffff1:l\(r1,r0\)
a8: f1 ff
aa: 19 00 10 df storw r1,0xffff1:l\(r1,r0\)
ae: f1 ff
b0: 19 00 20 df storw r2,0xfedcc:l\(r1,r0\)
b4: cc ed
b6: 19 00 32 df storw r3,0xf5433:l\(r3,r2\)
ba: 33 54
bc: 19 00 43 df storw r4,0xf5001:l\(r4,r3\)
c0: 01 50
c2: 19 00 55 d5 storw r5,0x5edcc:l\(r6,r5\)
c6: cc ed
c8: 00 de storw r0,\[r12\]0x0:s\(r1,r0\)
ca: 18 de storw r1,\[r13\]0x0:s\(r1,r0\)
cc: f0 c6 04 12 storw r15,\[r12\]0x234:m\(r1,r0\)
d0: 13 00 38 e1 storw r3,\[r13\]0x1abcd:l\(r1,r0\)
d4: cd ab
d6: 13 00 40 ea storw r4,\[r12\]0xa1234:l\(r1,r0\)
da: 34 12
dc: 13 00 58 eb storw r5,\[r13\]0xb1234:l\(r1,r0\)
e0: 34 12
e2: 13 00 68 ef storw r6,\[r13\]0xfffff:l\(r1,r0\)
e6: ff ff
e8: 40 c1 cd 0b storw \$0x4:s,0xbcd <main\+0xbcd>:m
ec: 5a c1 cd ab storw \$0x5:s,0xaabcd <main\+0xaabcd>:m
f0: 13 00 3f 3a storw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l
f4: cd ab
f6: 50 c4 14 00 storw \$0x5:s,\[r13\]0x14:m
fa: 40 c5 fc ab storw \$0x4:s,\[r13\]0xabfc:m
fe: 30 c4 34 12 storw \$0x3:s,\[r12\]0x1234:m
102: 30 c5 34 12 storw \$0x3:s,\[r12\]0x1234:m
106: 30 c4 34 00 storw \$0x3:s,\[r12\]0x34:m
10a: 30 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
10e: 31 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
112: 36 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
116: 32 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
11a: 37 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
11e: 33 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
122: 34 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
126: 35 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
12a: 38 c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
12e: 39 c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
132: 3e c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
136: 3a c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
13a: 3f c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
13e: 3b c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
142: 3c c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
146: 3d c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
14a: 3e c6 5a 4b storw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
14e: 37 c6 1a 41 storw \$0x1:s,\[r12\]0x17a:m\(r6,r5\)
152: 3f c6 14 01 storw \$0x1:s,\[r13\]0x134:m\(r6,r5\)
156: 13 00 36 2a storw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
15a: de bc
15c: 13 00 5e 20 storw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
160: cd ab
162: 13 00 37 20 storw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
166: cd ab
168: 13 00 3f 20 storw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
16c: de bc
16e: 13 00 52 00 storw \$0x5:s,0x0:l\(r2\)
172: 00 00
174: 3c c3 34 00 storw \$0x3:s,0x34:m\(r12\)
178: 3d c3 ab 00 storw \$0x3:s,0xab:m\(r13\)
17c: 13 00 51 00 storw \$0x5:s,0xad:l\(r1\)
180: ad 00
182: 13 00 52 00 storw \$0x5:s,0xcd:l\(r2\)
186: cd 00
188: 13 00 50 00 storw \$0x5:s,0xfff:l\(r0\)
18c: ff 0f
18e: 13 00 34 00 storw \$0x3:s,0xbcd:l\(r4\)
192: cd 0b
194: 3c c3 ff 0f storw \$0x3:s,0xfff:m\(r12\)
198: 3d c3 ff 0f storw \$0x3:s,0xfff:m\(r13\)
19c: 3d c3 ff ff storw \$0x3:s,0xffff:m\(r13\)
1a0: 3c c3 43 23 storw \$0x3:s,0x2343:m\(r12\)
1a4: 13 00 32 01 storw \$0x3:s,0x2345:l\(r2\)
1a8: 45 23
1aa: 13 00 38 04 storw \$0x3:s,0xabcd:l\(r8\)
1ae: cd ab
1b0: 13 00 3d 1f storw \$0x3:s,0xfabcd:l\(r13\)
1b4: cd ab
1b6: 13 00 38 0f storw \$0x3:s,0xabcd:l\(r8\)
1ba: cd ab
1bc: 13 00 39 0f storw \$0x3:s,0xabcd:l\(r9\)
1c0: cd ab
1c2: 13 00 39 04 storw \$0x3:s,0xabcd:l\(r9\)
1c6: cd ab
1c8: 31 c2 storw \$0x3:s,0x0:s\(r2,r1\)
1ca: 51 c3 01 00 storw \$0x5:s,0x1:m\(r2,r1\)
1ce: 41 c3 34 12 storw \$0x4:s,0x1234:m\(r2,r1\)
1d2: 31 c3 34 12 storw \$0x3:s,0x1234:m\(r2,r1\)
1d6: 13 00 31 11 storw \$0x3:s,0x12345:l\(r2,r1\)
1da: 45 23
1dc: 31 c3 23 01 storw \$0x3:s,0x123:m\(r2,r1\)
1e0: 13 00 31 11 storw \$0x3:s,0x12345:l\(r2,r1\)
1e4: 45 23

144
gas/testsuite/gas/cr16/storw_test.s Normal file
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.text
.global main
main:
######################
# storw reg abs20/24
######################
storw r0,0x0
storw r1,0xff
storw r3,0xfff
storw r4,0x1234
storw r5,0x1234
storw r0,0x7A1234
storw r1,0xBA1234
storw r2,0xffffff
######################
# storw abs20 rel reg
######################
storw r0,[r12]0x0
storw r0,[r13]0x0
storw r1,[r12]0xff
storw r1,[r13]0xff
storw r3,[r12]0xfff
storw r3,[r13]0xfff
storw r4,[r12]0x1234
storw r4,[r13]0x1234
storw r5,[r12]0x1234
storw r5,[r13]0x1234
storw r2,[r12]0x4567
storw r2,[r13]0xA1234
###################################
# storw reg rbase(disp20/-disp20)
###################################
storw r1,0x4(r1,r0)
storw r3,0x4(r3,r2)
storw r4,0x1234(r1,r0)
storw r5,0x1234(r3,r2)
storw r6,0xA1234(r1,r0)
storw r1,-0x4(r1,r0)
storw r3,-0x4(r3,r2)
storw r4,-0x1234(r1,r0)
storw r5,-0x1234(r3,r2)
storw r6,-0xA1234(r1,r0)
#################################################
# storw reg rpbase(disp4/disp16/disp20/-disp20)
#################################################
storw r0,0x0(r1,r0)
storw r0,0x0(r1,r0)
storw r0,0xf(r1,r0)
storw r1,0xf(r1,r0)
storw r2,0x1234(r1,r0)
storw r3,0xabcd(r3,r2)
storw r4,0xAfff(r4,r3)
storw r5,0xA1234(r6,r5)
storw r0,-0xf(r1,r0)
storw r1,-0xf(r1,r0)
storw r2,-0x1234(r1,r0)
storw r3,-0xabcd(r3,r2)
storw r4,-0xAfff(r4,r3)
storw r5,-0xA1234(r6,r5)
####################################
# storw rbase(disp0/disp14) rel reg
####################################
storw r0,[r12]0x0(r1,r0)
storw r1,[r13]0x0(r1,r0)
storw r2,[r12]0x1234(r1,r0)
storw r3,[r13]0x1abcd(r1,r0)
#################################
# storw reg rpbase(disp20) rel
#################################
storw r4,[r12]0xA1234(r1,r0)
storw r5,[r13]0xB1234(r1,r0)
storw r6,[r13]0xfffff(r1,r0)
#######################
# storw reg, uimm16/20
######################
storw $4,0xbcd
storw $5,0xaabcd
storw $3,0xfaabcd
#######################
# storw reg, uimm16/20
######################
storw $5,[r12]0x14
storw $4,[r13]0xabfc
storw $3,[r12]0x1234
storw $3,[r13]0x1234
storw $3,[r12]0x34
#######################
# storw imm, index-rbase
######################
storw $3,[r12]0xa7a(r1,r0)
storw $3,[r12]0xa7a(r3,r2)
storw $3,[r12]0xa7a(r4,r3)
storw $3,[r12]0xa7a(r5,r4)
storw $3,[r12]0xa7a(r6,r5)
storw $3,[r12]0xa7a(r7,r6)
storw $3,[r12]0xa7a(r9,r8)
storw $3,[r12]0xa7a(r11,r10)
storw $3,[r13]0xa7a(r1,r0)
storw $3,[r13]0xa7a(r3,r2)
storw $3,[r13]0xa7a(r4,r3)
storw $3,[r13]0xa7a(r5,r4)
storw $3,[r13]0xa7a(r6,r5)
storw $3,[r13]0xa7a(r7,r6)
storw $3,[r13]0xa7a(r9,r8)
storw $3,[r13]0xa7a(r11,r10)
storw $5,[r13]0xb7a(r4,r3)
storw $1,[r12]0x17a(r6,r5)
storw $1,[r13]0x134(r6,r5)
storw $3,[r12]0xabcde(r4,r3)
storw $5,[r13]0xabcd(r4,r3)
storw $3,[r12]0xabcd(r6,r5)
storw $3,[r13]0xbcde(r6,r5)
#######################
# storw imm4, rbase(disp)
######################
storw $5,0x0(r2)
storw $3,0x34(r12)
storw $3,0xab(r13)
storw $5,0xad(r1)
storw $5,0xcd(r2)
storw $5,0xfff(r0)
storw $3,0xbcd(r4)
storw $3,0xfff(r12)
storw $3,0xfff(r13)
storw $3,0xffff(r13)
storw $3,0x2343(r12)
storw $3,0x12345(r2)
storw $3,0x4abcd(r8)
storw $3,0xfabcd(r13)
storw $3,0xfabcd(r8)
storw $3,0xfabcd(r9)
storw $3,0x4abcd(r9)
##########################
# storw imm, disp20(rpbase)
#########################
storw $3,0x0(r2,r1)
storw $5,0x1(r2,r1)
storw $4,0x1234(r2,r1)
storw $3,0x1234(r2,r1)
storw $3,0x12345(r2,r1)
storw $3,0x123(r2,r1)
storw $3,0x12345(r2,r1)

69
gas/testsuite/gas/cr16/sub_test.d Normal file
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#as:
#objdump: -dr
#name: sub_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: f1 38 subb \$0xf:s,r1
2: b2 38 ff 00 subb \$0xff:m,r2
6: b1 38 ff 0f subb \$0xfff:m,r1
a: b1 38 14 00 subb \$0x14:m,r1
e: a2 38 subb \$0xa:s,r2
10: 12 39 subb r1,r2
12: 23 39 subb r2,r3
14: 34 39 subb r3,r4
16: 56 39 subb r5,r6
18: 67 39 subb r6,r7
1a: 78 39 subb r7,r8
1c: f1 3c subcb \$0xf:s,r1
1e: b2 3c ff 00 subcb \$0xff:m,r2
22: b1 3c ff 0f subcb \$0xfff:m,r1
26: b1 3c 14 00 subcb \$0x14:m,r1
2a: a2 3c subcb \$0xa:s,r2
2c: 12 3d subcb r1,r2
2e: 23 3d subcb r2,r3
30: 34 3d subcb r3,r4
32: 56 3d subcb r5,r6
34: 67 3d subcb r6,r7
36: 78 3d subcb r7,r8
38: f1 3e subcw \$0xf:s,r1
3a: b2 3e ff 00 subcw \$0xff:m,r2
3e: b1 3e ff 0f subcw \$0xfff:m,r1
42: b1 3e 14 00 subcw \$0x14:m,r1
46: a2 3e subcw \$0xa:s,r2
48: 12 3f subcw r1,r2
4a: 23 3f subcw r2,r3
4c: 34 3f subcw r3,r4
4e: 56 3f subcw r5,r6
50: 67 3f subcw r6,r7
52: 78 3f subcw r7,r8
54: f1 3a subw \$0xf:s,r1
56: b2 3a ff 00 subw \$0xff:m,r2
5a: b1 3a ff 0f subw \$0xfff:m,r1
5e: b1 3a 14 00 subw \$0x14:m,r1
62: a2 3a subw \$0xa:s,r2
64: 12 3b subw r1,r2
66: 23 3b subw r2,r3
68: 34 3b subw r3,r4
6a: 56 3b subw r5,r6
6c: 67 3b subw r6,r7
6e: 78 3b subw r7,r8
70: 31 00 00 00 subd \$0xf:l,\(r2,r1\)
74: 0f 00
76: 31 00 00 00 subd \$0xff:l,\(r2,r1\)
7a: ff 00
7c: 31 00 00 00 subd \$0xfff:l,\(r2,r1\)
80: ff 0f
82: 31 00 00 00 subd \$0xffff:l,\(r2,r1\)
86: ff ff
88: 31 00 0f 00 subd \$0xfffff:l,\(r2,r1\)
8c: ff ff
8e: 31 00 ff 0f subd \$0xfffffff:l,\(r2,r1\)
92: ff ff
94: 31 00 ff ff subd \$0xffffffff:l,\(r2,r1\)
98: ff ff
9a: 14 00 31 c0 subd \(r4,r3\),\(r2,r1\)
9e: 14 00 31 c0 subd \(r4,r3\),\(r2,r1\)

93
gas/testsuite/gas/cr16/sub_test.s Normal file
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.text
.global main
main:
###########
# SUBB imm4/imm16, reg
###########
subb $0xf,r1
subb $0xff,r2
subb $0xfff,r1
#subb $0xffff,r2 // CHECK WITH CRASM 4.1
subb $20,r1
subb $10,r2
###########
# SUBB reg, reg
###########
subb r1,r2
subb r2,r3
subb r3,r4
subb r5,r6
subb r6,r7
subb r7,r8
###########
# SUBCB imm4/imm16, reg
###########
subcb $0xf,r1
subcb $0xff,r2
subcb $0xfff,r1
#subcb $0xffff,r2 // CHECK WITH CRASM 4.1
subcb $20,r1
subcb $10,r2
###########
# SUBCB reg, reg
###########
subcb r1,r2
subcb r2,r3
subcb r3,r4
subcb r5,r6
subcb r6,r7
subcb r7,r8
###########
# SUBCW imm4/imm16, reg
###########
subcw $0xf,r1
subcw $0xff,r2
subcw $0xfff,r1
#subcw $0xffff,r2 // CHECK WITH CRASM 4.1
subcw $20,r1
subcw $10,r2
###########
# SUBCW reg, reg
###########
subcw r1,r2
subcw r2,r3
subcw r3,r4
subcw r5,r6
subcw r6,r7
subcw r7,r8
###########
# SUBW imm4/imm16, reg
###########
subw $0xf,r1
subw $0xff,r2
subw $0xfff,r1
#subw $0xffff,r2 // CHECK WITH CRASM 4.1
subw $20,r1
subw $10,r2
###########
# SUBW reg, reg
###########
subw r1,r2
subw r2,r3
subw r3,r4
subw r5,r6
subw r6,r7
subw r7,r8
###########
# SUBD imm4/imm16/imm32, regp
###########
subd $0xf,(r2,r1)
subd $0xff,(r2,r1)
subd $0xfff,(r2,r1)
subd $0xffff,(r2,r1)
subd $0xfffff,(r2,r1)
subd $0xfffffff,(r2,r1)
subd $0xffffffff,(r2,r1)
###########
# SUBD regp, regp
###########
subd (r4,r3),(r2,r1)
subd (r4,r3),(r2,r1)
#subd $10,(sp)
#subd $14,(sp)
#subd $8,(sp)

37
gas/testsuite/gas/cr16/tbit_test.d Normal file
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#as:
#objdump: -dr
#name: tbit_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 00 06 tbit \$0x0:s,r0
2: 11 06 tbit \$0x1:s,r1
4: 22 06 tbit \$0x2:s,r2
6: 33 06 tbit \$0x3:s,r3
8: 44 06 tbit \$0x4:s,r4
a: 55 06 tbit \$0x5:s,r5
c: 66 06 tbit \$0x6:s,r6
e: 77 06 tbit \$0x7:s,r7
10: 88 06 tbit \$0x8:s,r8
12: 99 06 tbit \$0x9:s,r9
14: aa 06 tbit \$0xa:s,r10
16: bb 06 tbit \$0xb:s,r11
18: cc 06 tbit \$0xc:s,r12
1a: dd 06 tbit \$0xd:s,r13
1c: 00 07 tbit r0,r0
1e: 11 07 tbit r1,r1
20: 22 07 tbit r2,r2
22: 33 07 tbit r3,r3
24: 44 07 tbit r4,r4
26: 55 07 tbit r5,r5
28: 66 07 tbit r6,r6
2a: 77 07 tbit r7,r7
2c: 88 07 tbit r8,r8
2e: 99 07 tbit r9,r9
30: aa 07 tbit r10,r10
32: bb 07 tbit r11,r11
34: cc 07 tbit r12,r12
36: dd 07 tbit r13,r13

41
gas/testsuite/gas/cr16/tbit_test.s Normal file
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.text
.global main
main:
##################
# tbit uimm4, reg
#################
tbit $0,r0
tbit $1,r1
tbit $2,r2
tbit $3,r3
tbit $4,r4
tbit $5,r5
tbit $6,r6
tbit $7,r7
tbit $8,r8
tbit $9,r9
tbit $10,r10
tbit $11,r11
tbit $12,r12
tbit $13,r13
# tbit $14,r14 // Add error check for these INST
# tbit $15,r15 // Add error check for these INST
##################
# tbit reg, reg
#################
tbit r0,r0
tbit r1,r1
tbit r2,r2
tbit r3,r3
tbit r4,r4
tbit r5,r5
tbit r6,r6
tbit r7,r7
tbit r8,r8
tbit r9,r9
tbit r10,r10
tbit r11,r11
tbit r12,r12
tbit r13,r13
# tbit r14,r14 // Add error check for these INST
# tbit r15,r15 // Add error check for these INST

82
gas/testsuite/gas/cr16/tbitb_test.d Normal file
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#as:
#objdump: -dr
#name: tbitb_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: c0 7b cd 0b tbitb \$0x4,0xbcd <main\+0xbcd>:m
4: da 7b cd ab tbitb \$0x5,0xaabcd <main\+0xaabcd>:m
8: 10 00 3f fa tbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: 50 78 14 00 tbitb \$0x5,\[r12\]0x14:m
12: c0 78 fc ab tbitb \$0x4,\[r13\]0xabfc:m
16: 30 78 34 12 tbitb \$0x3,\[r12\]0x1234:m
1a: b0 78 34 12 tbitb \$0x3,\[r13\]0x1234:m
1e: 30 78 34 00 tbitb \$0x3,\[r12\]0x34:m
22: b0 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\)
26: b1 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\)
2a: b6 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\)
2e: b2 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\)
32: b7 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\)
36: b3 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\)
3a: b4 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\)
3e: b5 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\)
42: b8 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\)
46: b9 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\)
4a: be 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\)
4e: ba 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\)
52: bf 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\)
56: bb 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\)
5a: bc 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\)
5e: bd 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\)
62: be 7a 5a 4b tbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\)
66: b7 7a 1a 41 tbitb \$0x1,\[r12\]0x17a:m\(r6,r5\)
6a: bf 7a 14 01 tbitb \$0x1,\[r13\]0x134:m\(r6,r5\)
6e: 10 00 36 ea tbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\)
72: de bc
74: 10 00 5e e0 tbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\)
78: cd ab
7a: 10 00 37 e0 tbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\)
7e: cd ab
80: 10 00 3f e0 tbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\)
84: de bc
86: 10 00 52 c0 tbitb \$0x5,0x0:l\(r2\)
8a: 00 00
8c: 3c 7b 34 00 tbitb \$0x3,0x34:m\(r12\)
90: 3d 7b ab 00 tbitb \$0x3,0xab:m\(r13\)
94: 10 00 51 c0 tbitb \$0x5,0xad:l\(r1\)
98: ad 00
9a: 10 00 52 c0 tbitb \$0x5,0xcd:l\(r2\)
9e: cd 00
a0: 10 00 50 c0 tbitb \$0x5,0xfff:l\(r0\)
a4: ff 0f
a6: 10 00 34 c0 tbitb \$0x3,0xbcd:l\(r4\)
aa: cd 0b
ac: 3c 7b ff 0f tbitb \$0x3,0xfff:m\(r12\)
b0: 3d 7b ff 0f tbitb \$0x3,0xfff:m\(r13\)
b4: 3d 7b ff ff tbitb \$0x3,0xffff:m\(r13\)
b8: 3c 7b 43 23 tbitb \$0x3,0x2343:m\(r12\)
bc: 10 00 32 c1 tbitb \$0x3,0x2345:l\(r2\)
c0: 45 23
c2: 10 00 38 c4 tbitb \$0x3,0xabcd:l\(r8\)
c6: cd ab
c8: 10 00 3d df tbitb \$0x3,0xfabcd:l\(r13\)
cc: cd ab
ce: 10 00 38 cf tbitb \$0x3,0xabcd:l\(r8\)
d2: cd ab
d4: 10 00 39 cf tbitb \$0x3,0xabcd:l\(r9\)
d8: cd ab
da: 10 00 39 c4 tbitb \$0x3,0xabcd:l\(r9\)
de: cd ab
e0: 31 7a tbitb \$0x3,0x0:s\(r2,r1\)
e2: 51 7b 01 00 tbitb \$0x5,0x1:m\(r2,r1\)
e6: 41 7b 34 12 tbitb \$0x4,0x1234:m\(r2,r1\)
ea: 31 7b 34 12 tbitb \$0x3,0x1234:m\(r2,r1\)
ee: 10 00 31 d1 tbitb \$0x3,0x12345:l\(r2,r1\)
f2: 45 23
f4: 31 7b 23 01 tbitb \$0x3,0x123:m\(r2,r1\)
f8: 10 00 31 d1 tbitb \$0x3,0x12345:l\(r2,r1\)
fc: 45 23

62
gas/testsuite/gas/cr16/tbitb_test.s Normal file
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.text
.global main
main:
tbitb $4,0xbcd
tbitb $5,0xaabcd
tbitb $3,0xfaabcd
tbitb $5,[r12]0x14
tbitb $4,[r13]0xabfc
tbitb $3,[r12]0x1234
tbitb $3,[r13]0x1234
tbitb $3,[r12]0x34
tbitb $3,[r12]0xa7a(r1,r0)
tbitb $3,[r12]0xa7a(r3,r2)
tbitb $3,[r12]0xa7a(r4,r3)
tbitb $3,[r12]0xa7a(r5,r4)
tbitb $3,[r12]0xa7a(r6,r5)
tbitb $3,[r12]0xa7a(r7,r6)
tbitb $3,[r12]0xa7a(r9,r8)
tbitb $3,[r12]0xa7a(r11,r10)
tbitb $3,[r13]0xa7a(r1,r0)
tbitb $3,[r13]0xa7a(r3,r2)
tbitb $3,[r13]0xa7a(r4,r3)
tbitb $3,[r13]0xa7a(r5,r4)
tbitb $3,[r13]0xa7a(r6,r5)
tbitb $3,[r13]0xa7a(r7,r6)
tbitb $3,[r13]0xa7a(r9,r8)
tbitb $3,[r13]0xa7a(r11,r10)
tbitb $5,[r13]0xb7a(r4,r3)
tbitb $1,[r12]0x17a(r6,r5)
tbitb $1,[r13]0x134(r6,r5)
tbitb $3,[r12]0xabcde(r4,r3)
tbitb $5,[r13]0xabcd(r4,r3)
tbitb $3,[r12]0xabcd(r6,r5)
tbitb $3,[r13]0xbcde(r6,r5)
tbitb $5,0x0(r2)
tbitb $3,0x34(r12)
tbitb $3,0xab(r13)
tbitb $5,0xad(r1)
tbitb $5,0xcd(r2)
tbitb $5,0xfff(r0)
tbitb $3,0xbcd(r4)
tbitb $3,0xfff(r12)
tbitb $3,0xfff(r13)
tbitb $3,0xffff(r13)
tbitb $3,0x2343(r12)
tbitb $3,0x12345(r2)
tbitb $3,0x4abcd(r8)
tbitb $3,0xfabcd(r13)
tbitb $3,0xfabcd(r8)
tbitb $3,0xfabcd(r9)
tbitb $3,0x4abcd(r9)
tbitb $3,0x0(r2,r1)
tbitb $5,0x1(r2,r1)
tbitb $4,0x1234(r2,r1)
tbitb $3,0x1234(r2,r1)
tbitb $3,0x12345(r2,r1)
tbitb $3,0x123(r2,r1)
tbitb $3,0x12345(r2,r1)

155
gas/testsuite/gas/cr16/tbitw_test.d Normal file
View File

@ -0,0 +1,155 @@
#as:
#objdump: -dr
#name: tbitw_test
.*: +file format .*
Disassembly of section .text:
00000000 <main>:
0: 40 7f cd 0b tbitw \$0x4:s,0xbcd <main\+0xbcd>:m
4: 5a 7f cd ab tbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m
8: 11 00 3f fa tbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l
c: cd ab
e: a0 7f cd 0b tbitw \$0xa:s,0xbcd <main\+0xbcd>:m
12: fa 7f cd ab tbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m
16: 11 00 ef fa tbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l
1a: cd ab
1c: 50 7c 14 00 tbitw \$0x5:s,\[r13\]0x14:m
20: 40 7d fc ab tbitw \$0x4:s,\[r13\]0xabfc:m
24: 30 7c 34 12 tbitw \$0x3:s,\[r12\]0x1234:m
28: 30 7d 34 12 tbitw \$0x3:s,\[r12\]0x1234:m
2c: 30 7c 34 00 tbitw \$0x3:s,\[r12\]0x34:m
30: f0 7c 14 00 tbitw \$0xf:s,\[r13\]0x14:m
34: e0 7d fc ab tbitw \$0xe:s,\[r13\]0xabfc:m
38: d0 7c 34 12 tbitw \$0xd:s,\[r13\]0x1234:m
3c: d0 7d 34 12 tbitw \$0xd:s,\[r13\]0x1234:m
40: b0 7c 34 00 tbitw \$0xb:s,\[r12\]0x34:m
44: f0 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
48: f1 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
4c: f6 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
50: f2 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
54: f7 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
58: f3 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
5c: f4 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
60: f5 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
64: f8 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
68: f9 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
6c: fe 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
70: fa 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
74: ff 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
78: fb 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
7c: fc 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
80: fd 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
84: fe 7a 5a 4b tbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
88: f7 7a 1a 41 tbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\)
8c: ff 7a 14 01 tbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\)
90: 11 00 36 ea tbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
94: de bc
96: 11 00 5e e0 tbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
9a: cd ab
9c: 11 00 37 e0 tbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
a0: cd ab
a2: 11 00 3f e0 tbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
a6: de bc
a8: f0 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\)
ac: f1 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\)
b0: f6 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\)
b4: f2 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\)
b8: f7 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\)
bc: f3 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\)
c0: f4 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\)
c4: f5 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\)
c8: f8 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\)
cc: f9 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\)
d0: fe 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\)
d4: fa 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\)
d8: ff 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\)
dc: fb 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\)
e0: fc 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\)
e4: fd 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\)
e8: fe 7a fa 4b tbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
ec: f7 7a ba 41 tbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
f0: ff 7a b4 01 tbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
f4: 11 00 d6 ea tbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
f8: de bc
fa: 11 00 fe e0 tbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
fe: cd ab
100: 11 00 d7 e0 tbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
104: cd ab
106: 11 00 df e0 tbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
10a: de bc
10c: 11 00 52 c0 tbitw \$0x5:s,0x0:l\(r2\)
110: 00 00
112: 3c 79 34 00 tbitw \$0x3:s,0x34:m\(r12\)
116: 3d 79 ab 00 tbitw \$0x3:s,0xab:m\(r13\)
11a: 11 00 51 c0 tbitw \$0x5:s,0xad:l\(r1\)
11e: ad 00
120: 11 00 52 c0 tbitw \$0x5:s,0xcd:l\(r2\)
124: cd 00
126: 11 00 50 c0 tbitw \$0x5:s,0xfff:l\(r0\)
12a: ff 0f
12c: 11 00 34 c0 tbitw \$0x3:s,0xbcd:l\(r4\)
130: cd 0b
132: 3c 79 ff 0f tbitw \$0x3:s,0xfff:m\(r12\)
136: 3d 79 ff 0f tbitw \$0x3:s,0xfff:m\(r13\)
13a: 3d 79 ff ff tbitw \$0x3:s,0xffff:m\(r13\)
13e: 3c 79 43 23 tbitw \$0x3:s,0x2343:m\(r12\)
142: 11 00 32 c1 tbitw \$0x3:s,0x2345:l\(r2\)
146: 45 23
148: 11 00 38 c4 tbitw \$0x3:s,0xabcd:l\(r8\)
14c: cd ab
14e: 11 00 3d df tbitw \$0x3:s,0xfabcd:l\(r13\)
152: cd ab
154: 11 00 38 cf tbitw \$0x3:s,0xabcd:l\(r8\)
158: cd ab
15a: 11 00 39 cf tbitw \$0x3:s,0xabcd:l\(r9\)
15e: cd ab
160: 11 00 39 c4 tbitw \$0x3:s,0xabcd:l\(r9\)
164: cd ab
166: 11 00 f2 c0 tbitw \$0xf:s,0x0:l\(r2\)
16a: 00 00
16c: dc 79 34 00 tbitw \$0xd:s,0x34:m\(r12\)
170: dd 79 ab 00 tbitw \$0xd:s,0xab:m\(r13\)
174: 11 00 f1 c0 tbitw \$0xf:s,0xad:l\(r1\)
178: ad 00
17a: 11 00 f2 c0 tbitw \$0xf:s,0xcd:l\(r2\)
17e: cd 00
180: 11 00 f0 c0 tbitw \$0xf:s,0xfff:l\(r0\)
184: ff 0f
186: 11 00 d4 c0 tbitw \$0xd:s,0xbcd:l\(r4\)
18a: cd 0b
18c: dc 79 ff 0f tbitw \$0xd:s,0xfff:m\(r12\)
190: dd 79 ff 0f tbitw \$0xd:s,0xfff:m\(r13\)
194: dd 79 ff ff tbitw \$0xd:s,0xffff:m\(r13\)
198: dc 79 43 23 tbitw \$0xd:s,0x2343:m\(r12\)
19c: 11 00 d2 c1 tbitw \$0xd:s,0x2345:l\(r2\)
1a0: 45 23
1a2: 11 00 d8 c4 tbitw \$0xd:s,0xabcd:l\(r8\)
1a6: cd ab
1a8: 11 00 dd df tbitw \$0xd:s,0xfabcd:l\(r13\)
1ac: cd ab
1ae: 11 00 d8 cf tbitw \$0xd:s,0xabcd:l\(r8\)
1b2: cd ab
1b4: 11 00 d9 cf tbitw \$0xd:s,0xabcd:l\(r9\)
1b8: cd ab
1ba: 11 00 d9 c4 tbitw \$0xd:s,0xabcd:l\(r9\)
1be: cd ab
1c0: 31 7e tbitw \$0x3:s,0x0:s\(r2,r1\)
1c2: 51 79 01 00 tbitw \$0x5:s,0x1:m\(r2,r1\)
1c6: 41 79 34 12 tbitw \$0x4:s,0x1234:m\(r2,r1\)
1ca: 31 79 34 12 tbitw \$0x3:s,0x1234:m\(r2,r1\)
1ce: 11 00 31 d1 tbitw \$0x3:s,0x12345:l\(r2,r1\)
1d2: 45 23
1d4: 31 79 23 01 tbitw \$0x3:s,0x123:m\(r2,r1\)
1d8: 11 00 31 d1 tbitw \$0x3:s,0x12345:l\(r2,r1\)
1dc: 45 23
1de: d1 7e tbitw \$0xd:s,0x0:s\(r2,r1\)
1e0: f1 79 01 00 tbitw \$0xf:s,0x1:m\(r2,r1\)
1e4: e1 79 34 12 tbitw \$0xe:s,0x1234:m\(r2,r1\)
1e8: d1 79 34 12 tbitw \$0xd:s,0x1234:m\(r2,r1\)
1ec: 11 00 d1 d1 tbitw \$0xd:s,0x12345:l\(r2,r1\)
1f0: 45 23
1f2: d1 79 23 01 tbitw \$0xd:s,0x123:m\(r2,r1\)
1f6: 11 00 d1 d1 tbitw \$0xd:s,0x12345:l\(r2,r1\)
1fa: 45 23

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