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RISC-V: Scalar crypto instructions and operand set.
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support. The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add a new Entropy Source CSR define 'seed' located at address 0x015. bfd/ * elfxx-riscv.c (riscv_multi_subset_supports): Added support for crypto extension. gas/ *config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR. (riscv_csr_address): Checked for CSR_CLASS_ZKR. (validate_riscv_insn): Added y and Y for bs and rnum operands. (riscv_ip): Handle y and Y operands. include/ * opcode/riscv-opc.h: Added encodings of crypto instructions. Also defined new csr seed, which address is 0x15. * opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto. opcodes/ * riscv-dis.c (print_insn_args): Recognized new y and Y operands. * riscv-opc.c (riscv_opcodes): Added crypto instructions.
This commit is contained in:
jiawei
Nelson Chu
parent
dfdba09776
commit
3d1cafa0c6
@ -2180,6 +2180,31 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zbc");
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case INSN_CLASS_ZBS:
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return riscv_subset_supports (rps, "zbs");
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case INSN_CLASS_ZBKB:
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return riscv_subset_supports (rps, "zbkb");
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case INSN_CLASS_ZBKC:
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return riscv_subset_supports (rps, "zbkc");
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case INSN_CLASS_ZBKX:
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return riscv_subset_supports (rps, "zbkx");
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case INSN_CLASS_ZBB_OR_ZBKB:
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return (riscv_subset_supports (rps, "zbb")
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|| riscv_subset_supports (rps, "zbkb"));
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case INSN_CLASS_ZBC_OR_ZBKC:
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return (riscv_subset_supports (rps, "zbc")
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|| riscv_subset_supports (rps, "zbkc"));
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case INSN_CLASS_ZKND:
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return riscv_subset_supports (rps, "zknd");
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case INSN_CLASS_ZKNE:
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return riscv_subset_supports (rps, "zkne");
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case INSN_CLASS_ZKNH:
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return riscv_subset_supports (rps, "zknh");
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case INSN_CLASS_ZKND_OR_ZKNE:
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return (riscv_subset_supports (rps, "zknd")
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|| riscv_subset_supports (rps, "zkne"));
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case INSN_CLASS_ZKSED:
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return riscv_subset_supports (rps, "zksed");
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case INSN_CLASS_ZKSH:
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return riscv_subset_supports (rps, "zksh");
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default:
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rps->error_handler
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(_("internal: unreachable INSN_CLASS_*"));
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@ -63,6 +63,7 @@ enum riscv_csr_class
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CSR_CLASS_I,
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CSR_CLASS_I_32, /* rv32 only */
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CSR_CLASS_F, /* f-ext only */
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CSR_CLASS_ZKR, /* zkr only */
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CSR_CLASS_DEBUG /* debug CSR */
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};
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@ -875,6 +876,10 @@ riscv_csr_address (const char *csr_name,
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result = riscv_subset_supports (&riscv_rps_as, "f");
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need_check_version = false;
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break;
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case CSR_CLASS_ZKR:
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result = riscv_subset_supports (&riscv_rps_as, "zkr");
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need_check_version = false;
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break;
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case CSR_CLASS_DEBUG:
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need_check_version = false;
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break;
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@ -1085,6 +1090,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
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case 'I': break; /* Macro operand, must be constant. */
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case 'D': /* RD, floating point. */
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case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
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case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
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case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
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case 'Z': /* RS1, CSR number. */
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case 'S': /* RS1, floating point. */
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case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
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@ -2706,6 +2713,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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}
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break;
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case 'y': /* bs immediate */
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my_getExpression (imm_expr, asarg);
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check_absolute_expr (ip, imm_expr, FALSE);
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if ((unsigned long)imm_expr->X_add_number > 3)
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as_bad(_("Improper bs immediate (%lu)"),
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(unsigned long)imm_expr->X_add_number);
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INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
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imm_expr->X_op = O_absent;
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asarg = expr_end;
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continue;
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case 'Y': /* rnum immediate */
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my_getExpression (imm_expr, asarg);
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check_absolute_expr (ip, imm_expr, FALSE);
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if ((unsigned long)imm_expr->X_add_number > 10)
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as_bad(_("Improper rnum immediate (%lu)"),
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(unsigned long)imm_expr->X_add_number);
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INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
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imm_expr->X_op = O_absent;
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asarg = expr_end;
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continue;
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case 'z':
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if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
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|| imm_expr->X_op != O_constant
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@ -443,6 +443,8 @@
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#define MASK_SEXT_H 0xfff0707f
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#define MATCH_PACK 0x8004033
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#define MASK_PACK 0xfe00707f
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#define MATCH_PACKH 0x8007033
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#define MASK_PACKH 0xfe00707f
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#define MATCH_PACKW 0x800403b
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#define MASK_PACKW 0xfe00707f
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#define MATCH_ANDN 0x40007033
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@ -461,6 +463,10 @@
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#define MASK_GREVI 0xfc00707f
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#define MATCH_GORCI 0x28005013
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#define MASK_GORCI 0xfc00707f
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#define MATCH_SHFLI 0x8001013
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#define MASK_SHFLI 0xfe00707f
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#define MATCH_UNSHFLI 0x8005013
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#define MASK_UNSHFLI 0xfe00707f
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#define MATCH_CLZW 0x6000101b
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#define MASK_CLZW 0xfff0707f
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#define MATCH_CTZW 0x6010101b
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@ -495,6 +501,10 @@
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#define MASK_CLMULH 0xfe00707f
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#define MATCH_CLMULR 0xa002033
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#define MASK_CLMULR 0xfe00707f
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#define MATCH_XPERM4 0x28002033
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#define MASK_XPERM4 0xfe00707f
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#define MATCH_XPERM8 0x28004033
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#define MASK_XPERM8 0xfe00707f
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#define MATCH_BCLRI 0x48001013
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#define MASK_BCLRI 0xfc00707f
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#define MATCH_BSETI 0x28001013
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@ -637,6 +647,64 @@
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#define MASK_C_LDSP 0xe003
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#define MATCH_C_SDSP 0xe002
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#define MASK_C_SDSP 0xe003
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#define MATCH_SM3P0 0x10801013
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#define MASK_SM3P0 0xfff0707f
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#define MATCH_SM3P1 0x10901013
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#define MASK_SM3P1 0xfff0707f
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#define MATCH_SHA256SUM0 0x10001013
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#define MASK_SHA256SUM0 0xfff0707f
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#define MATCH_SHA256SUM1 0x10101013
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#define MASK_SHA256SUM1 0xfff0707f
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#define MATCH_SHA256SIG0 0x10201013
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#define MASK_SHA256SIG0 0xfff0707f
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#define MATCH_SHA256SIG1 0x10301013
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#define MASK_SHA256SIG1 0xfff0707f
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#define MATCH_SHA512SUM0R 0x50000033
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#define MASK_SHA512SUM0R 0xfe00707f
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#define MATCH_SHA512SUM1R 0x52000033
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#define MASK_SHA512SUM1R 0xfe00707f
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#define MATCH_SHA512SIG0L 0x54000033
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#define MASK_SHA512SIG0L 0xfe00707f
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#define MATCH_SHA512SIG0H 0x5c000033
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#define MASK_SHA512SIG0H 0xfe00707f
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#define MATCH_SHA512SIG1L 0x56000033
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#define MASK_SHA512SIG1L 0xfe00707f
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#define MATCH_SHA512SIG1H 0x5e000033
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#define MASK_SHA512SIG1H 0xfe00707f
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#define MATCH_SM4ED 0x30000033
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#define MASK_SM4ED 0x3e00707f
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#define MATCH_SM4KS 0x34000033
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#define MASK_SM4KS 0x3e00707f
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#define MATCH_AES32ESMI 0x26000033
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#define MASK_AES32ESMI 0x3e00707f
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#define MATCH_AES32ESI 0x22000033
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#define MASK_AES32ESI 0x3e00707f
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#define MATCH_AES32DSMI 0x2e000033
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#define MASK_AES32DSMI 0x3e00707f
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#define MATCH_AES32DSI 0x2a000033
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#define MASK_AES32DSI 0x3e00707f
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#define MATCH_SHA512SUM0 0x10401013
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#define MASK_SHA512SUM0 0xfff0707f
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#define MATCH_SHA512SUM1 0x10501013
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#define MASK_SHA512SUM1 0xfff0707f
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#define MATCH_SHA512SIG0 0x10601013
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#define MASK_SHA512SIG0 0xfff0707f
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#define MATCH_SHA512SIG1 0x10701013
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#define MASK_SHA512SIG1 0xfff0707f
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#define MATCH_AES64KS1I 0x31001013
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#define MASK_AES64KS1I 0xff00707f
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#define MATCH_AES64IM 0x30001013
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#define MASK_AES64IM 0xfff0707f
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#define MATCH_AES64KS2 0x7e000033
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#define MASK_AES64KS2 0xfe00707f
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#define MATCH_AES64ESM 0x36000033
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#define MASK_AES64ESM 0xfe00707f
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#define MATCH_AES64ES 0x32000033
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#define MASK_AES64ES 0xfe00707f
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#define MATCH_AES64DSM 0x3e000033
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#define MASK_AES64DSM 0xfe00707f
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#define MATCH_AES64DS 0x3a000033
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#define MASK_AES64DS 0xfe00707f
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/* Privileged CSR addresses. */
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#define CSR_USTATUS 0x0
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#define CSR_UIE 0x4
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@ -884,6 +952,7 @@
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#define CSR_TCONTROL 0x7a5
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#define CSR_MCONTEXT 0x7a8
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#define CSR_SCONTEXT 0x7aa
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#define CSR_SEED 0x015
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#endif /* RISCV_ENCODING_H */
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#ifdef DECLARE_INSN
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DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
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@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
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DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
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DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
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DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
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DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
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DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
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DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
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DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
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DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
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DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
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DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
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DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
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@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
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DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
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DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
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DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
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DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
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#endif /* DECLARE_CSR */
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#ifdef DECLARE_CSR_ALIAS
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DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
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@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
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#define OP_MASK_CFUNCT2 0x3
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#define OP_SH_CFUNCT2 5
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/* Scalar crypto fields. */
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#define OP_SH_BS 30
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#define OP_MASK_BS 3
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#define OP_SH_RNUM 20
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#define OP_MASK_RNUM 0xf
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/* ABI names for selected x-registers. */
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#define X_RA 1
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@ -320,6 +327,17 @@ enum riscv_insn_class
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INSN_CLASS_ZBB,
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INSN_CLASS_ZBC,
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INSN_CLASS_ZBS,
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INSN_CLASS_ZBKB,
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INSN_CLASS_ZBKC,
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INSN_CLASS_ZBKX,
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INSN_CLASS_ZKND,
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INSN_CLASS_ZKNE,
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INSN_CLASS_ZKNH,
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INSN_CLASS_ZKSED,
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INSN_CLASS_ZKSH,
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INSN_CLASS_ZBB_OR_ZBKB,
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INSN_CLASS_ZBC_OR_ZBKC,
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INSN_CLASS_ZKND_OR_ZKNE,
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};
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/* This structure holds information for a particular instruction. */
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@ -375,6 +375,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
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print (info->stream, "%s", riscv_gpr_names[rd]);
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break;
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case 'y':
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print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
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break;
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case 'z':
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print (info->stream, "%s", riscv_gpr_names[0]);
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break;
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@ -440,6 +444,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
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break;
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}
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case 'Y':
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print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
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break;
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case 'Z':
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print (info->stream, "%d", rs1);
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break;
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@ -84,6 +84,8 @@ const char * const riscv_fpr_names_abi[NFPR] =
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#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
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#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
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#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
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#define MATCH_SHAMT_BREV8 (0b00111 << OP_SH_SHAMT)
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#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
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#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
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static int
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@ -783,7 +785,7 @@ const struct riscv_opcode riscv_opcodes[] =
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{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
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{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
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/* Zbb instructions */
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/* Zbb or zbkb instructions. */
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{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
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{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
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{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
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@ -798,25 +800,32 @@ const struct riscv_opcode riscv_opcodes[] =
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{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
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{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
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{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
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{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
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{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
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{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
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{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
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{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
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{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
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{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
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{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
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{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
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{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
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{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
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{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
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{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
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{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
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{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
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{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
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{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
|
||||
{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
|
||||
{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
|
||||
{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
|
||||
{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
|
||||
{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
|
||||
{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
|
||||
{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
|
||||
{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
|
||||
{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
|
||||
{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
|
||||
{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
|
||||
{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
|
||||
{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
|
||||
{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
|
||||
{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
|
||||
{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
|
||||
{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
|
||||
{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
|
||||
{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
|
||||
{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
|
||||
|
||||
/* Zba instructions */
|
||||
/* Zba instructions. */
|
||||
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
|
||||
{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
|
||||
{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
|
||||
@ -828,12 +837,12 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
|
||||
{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
|
||||
|
||||
/* Zbc instructions */
|
||||
{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
|
||||
{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
|
||||
/* Zbc or zbkc instructions. */
|
||||
{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
|
||||
{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
|
||||
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
|
||||
|
||||
/* Zbs instructions */
|
||||
/* Zbs instructions. */
|
||||
{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
|
||||
{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
|
||||
{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
|
||||
@ -847,6 +856,49 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
|
||||
{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
|
||||
|
||||
/* Zbkx instructions. */
|
||||
{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
|
||||
{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
|
||||
|
||||
/* Zknd instructions. */
|
||||
{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
|
||||
{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
|
||||
{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
|
||||
{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
|
||||
{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
|
||||
{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
|
||||
{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
|
||||
|
||||
/* Zkne instructions. */
|
||||
{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
|
||||
{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
|
||||
{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
|
||||
{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
|
||||
|
||||
/* Zknh instructions. */
|
||||
{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
|
||||
{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
|
||||
{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
|
||||
{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
|
||||
{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
|
||||
{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
|
||||
{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
|
||||
{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
|
||||
{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
|
||||
{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
|
||||
{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
|
||||
{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
|
||||
{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
|
||||
{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
|
||||
|
||||
/* Zksed instructions. */
|
||||
{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
|
||||
{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
|
||||
|
||||
/* Zksh instructions */
|
||||
{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
|
||||
{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
|
||||
|
||||
/* Terminate the list. */
|
||||
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user