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bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insns

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This patch fixes the pseudoc syntax of the V4 instructions MOVS* and
LDXS* in order to reflect https://reviews.llvm.org/D144829.

opcodes/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
	instructions.

gas/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS*
	and LDXS* instructions.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
This commit is contained in:
Jose E. Marchesi 2023-07-24 02:11:34 +02:00
parent 167991e60e
commit 3ccfc0b46c
13 changed files with 69 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
gas/ChangeLog
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@ -1,3 +1,17 @@
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS*
and LDXS* instructions.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.

20
gas/doc/c-bpf.texi
View File

@ -264,15 +264,15 @@ Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
in @code{rd}.
@item movs rd, rs, 8
@itemx rd s= (i8) rs
@itemx rd s= (s8) rs
Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
@item movs rd, rs, 16
@itemx rd s= (i16) rs
@itemx rd s= (s16) rs
Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
@item movs rd, rs, 32
@itemx rd s= (i32) rs
@itemx rd s= (s32) rs
Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
@end table
@ -371,15 +371,15 @@ Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
in @code{rd}.
@item mov32s rd, rs, 8
@itemx rd s= (i8) rs
@itemx rd s= (s8) rs
Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
@item mov32s rd, rs, 16
@itemx rd s= (i16) rs
@itemx rd s= (s16) rs
Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
@item mov32s rd, rs, 32
@itemx rd s= (i32) rs
@itemx rd s= (s32) rs
Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
@end table
@ -490,19 +490,19 @@ Signed load to register instructions:
@table @code
@item ldxsdw rd, [rs + offset16]
@itemx rd = *(i64 *) (rs + offset16)
@itemx rd = *(s64 *) (rs + offset16)
Generic 64-bit signed load.
@item ldxsw rd, [rs + offset16]
@itemx rd = *(i32 *) (rs + offset16)
@itemx rd = *(s32 *) (rs + offset16)
Generic 32-bit signed load.
@item ldxsh rd, [rs + offset16]
@itemx rd = *(i16 *) (rs + offset16)
@itemx rd = *(s16 *) (rs + offset16)
Generic 16-bit signed load.
@item ldxsb rd, [rs + offset16]
@itemx rd = *(i8 *) (rs + offset16)
@itemx rd = *(s8 *) (rs + offset16)
Generic 8-bit signed load.
@end table

6
gas/testsuite/gas/bpf/alu-be-pseudoc.d
View File

@ -63,6 +63,6 @@ Disassembly of section .text:
1a0: dc 60 00 00 00 00 00 10 r6=be16 r6
1a8: dc 50 00 00 00 00 00 20 r5=be32 r5
1b0: dc 40 00 00 00 00 00 40 r4=be64 r4
1b8: bf 12 00 08 00 00 00 00 r1 s= \(i8\) r2
1c0: bf 12 00 10 00 00 00 00 r1 s= \(i16\) r2
1c8: bf 12 00 20 00 00 00 00 r1 s= \(i32\) r2
1b8: bf 12 00 08 00 00 00 00 r1 = \(s8\) r2
1c0: bf 12 00 10 00 00 00 00 r1 = \(s16\) r2
1c8: bf 12 00 20 00 00 00 00 r1 = \(s32\) r2

6
gas/testsuite/gas/bpf/alu-pseudoc.d
View File

@ -63,6 +63,6 @@ Disassembly of section .text:
1a0: dc 06 00 00 10 00 00 00 r6=be16 r6
1a8: dc 05 00 00 20 00 00 00 r5=be32 r5
1b0: dc 04 00 00 40 00 00 00 r4=be64 r4
1b8: bf 21 08 00 00 00 00 00 r1 s= \(i8\) r2
1c0: bf 21 10 00 00 00 00 00 r1 s= \(i16\) r2
1c8: bf 21 20 00 00 00 00 00 r1 s= \(i32\) r2
1b8: bf 21 08 00 00 00 00 00 r1 = \(s8\) r2
1c0: bf 21 10 00 00 00 00 00 r1 = \(s16\) r2
1c8: bf 21 20 00 00 00 00 00 r1 = \(s32\) r2

6
gas/testsuite/gas/bpf/alu-pseudoc.s
View File

@ -55,6 +55,6 @@
r6 = be16 r6
r5 = be32 r5
r4 = be64 r4
r1 s= (i8) r2
r1 s= (i16) r2
r1 s= (i32) r2
r1 = (s8) r2
r1 = (s16) r2
r1 = (s32) r2

6
gas/testsuite/gas/bpf/alu32-be-pseudoc.d
View File

@ -57,6 +57,6 @@ Disassembly of section .text:
170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef
178: cc 56 00 00 00 00 00 00 w5 s>>=w6
180: 8c 23 00 00 00 00 00 00 w2=-w3
188: bc 12 00 08 00 00 00 00 w1 s= \(i8\) w2
190: bc 12 00 10 00 00 00 00 w1 s= \(i16\) w2
198: bc 12 00 20 00 00 00 00 w1 s= \(i32\) w2
188: bc 12 00 08 00 00 00 00 w1 = \(s8\) w2
190: bc 12 00 10 00 00 00 00 w1 = \(s16\) w2
198: bc 12 00 20 00 00 00 00 w1 = \(s32\) w2

6
gas/testsuite/gas/bpf/alu32-pseudoc.d
View File

@ -57,6 +57,6 @@ Disassembly of section .text:
170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef
178: cc 65 00 00 00 00 00 00 w5 s>>=w6
180: 8c 32 00 00 00 00 00 00 w2=-w3
188: bc 21 08 00 00 00 00 00 w1 s= \(i8\) w2
190: bc 21 10 00 00 00 00 00 w1 s= \(i16\) w2
198: bc 21 20 00 00 00 00 00 w1 s= \(i32\) w2
188: bc 21 08 00 00 00 00 00 w1 = \(s8\) w2
190: bc 21 10 00 00 00 00 00 w1 = \(s16\) w2
198: bc 21 20 00 00 00 00 00 w1 = \(s32\) w2

6
gas/testsuite/gas/bpf/alu32-pseudoc.s
View File

@ -49,6 +49,6 @@
w4 s>>= 2125315823
w5 s>>= w6
w2 = - w3
w1 s= (i8) w2
w1 s= (i16) w2
w1 s= (i32) w2
w1 = (s8) w2
w1 = (s16) w2
w1 = (s32) w2

8
gas/testsuite/gas/bpf/mem-be-pseudoc.d
View File

@ -28,9 +28,9 @@ Disassembly of section .text:
88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
a0: 81 21 7e ef 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\)
a8: 89 21 7e ef 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\)
b0: 91 21 7e ef 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\)
b8: 99 21 7e ef 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\)
a0: 81 21 7e ef 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\)
a8: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
b0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
b8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
c0: 58 05 00 00 00 00 00 00 r0=\*\(u64\*\)skb\[r5\+0x0\]
c8: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)

8
gas/testsuite/gas/bpf/mem-pseudoc.d
View File

@ -28,9 +28,9 @@ Disassembly of section .text:
88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
a0: 81 12 ef 7e 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\)
a8: 89 12 ef 7e 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\)
b0: 91 12 ef 7e 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\)
b8: 99 12 ef 7e 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\)
a0: 81 12 ef 7e 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\)
a8: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
b0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
b8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
c0: 58 50 00 00 00 00 00 00 r0=\*\(u64\*\)skb\[r5\+0x0\]
c8: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)

8
gas/testsuite/gas/bpf/mem-pseudoc.s
View File

@ -21,9 +21,9 @@
*(u16 *)(r1 + 0x7eef) = 0x11223344
*(u32 *)(r1 + 0x7eef) = 0x11223344
*(u64 *)(r1 + -2) = 0x11223344
r2 = *(i32*)(r1+0x7eef)
r2 = *(i16*)(r1+0x7eef)
r2 = *(i8*)(r1+0x7eef)
r2 = *(i64*)(r1+0x7eef)
r2 = *(s32*)(r1+0x7eef)
r2 = *(s16*)(r1+0x7eef)
r2 = *(s8*)(r1+0x7eef)
r2 = *(s64*)(r1+0x7eef)
r0 = *(u64 *)skb[r5 + 0]
r2 = *(u32 *)(r1 + 0)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
instructions.
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.

20
opcodes/bpf-opc.c
View File

@ -89,11 +89,11 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
{BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
{BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=%w( i8 )%w%sr",
{BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%w=%w( s8 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
{BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=%w( i16 )%w%sr",
{BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%w=%w( s16 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
{BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=%w( i32 )%w%sr",
{BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%w=%w( s32 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
{BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
@ -157,11 +157,11 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
{BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
{BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=%w( i8 )%w%sw",
{BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%w=%w( s8 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
{BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=%w( i16 )%w%sw",
{BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%w=%w( s16 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
{BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=%w( i32 )%w%sw",
{BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%w=%w( s32 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
{BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
@ -218,13 +218,13 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
/* Generic signed load instructions (to register.) */
{BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( i8 * ) ( %sr %o16 )",
{BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( s8 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_SMEM},
{BPF_INSN_LDXSH, "ldxsh%W%dr , [ %sr %o16 ]", "%dr = * ( i16 * ) ( %sr %o16 )",
{BPF_INSN_LDXSH, "ldxsh%W%dr , [ %sr %o16 ]", "%dr = * ( s16 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_SMEM},
{BPF_INSN_LDXSW, "ldxsw%W%dr , [ %sr %o16 ]", "%dr = * ( i32 * ) ( %sr %o16 )",
{BPF_INSN_LDXSW, "ldxsw%W%dr , [ %sr %o16 ]", "%dr = * ( s32 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_SMEM},
{BPF_INSN_LDXSDW, "ldxsdw%W%dr , [ %sr %o16 ]","%dr = * ( i64 * ) ( %sr %o16 )",
{BPF_INSN_LDXSDW, "ldxsdw%W%dr , [ %sr %o16 ]","%dr = * ( s64 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_SMEM},
/* Generic store instructions (from register.) */