mirrors/binutils-gdb
1
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-23 18:14:13 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

S12Z: Fix disassembly of indexed OPR operands with zero index.

Browse Source 
gas/
	* testsuite/gas/s12z/jsr.s: New case.
	* testsuite/gas/s12z/jsr.d: New case.
opcodes/
	* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
	zero.
This commit is contained in:
John Darrington 2018-12-31 07:48:10 +00:00
parent 041be52673
commit 39f286cd58
5 changed files with 40 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2019-01-09 John Darrington <john@darrington.wattle.id.au>
* testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.

1
gas/testsuite/gas/s12z/jsr.d
View File

@ -31,3 +31,4 @@ Disassembly of section .text:
2a: ab f9 be 91 jsr 114321
2e: ab fe 07 82 jsr \[492134\]
32: 66
33: ab 40 jsr \(0,x\)

3
gas/testsuite/gas/s12z/jsr.s
View File

@ -1,5 +1,5 @@
jsr d2
jsr (2, y)
jsr (2,y)
jsr (+y)
jsr (-y)
jsr (y+)
@ -18,3 +18,4 @@
jsr 4021
jsr 114321
jsr [492134]
jsr (0,x)

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2019-01-09 John Darrington <john@darrington.wattle.id.au>
* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
zero.
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.

57
opcodes/s12z-dis.c
View File

@ -282,36 +282,33 @@ opr_emit_disassembly (const struct operand *opr,
struct memory_operand *mo = (struct memory_operand *) opr;
(*info->fprintf_func) (info->stream, "%c", mo->indirect ? '[' : '(');
if (mo->base_offset != 0)
{
(*info->fprintf_func) (info->stream, "%d", mo->base_offset);
}
else if (mo->n_regs > 0)
{
const char *fmt;
switch (mo->mutation)
{
case OPND_RM_PRE_DEC:
fmt = "-%s";
break;
case OPND_RM_PRE_INC:
fmt = "+%s";
break;
case OPND_RM_POST_DEC:
fmt = "%s-";
break;
case OPND_RM_POST_INC:
fmt = "%s+";
break;
case OPND_RM_NONE:
default:
fmt = "%s";
break;
}
(*info->fprintf_func) (info->stream, fmt,
registers[mo->regs[0]].name);
used_reg = 1;
}
const char *fmt;
assert (mo->mutation == OPND_RM_NONE || mo->n_regs == 1);
switch (mo->mutation)
{
case OPND_RM_PRE_DEC:
fmt = "-%s";
break;
case OPND_RM_PRE_INC:
fmt = "+%s";
break;
case OPND_RM_POST_DEC:
fmt = "%s-";
break;
case OPND_RM_POST_INC:
fmt = "%s+";
break;
case OPND_RM_NONE:
default:
if (mo->n_regs < 2)
(*info->fprintf_func) (info->stream, (mo->n_regs == 0) ? "%d" : "%d,", mo->base_offset);
fmt = "%s";
break;
}
if (mo->n_regs > 0)
(*info->fprintf_func) (info->stream, fmt,
registers[mo->regs[0]].name);
used_reg = 1;
if (mo->n_regs > used_reg)
{