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RISC-V: Disassemble x0 based addresses as 0.

Browse Source 
gas/
	* testsuite/gas/riscv/auipc-x0.d: New.
	* testsuite/gas/riscv/auipc-x0.s: New.

	opcodes/
	* riscv-dis.c (maybe_print_address): If base_reg is zero,
	then the hi_addr value is zero.
This commit is contained in:
Jim Wilson 2018-01-09 16:40:06 -08:00
parent d9ccd460fd
commit 35fd2b2bcf
5 changed files with 27 additions and 1 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2018-01-09 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above

12
gas/testsuite/gas/riscv/auipc-x0.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
#...
[ ]+40:[ ]+00000017[ ]+auipc[ ]+zero,0x0
[ ]+44:[ ]+00002003[ ]+lw[ ]+zero,0\(zero\) # 0 .*

4
gas/testsuite/gas/riscv/auipc-x0.s Normal file
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@ -0,0 +1,4 @@
target:
.skip 64
auipc x0, 0
lw x0, 0(x0)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-01-09 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.

2
opcodes/riscv-dis.c
View File

@ -101,7 +101,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
pd->print_addr = pd->hi_addr[base_reg] + offset;
pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
pd->hi_addr[base_reg] = -1;
}
else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)