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Arm/AArch64: Use a single set of Arm register set size defines
Both targets were using a mixture of defines and hardcoded values. Add a standard set in arch/arm.h and use throughout, ensuring that none of the existing sizes change. No functionality changes. gdb/ChangeLog: * aarch32-linux-nat.h (VFP_REGS_SIZE): Remove define. * aarch64-linux-nat.c (fetch_fpregs_from_thread) (store_fpregs_to_thread) (aarch64_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE. * arch/arm.h (IWMMXT_VEC_REGISTER_SIZE, ARM_CORE_REGS_SIZE) (ARM_FP_REGS_SIZE, ARM_VFP2_REGS_SIZE, ARM_VFP3_REGS_SIZE) (IWMMXT_REGS_SIZE): Add define. * arm-linux-nat.c (IWMMXT_REGS_SIZE): Remove define. (fetch_vfp_regs, store_vfp_regs) (arm_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE. * arm-tdep.c (arm_register_g_packet_guesses): Use new defines. gdb/gdbserver/ChangeLog: * linux-aarch32-low.c (arm_read_description, arm_regsets): Use new defines. * linux-arm-low.c (arm_read_description, arm_regsets): Likewise.
This commit is contained in:
Alan Hayward
parent
f0452268d6
commit
350fab5416
@ -1,3 +1,17 @@
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2019-07-04 Alan Hayward <alan.hayward@arm.com>
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* aarch32-linux-nat.h (VFP_REGS_SIZE): Remove define.
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* aarch64-linux-nat.c (fetch_fpregs_from_thread)
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(store_fpregs_to_thread)
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(aarch64_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
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* arch/arm.h (IWMMXT_VEC_REGISTER_SIZE, ARM_CORE_REGS_SIZE)
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(ARM_FP_REGS_SIZE, ARM_VFP2_REGS_SIZE, ARM_VFP3_REGS_SIZE)
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(IWMMXT_REGS_SIZE): Add define.
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* arm-linux-nat.c (IWMMXT_REGS_SIZE): Remove define.
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(fetch_vfp_regs, store_vfp_regs)
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(arm_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
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* arm-tdep.c (arm_register_g_packet_guesses): Use new defines.
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2019-07-04 Alan Hayward <alan.hayward@arm.com>
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* arch/arm-get-next-pcs.c (thumb_get_next_pcs_raw): Use ARM_
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@ -18,11 +18,6 @@
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#ifndef AARCH32_LINUX_NAT_H
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#define AARCH32_LINUX_NAT_H
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/* Fetch and store VFP Registers. The kernel object has space for 32
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64-bit registers, and the FPSCR. This is even when on a VFPv2 or
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VFPv3D16 target. */
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#define VFP_REGS_SIZE (32 * 8 + 4)
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void aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs,
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int arm_apcs_32);
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@ -30,6 +30,7 @@
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#include "aarch64-tdep.h"
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#include "aarch64-linux-tdep.h"
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#include "aarch32-linux-nat.h"
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#include "arch/arm.h"
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#include "nat/aarch64-linux.h"
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#include "nat/aarch64-linux-hw-point.h"
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#include "nat/aarch64-sve-linux-ptrace.h"
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@ -294,7 +295,7 @@ fetch_fpregs_from_thread (struct regcache *regcache)
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/* Make sure REGS can hold all VFP registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
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gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
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tid = regcache->ptid ().lwp ();
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@ -302,7 +303,7 @@ fetch_fpregs_from_thread (struct regcache *regcache)
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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{
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iovec.iov_len = VFP_REGS_SIZE;
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iovec.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret < 0)
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@ -341,14 +342,14 @@ store_fpregs_to_thread (const struct regcache *regcache)
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/* Make sure REGS can hold all VFP registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
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gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
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tid = regcache->ptid ().lwp ();
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iovec.iov_base = ®s;
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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{
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iovec.iov_len = VFP_REGS_SIZE;
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iovec.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret < 0)
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@ -638,13 +639,13 @@ const struct target_desc *
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aarch64_linux_nat_target::read_description ()
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{
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int ret, tid;
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gdb_byte regbuf[VFP_REGS_SIZE];
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gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
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struct iovec iovec;
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tid = inferior_ptid.lwp ();
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iovec.iov_base = regbuf;
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iovec.iov_len = VFP_REGS_SIZE;
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iovec.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret == 0)
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@ -99,6 +99,21 @@ enum arm_breakpoint_kinds
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/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
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#define ARM_FP_REGISTER_SIZE 12
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#define ARM_VFP_REGISTER_SIZE 8
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#define IWMMXT_VEC_REGISTER_SIZE 8
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/* Size of register sets. */
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/* r0-r12,sp,lr,pc,cpsr. */
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#define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE)
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/* f0-f8,fps. */
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#define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* d0-d15,fpscr. */
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#define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* d0-d31,fpscr. */
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#define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* wR0-wR15,fpscr. */
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#define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \
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+ 6 * ARM_INT_REGISTER_SIZE)
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/* Addresses for calling Thumb functions have the bit 0 set.
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Here are some macros to test, set, or clear bit 0 of addresses. */
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@ -276,8 +276,6 @@ store_regs (const struct regcache *regcache)
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/* Fetch all WMMX registers of the process and store into
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regcache. */
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#define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4)
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static void
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fetch_wmmx_regs (struct regcache *regcache)
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{
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@ -339,7 +337,7 @@ store_wmmx_regs (const struct regcache *regcache)
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static void
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fetch_vfp_regs (struct regcache *regcache)
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{
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gdb_byte regbuf[VFP_REGS_SIZE];
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gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
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int ret, tid;
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struct gdbarch *gdbarch = regcache->arch ();
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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@ -352,7 +350,7 @@ fetch_vfp_regs (struct regcache *regcache)
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struct iovec iov;
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iov.iov_base = regbuf;
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iov.iov_len = VFP_REGS_SIZE;
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iov.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
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}
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else
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@ -368,7 +366,7 @@ fetch_vfp_regs (struct regcache *regcache)
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static void
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store_vfp_regs (const struct regcache *regcache)
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{
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gdb_byte regbuf[VFP_REGS_SIZE];
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gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
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int ret, tid;
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struct gdbarch *gdbarch = regcache->arch ();
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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@ -381,7 +379,7 @@ store_vfp_regs (const struct regcache *regcache)
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struct iovec iov;
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iov.iov_base = regbuf;
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iov.iov_len = VFP_REGS_SIZE;
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iov.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
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}
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else
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@ -398,7 +396,7 @@ store_vfp_regs (const struct regcache *regcache)
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struct iovec iov;
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iov.iov_base = regbuf;
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iov.iov_len = VFP_REGS_SIZE;
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iov.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov);
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}
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else
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@ -574,7 +572,7 @@ arm_linux_nat_target::read_description ()
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registers. Support was added in 2.6.30. */
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pid = inferior_ptid.lwp ();
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errno = 0;
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buf = (char *) alloca (VFP_REGS_SIZE);
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buf = (char *) alloca (ARM_VFP3_REGS_SIZE);
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if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
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&& errno == EIO)
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result = NULL;
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@ -8781,25 +8781,16 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch)
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cater for remote targets whose register set layout is the
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same as the FPA layout. */
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register_remote_g_packet_guess (gdbarch,
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/* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
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(16 * ARM_INT_REGISTER_SIZE)
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+ (8 * ARM_FP_REGISTER_SIZE)
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+ (2 * ARM_INT_REGISTER_SIZE),
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ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE,
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tdesc_arm_with_m_fpa_layout);
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/* The regular M-profile layout. */
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register_remote_g_packet_guess (gdbarch,
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/* r0-r12,sp,lr,pc; xpsr */
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(16 * ARM_INT_REGISTER_SIZE)
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+ ARM_INT_REGISTER_SIZE,
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register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE,
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tdesc_arm_with_m);
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/* M-profile plus M4F VFP. */
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register_remote_g_packet_guess (gdbarch,
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/* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
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(16 * ARM_INT_REGISTER_SIZE)
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+ (16 * ARM_VFP_REGISTER_SIZE)
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+ (2 * ARM_INT_REGISTER_SIZE),
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ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE,
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tdesc_arm_with_m_vfp_d16);
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}
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@ -1,3 +1,9 @@
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2019-07-04 Alan Hayward <alan.hayward@arm.com>
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* linux-aarch32-low.c (arm_read_description, arm_regsets): Use new
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defines.
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* linux-arm-low.c (arm_read_description, arm_regsets): Likewise.
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2019-07-04 Alan Hayward <alan.hayward@arm.com>
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* configure.srv: Remove legacy xml.
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@ -143,10 +143,10 @@ arm_store_vfpregset (struct regcache *regcache, const void *buf)
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/* Register sets with using PTRACE_GETREGSET. */
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static struct regset_info aarch32_regsets[] = {
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 18 * 4,
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GENERAL_REGS,
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
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ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
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arm_fill_gregset, arm_store_gregset },
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, 32 * 8 + 4,
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, ARM_VFP3_REGS_SIZE,
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EXTENDED_REGS,
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arm_fill_vfpregset, arm_store_vfpregset },
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NULL_REGSET
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@ -876,7 +876,7 @@ arm_read_description (void)
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/* Now make sure that the kernel supports reading these
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registers. Support was added in 2.6.30. */
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errno = 0;
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buf = (char *) xmalloc (32 * 8 + 4);
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buf = (char *) xmalloc (ARM_VFP3_REGS_SIZE);
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if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
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&& errno == EIO)
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result = tdesc_arm;
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@ -973,14 +973,12 @@ arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno)
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/* Register sets without using PTRACE_GETREGSET. */
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static struct regset_info arm_regsets[] = {
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{ PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4,
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GENERAL_REGS,
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{ PTRACE_GETREGS, PTRACE_SETREGS, 0,
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ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
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arm_fill_gregset, arm_store_gregset },
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{ PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4,
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EXTENDED_REGS,
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{ PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS,
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arm_fill_wmmxregset, arm_store_wmmxregset },
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{ PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4,
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EXTENDED_REGS,
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{ PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS,
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arm_fill_vfpregset, arm_store_vfpregset },
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NULL_REGSET
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};
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