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revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"
This reverts commit 384f368958, which
broke i386-gen's emitting of diagnostics. As a replacement to address
the original issue of newer gcc no longer splicing lines when dropping
the line continuation backslashes, switch to using + as the line
continuation character, doing the line splicing in i386-gen.
This commit is contained in:
Jan Beulich
parent
246cb4b5a1
commit
33b6a20af3
@ -559,7 +559,7 @@ $(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
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@echo $@
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$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl i386-opc.h
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$(CPP) -P $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) - \
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$(CPP) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) - \
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< $(srcdir)/i386-opc.tbl \
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| ./i386-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir)
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@ -1534,7 +1534,7 @@ $(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
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@echo $@
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$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl i386-opc.h
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$(CPP) -P $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) - \
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$(CPP) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) - \
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< $(srcdir)/i386-opc.tbl \
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| ./i386-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir)
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@ -1764,17 +1764,36 @@ process_i386_opcodes (FILE *table)
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if (fgets (buf, sizeof (buf), fp) == NULL)
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break;
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lineno++;
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p = remove_leading_whitespaces (buf);
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/* Skip comments. */
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str = strstr (p, "//");
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if (str != NULL)
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str[0] = '\0';
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for ( ; ; )
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{
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lineno++;
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/* Remove trailing white spaces. */
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remove_trailing_whitespaces (p);
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/* Skip comments. */
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str = strstr (p, "//");
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if (str != NULL)
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{
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str[0] = '\0';
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remove_trailing_whitespaces (p);
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break;
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}
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/* Look for line continuation character. */
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remove_trailing_whitespaces (p);
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j = strlen (buf);
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if (!j || buf[j - 1] != '+')
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break;
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if (j >= sizeof (buf) - 1)
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fail (_("%s: %d: (continued) line too long\n"), filename, lineno);
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if (fgets (buf + j - 1, sizeof (buf) - j + 1, fp) == NULL)
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{
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fprintf (stderr, "%s: Line continuation on last line?\n",
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filename);
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break;
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}
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}
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switch (p[0])
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{
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@ -22,6 +22,11 @@
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#include "i386-opc.h"
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#undef None
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// When necessary lines can be split in a non-standard way, by placing a
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// trailing + on a to-be-continued line. This is intended mainly for non-insn
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// templates. Insn templates are better kept all on one line to make grep and
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// alike produce useful results.
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#define Amd64 ISA64=AMD64
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#define Intel64 ISA64=INTEL64
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#define Intel64Only ISA64=INTEL64ONLY
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@ -455,7 +460,7 @@ enter, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64,
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leave, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
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leave, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {}
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<cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, \
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<cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
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s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
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// Conditional jumps.
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@ -871,9 +876,9 @@ rex.wrxb, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Is
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// Pseudo prefixes (base_opcode == PSEUDO_PREFIX)
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<pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, \
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load:Load:0, store:Store:0, \
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vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, \
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<pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, +
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load:Load:0, store:Store:0, +
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vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, +
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rex:REX:Cpu64, nooptimize:NoOptimize:0>
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{<pseudopfx>}, PSEUDO_PREFIX, Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
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@ -962,13 +967,13 @@ pause, 0xf390, None, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
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// MMX/SSE2 instructions.
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<mmx:cpu:pfx:attr:shimm:reg:mem, \
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$avx:CpuAVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=2|VexW0|SSE2AVX:RegXMM:Xmmword, \
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$sse:CpuSSE2:66:::RegXMM:Xmmword, \
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<mmx:cpu:pfx:attr:shimm:reg:mem, +
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$avx:CpuAVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=2|VexW0|SSE2AVX:RegXMM:Xmmword, +
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$sse:CpuSSE2:66:::RegXMM:Xmmword, +
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$mmx:CpuMMX::NoRex64::RegMMX:Qword>
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<sse2:cpu:attr:scal:vvvv:shimm, \
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$avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|VexVVVV=2|VexW0|SSE2AVX, \
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<sse2:cpu:attr:scal:vvvv:shimm, +
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$avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|VexVVVV=2|VexW0|SSE2AVX, +
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$sse:CpuSSE2::NoRex64::>
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emms, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
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@ -1052,8 +1057,8 @@ pxor<mmx>, 0x<mmx:pfx>0fef, None, <mmx:cpu>, Modrm|<mmx:attr>|C|No_bSuf|No_wSuf|
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// SSE instructions.
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<sse:cpu:attr:scal:vvvv, \
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$avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, \
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<sse:cpu:attr:scal:vvvv, +
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$avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, +
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$sse:CpuSSE::IgnoreSize:>
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<sse_frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, ord:7:C>
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@ -1309,9 +1314,9 @@ invpcid, 0x660f3882, None, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qS
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// SSSE3 instructions.
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<ssse3:cpu:pfx:attr:vvvv:reg:mem, \
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$avx:CpuAVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, \
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$sse:CpuSSSE3:66:::RegXMM:Xmmword, \
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<ssse3:cpu:pfx:attr:vvvv:reg:mem, +
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$avx:CpuAVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, +
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$sse:CpuSSSE3:66:::RegXMM:Xmmword, +
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$mmx:CpuSSSE3::NoRex64::RegMMX:Qword>
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phaddw<ssse3>, 0x<ssse3:pfx>0f3801, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> }
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@ -1469,14 +1474,14 @@ gf2p8mulb<gfni>, 0x660f38cf, None, <gfni:cpu>CpuGFNI, Modrm|<gfni:w0>|No_bSuf|No
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// AVX instructions.
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<avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, \
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unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, \
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nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, \
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nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, \
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neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, \
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true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, \
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unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, \
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nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, \
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<avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, +
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unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, +
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nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, +
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nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, +
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neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, +
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true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, +
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unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, +
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nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, +
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true_us:1f:C>
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vaddpd, 0x6658, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
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