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gas/
2005-07-05 Jan Beulich <jbeulich@novell.com> * config/tc-i386.h (CpuSVME): New. (CpuUnknownFlags): Include CpuSVME. * config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron as alias of sledgehammer. (md_assemble): Include invlpga in the check for insns with two source operands. (process_operands): Include SVME insns in the check for ignored segment overrides. Adjust diagnostic. (i386_index_check): Special-case SVME insns with memory operands. gas/testsuite/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * gas/i386/svme.d: New. * gas/i386/svme.s: New. * gas/i386/svme64.d: New. * gas/i386/i386.exp: Run new tests. include/opcode/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): Add new insns. opcodes/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * i386-dis.c (SVME_Fixup): New. (grps): Use it for the lidt entry. (PNI_Fixup): Call OP_M rather than OP_E. (INVLPG_Fixup): Likewise.
This commit is contained in:
Jan Beulich
parent
b35d266b30
commit
3012383869
@ -1,3 +1,15 @@
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2005-07-05 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.h (CpuSVME): New.
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(CpuUnknownFlags): Include CpuSVME.
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* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
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as alias of sledgehammer.
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(md_assemble): Include invlpga in the check for insns with two source
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operands.
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(process_operands): Include SVME insns in the check for ignored
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segment overrides. Adjust diagnostic.
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(i386_index_check): Special-case SVME insns with memory operands.
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2005-07-04 Khem Raj <kraj@mvista.com>
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Nick Clifton <nickc@redhat.com>
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@ -429,12 +429,15 @@ static const arch_entry cpu_arch[] = {
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{"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
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{"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
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{"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
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{"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
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{".mmx", CpuMMX },
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{".sse", CpuMMX|CpuMMX2|CpuSSE },
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{".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
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{".3dnow", CpuMMX|Cpu3dnow },
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{".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
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{".padlock", CpuPadLock },
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{".pacifica", CpuSVME },
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{".svme", CpuSVME },
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{NULL, 0 }
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};
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@ -1403,6 +1406,7 @@ md_assemble (line)
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have two immediate operands. */
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if (intel_syntax && i.operands > 1
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&& (strcmp (mnemonic, "bound") != 0)
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&& (strcmp (mnemonic, "invlpga") != 0)
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&& !((i.types[0] & Imm) && (i.types[1] & Imm)))
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swap_operands ();
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@ -2846,8 +2850,10 @@ process_operands ()
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default_seg = &ds;
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}
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if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
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as_warn (_("segment override on `lea' is ineffectual"));
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if ((i.tm.base_opcode == 0x8d /* lea */
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|| (i.tm.cpu_flags & CpuSVME))
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&& i.seg[0] && !quiet_warnings)
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as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
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/* If a segment was explicitly specified, and the specified segment
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is not the default, use an opcode prefix to select it. If we
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@ -4194,7 +4200,30 @@ i386_index_check (operand_string)
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tryprefix:
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#endif
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ok = 1;
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if (flag_code == CODE_64BIT)
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if ((current_templates->start->cpu_flags & CpuSVME)
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&& current_templates->end[-1].operand_types[0] == AnyMem)
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{
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/* Memory operands of SVME insns are special in that they only allow
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rAX as their memory address and ignore any segment override. */
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unsigned RegXX;
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/* SKINIT is even more restrictive: it always requires EAX. */
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if (strcmp (current_templates->start->name, "skinit") == 0)
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RegXX = Reg32;
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else if (flag_code == CODE_64BIT)
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RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
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else
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RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
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? Reg16
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: Reg32;
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if (!i.base_reg
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|| !(i.base_reg->reg_type & Acc)
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|| !(i.base_reg->reg_type & RegXX)
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|| i.index_reg
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|| (i.types[0] & Disp))
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ok = 0;
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}
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else if (flag_code == CODE_64BIT)
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{
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unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
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@ -184,13 +184,16 @@ typedef struct
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#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
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#define CpuPNI 0x20000 /* Prescott New Instructions required */
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#define CpuPadLock 0x40000 /* VIA PadLock required */
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#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock)
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -1,3 +1,10 @@
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2005-07-05 Jan Beulich <jbeulich@novell.com>
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* gas/i386/svme.d: New.
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* gas/i386/svme.s: New.
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* gas/i386/svme64.d: New.
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* gas/i386/i386.exp: Run new tests.
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2005-07-04 Zack Weinberg <zack@codesourcery.com>
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* lib/gas-defs.exp (run_dump_tests): New proc.
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@ -74,6 +74,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "padlock"
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run_dump_test "crx"
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run_list_test "cr-err" ""
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run_dump_test "svme"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -128,6 +129,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_list_test "x86-64-segment" "-al"
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run_list_test "x86-64-inval-seg" "-al"
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run_dump_test "x86-64-branch"
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run_dump_test "svme64"
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# For ELF targets verify that @unwind works.
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if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"]
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29
gas/testsuite/gas/i386/svme.d
Normal file
29
gas/testsuite/gas/i386/svme.d
Normal file
@ -0,0 +1,29 @@
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#objdump: -dw
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#name: 32-bit SVME
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.*: +file format .*
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Disassembly of section .text:
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0+000 <common>:
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[ ]*[0-9a-f]+:[ ]+0f 01 dd[ ]+clgi[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 dc[ ]+stgi[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d9[ ]+vmmcall[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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[0-9a-f]+ <att32>:
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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[0-9a-f]+ <intel32>:
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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#pass
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36
gas/testsuite/gas/i386/svme.s
Normal file
36
gas/testsuite/gas/i386/svme.s
Normal file
@ -0,0 +1,36 @@
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.text
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common:
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clgi
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invlpga
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skinit
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stgi
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vmload
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vmmcall
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vmrun
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vmsave
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.macro do_args arg1, arg2
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invlpga \arg1, \arg2
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vmload \arg1
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vmrun \arg1
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vmsave \arg1
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.endm
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.ifdef __amd64__
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att64:
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do_args (%rax), %ecx
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.endif
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att32:
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skinit (%eax)
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do_args (%eax), %ecx
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.intel_syntax noprefix
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.ifdef __amd64__
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intel64:
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do_args [rax], ecx
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.endif
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intel32:
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skinit [eax]
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do_args [eax], ecx
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.p2align 4,0
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41
gas/testsuite/gas/i386/svme64.d
Normal file
41
gas/testsuite/gas/i386/svme64.d
Normal file
@ -0,0 +1,41 @@
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#as: --defsym __amd64__=1
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#objdump: -dw
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#name: 64-bit SVME
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#source: svme.s
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.*: +file format .*
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Disassembly of section .text:
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0+000 <common>:
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[ ]*[0-9a-f]+:[ ]+0f 01 dd[ ]+clgi[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 dc[ ]+stgi[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d9[ ]+vmmcall[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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[0-9a-f]+ <att64>:
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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[0-9a-f]+ <att32>:
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+67 0f 01 df[ ]+(addr32 )?invlpga[ ]*\(%eax\),[ ]*%ecx
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[ ]*[0-9a-f]+:[ ]+67 0f 01 da[ ]+(addr32 )?vmload[ ]*\(%eax\)
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[ ]*[0-9a-f]+:[ ]+67 0f 01 d8[ ]+(addr32 )?vmrun[ ]*\(%eax\)
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[ ]*[0-9a-f]+:[ ]+67 0f 01 db[ ]+(addr32 )?vmsave[ ]*\(%eax\)
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[0-9a-f]+ <intel64>:
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[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]*
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[0-9a-f]+ <intel32>:
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[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]*
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[ ]*[0-9a-f]+:[ ]+67 0f 01 df[ ]+(addr32 )?invlpga[ ]*\(%eax\),[ ]*%ecx
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[ ]*[0-9a-f]+:[ ]+67 0f 01 da[ ]+(addr32 )?vmload[ ]*\(%eax\)
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[ ]*[0-9a-f]+:[ ]+67 0f 01 d8[ ]+(addr32 )?vmrun[ ]*\(%eax\)
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[ ]*[0-9a-f]+:[ ]+67 0f 01 db[ ]+(addr32 )?vmsave[ ]*\(%eax\)
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#pass
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@ -1,3 +1,7 @@
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2005-07-05 Jan Beulich <jbeulich@novell.com>
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* i386.h (i386_optab): Add new insns.
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2005-07-01 Nick Clifton <nickc@redhat.com>
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* sparc.h: Add typedefs to structure declarations.
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@ -1383,6 +1383,22 @@ static const template i386_optab[] =
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{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} },
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{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} },
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/* AMD Pacifica additions. */
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{"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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/* Need to ensure only "invlpga ...,%ecx" is accepted. */
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{"invlpga", 2, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { AnyMem, Reg32, 0 } },
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{"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } },
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{"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"vmload", 1, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } },
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{"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"vmrun", 1, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } },
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{"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } },
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{"vmsave", 1, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } },
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/* VIA PadLock extensions. */
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{"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
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{"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
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@ -1,3 +1,10 @@
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2005-07-05 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (SVME_Fixup): New.
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(grps): Use it for the lidt entry.
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(PNI_Fixup): Call OP_M rather than OP_E.
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(INVLPG_Fixup): Likewise.
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2005-07-04 H.J. Lu <hongjiu.lu@intel.com>
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* tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
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@ -95,6 +95,7 @@ static void OP_3DNowSuffix (int, int);
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static void OP_SIMD_Suffix (int, int);
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static void SIMD_Fixup (int, int);
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static void PNI_Fixup (int, int);
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static void SVME_Fixup (int, int);
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static void INVLPG_Fixup (int, int);
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static void BadOp (void);
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static void SEG_Fixup (int, int);
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@ -1374,7 +1375,7 @@ static const struct dis386 grps[][8] = {
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{ "sgdtIQ", M, XX, XX },
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{ "sidtIQ", PNI_Fixup, 0, XX, XX },
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{ "lgdt{Q|Q||}", M, XX, XX },
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{ "lidt{Q|Q||}", M, XX, XX },
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{ "lidt{Q|Q||}", SVME_Fixup, 0, XX, XX },
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{ "smswQ", Ev, XX, XX },
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{ "(bad)", XX, XX, XX },
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{ "lmsw", Ew, XX, XX },
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@ -4445,7 +4446,77 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
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codep++;
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}
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else
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OP_E (0, sizeflag);
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OP_M (0, sizeflag);
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}
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static void
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SVME_Fixup (int bytemode, int sizeflag)
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{
|
||||
const char *alt;
|
||||
char *p;
|
||||
|
||||
switch (*codep)
|
||||
{
|
||||
case 0xd8:
|
||||
alt = "vmrun";
|
||||
break;
|
||||
case 0xd9:
|
||||
alt = "vmmcall";
|
||||
break;
|
||||
case 0xda:
|
||||
alt = "vmload";
|
||||
break;
|
||||
case 0xdb:
|
||||
alt = "vmsave";
|
||||
break;
|
||||
case 0xdc:
|
||||
alt = "stgi";
|
||||
break;
|
||||
case 0xdd:
|
||||
alt = "clgi";
|
||||
break;
|
||||
case 0xde:
|
||||
alt = "skinit";
|
||||
break;
|
||||
case 0xdf:
|
||||
alt = "invlpga";
|
||||
break;
|
||||
default:
|
||||
OP_M (bytemode, sizeflag);
|
||||
return;
|
||||
}
|
||||
/* Override "lidt". */
|
||||
p = obuf + strlen (obuf) - 4;
|
||||
/* We might have a suffix. */
|
||||
if (*p == 'i')
|
||||
--p;
|
||||
strcpy (p, alt);
|
||||
if (!(prefixes & PREFIX_ADDR))
|
||||
{
|
||||
++codep;
|
||||
return;
|
||||
}
|
||||
used_prefixes |= PREFIX_ADDR;
|
||||
switch (*codep++)
|
||||
{
|
||||
case 0xdf:
|
||||
strcpy (op2out, names32[1]);
|
||||
two_source_ops = 1;
|
||||
/* Fall through. */
|
||||
case 0xd8:
|
||||
case 0xda:
|
||||
case 0xdb:
|
||||
*obufp++ = open_char;
|
||||
if (mode_64bit || (sizeflag & AFLAG))
|
||||
alt = names32[0];
|
||||
else
|
||||
alt = names16[0];
|
||||
strcpy (obufp, alt);
|
||||
obufp += strlen (alt);
|
||||
*obufp++ = close_char;
|
||||
*obufp = '\0';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
@ -4462,7 +4533,7 @@ INVLPG_Fixup (int bytemode, int sizeflag)
|
||||
alt = "rdtscp";
|
||||
break;
|
||||
default:
|
||||
OP_E (bytemode, sizeflag);
|
||||
OP_M (bytemode, sizeflag);
|
||||
return;
|
||||
}
|
||||
/* Override "invlpg". */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user