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Arm64: simplify Crypto arch extension handling
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
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Jan Beulich
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d4340f89ec
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2dc4b12fcd
@ -1,3 +1,8 @@
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2019-12-05 Jan Beulich <jbeulich@suse.com>
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* config/tc-aarch64.c (aarch64_features): Drop redundant AES and
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SHA2 flags from "crypto" entry.
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2019-12-05 Jan Beulich <jbeulich@suse.com>
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* config/tc-aarch64.c (aarch64_features): Make SHA2 a prereq of
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@ -8990,9 +8990,7 @@ struct aarch64_option_cpu_value_table
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static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
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AARCH64_ARCH_NONE},
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{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
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| AARCH64_FEATURE_AES
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| AARCH64_FEATURE_SHA2, 0),
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{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
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AARCH64_ARCH_NONE},
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@ -1,3 +1,8 @@
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2019-12-05 Jan Beulich <jbeulich@suse.com>
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* opcode/aarch64.h (AARCH64_FEATURE_CRYPTO): Expand to the
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combination of AES and SHA2.
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2019-11-25 Alan Modra <amodra@gmail.com>
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* coff/ti.h (GET_SCNHDR_SIZE, PUT_SCNHDR_SIZE, GET_SCN_SCNLEN),
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@ -45,7 +45,6 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
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#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
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#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
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#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
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#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
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#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
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#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
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@ -103,6 +102,9 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_SVE2_SM4 0x000000200
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#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
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/* Crypto instructions are the combination of AES and SHA2. */
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#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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AARCH64_FEATURE_FP \
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@ -1,3 +1,9 @@
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2019-12-05 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_feature_crypto,
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aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
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CRYPTO_V8_2_INSN): Delete.
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2019-12-05 Alan Modra <amodra@gmail.com>
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PR 25249
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@ -2324,9 +2324,6 @@ static const aarch64_feature_set aarch64_feature_fp =
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AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_simd =
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AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
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static const aarch64_feature_set aarch64_feature_crypto =
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AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_AES
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| AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_crc =
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AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
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static const aarch64_feature_set aarch64_feature_lse =
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@ -2363,9 +2360,6 @@ static const aarch64_feature_set aarch64_feature_aes =
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AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
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static const aarch64_feature_set aarch64_feature_v8_4 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
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static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO
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| AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_sm4 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4
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| AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
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@ -2423,7 +2417,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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#define CORE &aarch64_feature_v8
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#define FP &aarch64_feature_fp
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#define SIMD &aarch64_feature_simd
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#define CRYPTO &aarch64_feature_crypto
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#define CRC &aarch64_feature_crc
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#define LSE &aarch64_feature_lse
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#define LOR &aarch64_feature_lor
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@ -2443,7 +2436,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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#define ARMV8_4 &aarch64_feature_v8_4
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#define SHA3 &aarch64_feature_sha3
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#define SM4 &aarch64_feature_sm4
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#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
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#define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
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#define DOTPROD &aarch64_feature_dotprod
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#define ARMV8_5 &aarch64_feature_v8_5
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@ -2476,8 +2468,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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{ NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
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{ NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER }
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#define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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@ -2510,8 +2500,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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{ NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
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#define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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