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aarch64: Add new AT system instructions.

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This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
This commit is contained in:
Srinath Parvathaneni 2023-11-16 14:24:27 +00:00 committed by srinath
parent 311276f10c
commit 281fda33bc
5 changed files with 24 additions and 1 deletions
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3
gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
View File

@ -24,3 +24,6 @@
.*: Error: selected processor does not support system register name 'pfar_el1'
.*: Error: selected processor does not support system register name 'pfar_el2'
.*: Error: selected processor does not support system register name 'pfar_el12'
.*: Error: selected processor does not support system register name 's1e1a'
.*: Error: selected processor does not support system register name 's1e2a'
.*: Error: selected processor does not support system register name 's1e3a'

3
gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
View File

@ -31,3 +31,6 @@ Disassembly of section \.text:
.*: d51860a0 msr pfar_el1, x0
.*: d51c60a0 msr pfar_el2, x0
.*: d51d60a0 msr pfar_el12, x0
.*: d5087941 at s1e1a, x1
.*: d50c7943 at s1e2a, x3
.*: d50e7945 at s1e3a, x5

5
gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
View File

@ -27,3 +27,8 @@
msr PFAR_EL1, x0
msr PFAR_EL2, x0
msr PFAR_EL12, x0
/* AT. */
at s1e1a, x1
at s1e2a, x3
at s1e3a, x5

5
include/opcode/aarch64.h
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@ -183,6 +183,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FGT2,
/* Physical Fault Address. */
AARCH64_FEATURE_PFAR,
/* Address Translate Stage 1. */
AARCH64_FEATURE_ATS1A,
AARCH64_NUM_FEATURES
};
@ -245,7 +247,8 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, RASv2) \
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
| AARCH64_FEATBIT (X, PFAR))
| AARCH64_FEATBIT (X, PFAR) \
| AARCH64_FEATBIT (X, ATS1A))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \

9
opcodes/aarch64-opc.c
View File

@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
{ "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
{ "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};
@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, THE))
return true;
if ((reg_value == CPENS (0, C7, C9, 2)
|| reg_value == CPENS (4, C7, C9, 2)
|| reg_value == CPENS (6, C7, C9, 2))
&& AARCH64_CPU_HAS_FEATURE (features, ATS1A))
return true;
return false;
}