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cr16 disassembly error of disp20 fields
When looking at the UB errors, I noticed that cbitb_test.d disassembly wasn't reproducing the input assembly. That turned out to be an error in make_argument case arg_cr. This fixes that and makes some general tidies. opcodes/ * cr16-dis.c: Formatting. (parameter): Delete struct typedef. Use dwordU instead throughout file. (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb and tbitb. (make_argument <arg_cr>): Extract 20-bit field not 16-bit. gas/ * testsuite/gas/cr16/cbitb_test.d: Update expected output. * testsuite/gas/cr16/cbitw_test.d: Likewise. * testsuite/gas/cr16/sbitb_test.d: Likewise. * testsuite/gas/cr16/sbitw_test.d: Likewise. * testsuite/gas/cr16/storb_test.d: Likewise. * testsuite/gas/cr16/storw_test.d: Likewise. * testsuite/gas/cr16/tbitb_test.d: Likewise. * testsuite/gas/cr16/tbitw_test.d: Likewise.
This commit is contained in:
Alan Modra
parent
c930281005
commit
2781f857e6
@ -1,3 +1,14 @@
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2020-08-30 Alan Modra <amodra@gmail.com>
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* testsuite/gas/cr16/cbitb_test.d: Update expected output.
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* testsuite/gas/cr16/cbitw_test.d: Likewise.
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* testsuite/gas/cr16/sbitb_test.d: Likewise.
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* testsuite/gas/cr16/sbitw_test.d: Likewise.
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* testsuite/gas/cr16/storb_test.d: Likewise.
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* testsuite/gas/cr16/storw_test.d: Likewise.
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* testsuite/gas/cr16/tbitb_test.d: Likewise.
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* testsuite/gas/cr16/tbitw_test.d: Likewise.
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2020-08-30 Alan Modra <amodra@gmail.com>
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PR26437
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@ -59,17 +59,17 @@ Disassembly of section .text:
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b0: 3d 6b ff 0f cbitb \$0x3,0xfff:m\(r13\)
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b4: 3d 6b ff ff cbitb \$0x3,0xffff:m\(r13\)
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b8: 3c 6b 43 23 cbitb \$0x3,0x2343:m\(r12\)
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bc: 10 00 32 41 cbitb \$0x3,0x2345:l\(r2\)
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bc: 10 00 32 41 cbitb \$0x3,0x12345:l\(r2\)
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c0: 45 23
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c2: 10 00 38 44 cbitb \$0x3,0xabcd:l\(r8\)
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c2: 10 00 38 44 cbitb \$0x3,0x4abcd:l\(r8\)
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c6: cd ab
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c8: 10 00 3d 5f cbitb \$0x3,0xfabcd:l\(r13\)
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cc: cd ab
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ce: 10 00 38 4f cbitb \$0x3,0xabcd:l\(r8\)
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ce: 10 00 38 4f cbitb \$0x3,0xfabcd:l\(r8\)
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d2: cd ab
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d4: 10 00 39 4f cbitb \$0x3,0xabcd:l\(r9\)
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d4: 10 00 39 4f cbitb \$0x3,0xfabcd:l\(r9\)
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d8: cd ab
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da: 10 00 39 44 cbitb \$0x3,0xabcd:l\(r9\)
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da: 10 00 39 44 cbitb \$0x3,0x4abcd:l\(r9\)
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de: cd ab
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e0: 31 6a cbitb \$0x3,0x0:s\(r2,r1\)
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e2: 51 6b 01 00 cbitb \$0x5,0x1:m\(r2,r1\)
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@ -95,17 +95,17 @@ Disassembly of section .text:
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136: 3d 69 ff 0f cbitw \$0x3:s,0xfff:m\(r13\)
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13a: 3d 69 ff ff cbitw \$0x3:s,0xffff:m\(r13\)
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13e: 3c 69 43 23 cbitw \$0x3:s,0x2343:m\(r12\)
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142: 11 00 32 41 cbitw \$0x3:s,0x2345:l\(r2\)
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142: 11 00 32 41 cbitw \$0x3:s,0x12345:l\(r2\)
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146: 45 23
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148: 11 00 38 44 cbitw \$0x3:s,0xabcd:l\(r8\)
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148: 11 00 38 44 cbitw \$0x3:s,0x4abcd:l\(r8\)
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14c: cd ab
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14e: 11 00 3d 5f cbitw \$0x3:s,0xfabcd:l\(r13\)
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152: cd ab
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154: 11 00 38 4f cbitw \$0x3:s,0xabcd:l\(r8\)
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154: 11 00 38 4f cbitw \$0x3:s,0xfabcd:l\(r8\)
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158: cd ab
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15a: 11 00 39 4f cbitw \$0x3:s,0xabcd:l\(r9\)
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15a: 11 00 39 4f cbitw \$0x3:s,0xfabcd:l\(r9\)
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15e: cd ab
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160: 11 00 39 44 cbitw \$0x3:s,0xabcd:l\(r9\)
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160: 11 00 39 44 cbitw \$0x3:s,0x4abcd:l\(r9\)
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164: cd ab
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166: 11 00 f2 40 cbitw \$0xf:s,0x0:l\(r2\)
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16a: 00 00
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@ -123,17 +123,17 @@ Disassembly of section .text:
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190: dd 69 ff 0f cbitw \$0xd:s,0xfff:m\(r13\)
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194: dd 69 ff ff cbitw \$0xd:s,0xffff:m\(r13\)
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198: dc 69 43 23 cbitw \$0xd:s,0x2343:m\(r12\)
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19c: 11 00 d2 41 cbitw \$0xd:s,0x2345:l\(r2\)
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19c: 11 00 d2 41 cbitw \$0xd:s,0x12345:l\(r2\)
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1a0: 45 23
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1a2: 11 00 d8 44 cbitw \$0xd:s,0xabcd:l\(r8\)
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1a2: 11 00 d8 44 cbitw \$0xd:s,0x4abcd:l\(r8\)
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1a6: cd ab
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1a8: 11 00 dd 5f cbitw \$0xd:s,0xfabcd:l\(r13\)
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1ac: cd ab
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1ae: 11 00 d8 4f cbitw \$0xd:s,0xabcd:l\(r8\)
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1ae: 11 00 d8 4f cbitw \$0xd:s,0xfabcd:l\(r8\)
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1b2: cd ab
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1b4: 11 00 d9 4f cbitw \$0xd:s,0xabcd:l\(r9\)
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1b4: 11 00 d9 4f cbitw \$0xd:s,0xfabcd:l\(r9\)
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1b8: cd ab
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1ba: 11 00 d9 44 cbitw \$0xd:s,0xabcd:l\(r9\)
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1ba: 11 00 d9 44 cbitw \$0xd:s,0x4abcd:l\(r9\)
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1be: cd ab
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1c0: 31 6e cbitw \$0x3:s,0x0:s\(r2,r1\)
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1c2: 51 69 01 00 cbitw \$0x5:s,0x1:m\(r2,r1\)
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@ -59,17 +59,17 @@ Disassembly of section .text:
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b0: 3d 73 ff 0f sbitb \$0x3,0xfff:m\(r13\)
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b4: 3d 73 ff ff sbitb \$0x3,0xffff:m\(r13\)
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b8: 3c 73 43 23 sbitb \$0x3,0x2343:m\(r12\)
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bc: 10 00 32 81 sbitb \$0x3,0x2345:l\(r2\)
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bc: 10 00 32 81 sbitb \$0x3,0x12345:l\(r2\)
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c0: 45 23
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c2: 10 00 38 84 sbitb \$0x3,0xabcd:l\(r8\)
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c2: 10 00 38 84 sbitb \$0x3,0x4abcd:l\(r8\)
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c6: cd ab
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c8: 10 00 3d 9f sbitb \$0x3,0xfabcd:l\(r13\)
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cc: cd ab
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ce: 10 00 38 8f sbitb \$0x3,0xabcd:l\(r8\)
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ce: 10 00 38 8f sbitb \$0x3,0xfabcd:l\(r8\)
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d2: cd ab
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d4: 10 00 39 8f sbitb \$0x3,0xabcd:l\(r9\)
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d4: 10 00 39 8f sbitb \$0x3,0xfabcd:l\(r9\)
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d8: cd ab
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da: 10 00 39 84 sbitb \$0x3,0xabcd:l\(r9\)
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da: 10 00 39 84 sbitb \$0x3,0x4abcd:l\(r9\)
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de: cd ab
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e0: 31 72 sbitb \$0x3,0x0:s\(r2,r1\)
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e2: 51 73 01 00 sbitb \$0x5,0x1:m\(r2,r1\)
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@ -95,17 +95,17 @@ Disassembly of section .text:
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136: 3d 71 ff 0f sbitw \$0x3:s,0xfff:m\(r13\)
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13a: 3d 71 ff ff sbitw \$0x3:s,0xffff:m\(r13\)
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13e: 3c 71 43 23 sbitw \$0x3:s,0x2343:m\(r12\)
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142: 11 00 32 81 sbitw \$0x3:s,0x2345:l\(r2\)
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142: 11 00 32 81 sbitw \$0x3:s,0x12345:l\(r2\)
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146: 45 23
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148: 11 00 38 84 sbitw \$0x3:s,0xabcd:l\(r8\)
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148: 11 00 38 84 sbitw \$0x3:s,0x4abcd:l\(r8\)
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14c: cd ab
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14e: 11 00 3d 9f sbitw \$0x3:s,0xfabcd:l\(r13\)
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152: cd ab
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154: 11 00 38 8f sbitw \$0x3:s,0xabcd:l\(r8\)
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154: 11 00 38 8f sbitw \$0x3:s,0xfabcd:l\(r8\)
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158: cd ab
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15a: 11 00 39 8f sbitw \$0x3:s,0xabcd:l\(r9\)
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15a: 11 00 39 8f sbitw \$0x3:s,0xfabcd:l\(r9\)
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15e: cd ab
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160: 11 00 39 84 sbitw \$0x3:s,0xabcd:l\(r9\)
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160: 11 00 39 84 sbitw \$0x3:s,0x4abcd:l\(r9\)
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164: cd ab
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166: 11 00 f2 80 sbitw \$0xf:s,0x0:l\(r2\)
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16a: 00 00
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@ -123,17 +123,17 @@ Disassembly of section .text:
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190: dd 71 ff 0f sbitw \$0xd:s,0xfff:m\(r13\)
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194: dd 71 ff ff sbitw \$0xd:s,0xffff:m\(r13\)
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198: dc 71 43 23 sbitw \$0xd:s,0x2343:m\(r12\)
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19c: 11 00 d2 81 sbitw \$0xd:s,0x2345:l\(r2\)
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19c: 11 00 d2 81 sbitw \$0xd:s,0x12345:l\(r2\)
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1a0: 45 23
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1a2: 11 00 d8 84 sbitw \$0xd:s,0xabcd:l\(r8\)
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1a2: 11 00 d8 84 sbitw \$0xd:s,0x4abcd:l\(r8\)
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1a6: cd ab
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1a8: 11 00 dd 9f sbitw \$0xd:s,0xfabcd:l\(r13\)
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1ac: cd ab
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1ae: 11 00 d8 8f sbitw \$0xd:s,0xabcd:l\(r8\)
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1ae: 11 00 d8 8f sbitw \$0xd:s,0xfabcd:l\(r8\)
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1b2: cd ab
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1b4: 11 00 d9 8f sbitw \$0xd:s,0xabcd:l\(r9\)
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1b4: 11 00 d9 8f sbitw \$0xd:s,0xfabcd:l\(r9\)
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1b8: cd ab
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1ba: 11 00 d9 84 sbitw \$0xd:s,0xabcd:l\(r9\)
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1ba: 11 00 d9 84 sbitw \$0xd:s,0x4abcd:l\(r9\)
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1be: cd ab
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1c0: 31 76 sbitw \$0x3:s,0x0:s\(r2,r1\)
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1c2: 51 71 01 00 sbitw \$0x5:s,0x1:m\(r2,r1\)
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@ -130,17 +130,17 @@ Disassembly of section .text:
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198: 3d 83 ff 0f storb \$0x3:s,0xfff:m\(r13\)
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19c: 3d 83 ff ff storb \$0x3:s,0xffff:m\(r13\)
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1a0: 3c 83 43 23 storb \$0x3:s,0x2343:m\(r12\)
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1a4: 12 00 32 01 storb \$0x3:s,0x2345:l\(r2\)
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1a4: 12 00 32 01 storb \$0x3:s,0x12345:l\(r2\)
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1a8: 45 23
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1aa: 12 00 38 04 storb \$0x3:s,0xabcd:l\(r8\)
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1aa: 12 00 38 04 storb \$0x3:s,0x4abcd:l\(r8\)
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1ae: cd ab
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1b0: 12 00 3d 1f storb \$0x3:s,0xfabcd:l\(r13\)
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1b4: cd ab
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1b6: 12 00 38 0f storb \$0x3:s,0xabcd:l\(r8\)
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1b6: 12 00 38 0f storb \$0x3:s,0xfabcd:l\(r8\)
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1ba: cd ab
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1bc: 12 00 39 0f storb \$0x3:s,0xabcd:l\(r9\)
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1bc: 12 00 39 0f storb \$0x3:s,0xfabcd:l\(r9\)
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1c0: cd ab
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1c2: 12 00 39 04 storb \$0x3:s,0xabcd:l\(r9\)
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1c2: 12 00 39 04 storb \$0x3:s,0x4abcd:l\(r9\)
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1c6: cd ab
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1c8: 31 82 storb \$0x3:s,0x0:s\(r2,r1\)
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1ca: 51 83 01 00 storb \$0x5:s,0x1:m\(r2,r1\)
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@ -130,17 +130,17 @@ Disassembly of section .text:
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198: 3d c3 ff 0f storw \$0x3:s,0xfff:m\(r13\)
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19c: 3d c3 ff ff storw \$0x3:s,0xffff:m\(r13\)
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1a0: 3c c3 43 23 storw \$0x3:s,0x2343:m\(r12\)
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1a4: 13 00 32 01 storw \$0x3:s,0x2345:l\(r2\)
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1a4: 13 00 32 01 storw \$0x3:s,0x12345:l\(r2\)
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1a8: 45 23
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1aa: 13 00 38 04 storw \$0x3:s,0xabcd:l\(r8\)
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1aa: 13 00 38 04 storw \$0x3:s,0x4abcd:l\(r8\)
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1ae: cd ab
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1b0: 13 00 3d 1f storw \$0x3:s,0xfabcd:l\(r13\)
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1b4: cd ab
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1b6: 13 00 38 0f storw \$0x3:s,0xabcd:l\(r8\)
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1b6: 13 00 38 0f storw \$0x3:s,0xfabcd:l\(r8\)
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1ba: cd ab
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1bc: 13 00 39 0f storw \$0x3:s,0xabcd:l\(r9\)
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1bc: 13 00 39 0f storw \$0x3:s,0xfabcd:l\(r9\)
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1c0: cd ab
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1c2: 13 00 39 04 storw \$0x3:s,0xabcd:l\(r9\)
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1c2: 13 00 39 04 storw \$0x3:s,0x4abcd:l\(r9\)
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1c6: cd ab
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1c8: 31 c2 storw \$0x3:s,0x0:s\(r2,r1\)
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1ca: 51 c3 01 00 storw \$0x5:s,0x1:m\(r2,r1\)
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@ -59,17 +59,17 @@ Disassembly of section .text:
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b0: 3d 7b ff 0f tbitb \$0x3,0xfff:m\(r13\)
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b4: 3d 7b ff ff tbitb \$0x3,0xffff:m\(r13\)
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b8: 3c 7b 43 23 tbitb \$0x3,0x2343:m\(r12\)
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bc: 10 00 32 c1 tbitb \$0x3,0x2345:l\(r2\)
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bc: 10 00 32 c1 tbitb \$0x3,0x12345:l\(r2\)
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c0: 45 23
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c2: 10 00 38 c4 tbitb \$0x3,0xabcd:l\(r8\)
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c2: 10 00 38 c4 tbitb \$0x3,0x4abcd:l\(r8\)
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c6: cd ab
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c8: 10 00 3d df tbitb \$0x3,0xfabcd:l\(r13\)
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cc: cd ab
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ce: 10 00 38 cf tbitb \$0x3,0xabcd:l\(r8\)
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ce: 10 00 38 cf tbitb \$0x3,0xfabcd:l\(r8\)
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d2: cd ab
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d4: 10 00 39 cf tbitb \$0x3,0xabcd:l\(r9\)
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d4: 10 00 39 cf tbitb \$0x3,0xfabcd:l\(r9\)
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d8: cd ab
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da: 10 00 39 c4 tbitb \$0x3,0xabcd:l\(r9\)
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da: 10 00 39 c4 tbitb \$0x3,0x4abcd:l\(r9\)
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de: cd ab
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e0: 31 7a tbitb \$0x3,0x0:s\(r2,r1\)
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e2: 51 7b 01 00 tbitb \$0x5,0x1:m\(r2,r1\)
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@ -95,17 +95,17 @@ Disassembly of section .text:
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136: 3d 79 ff 0f tbitw \$0x3:s,0xfff:m\(r13\)
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13a: 3d 79 ff ff tbitw \$0x3:s,0xffff:m\(r13\)
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13e: 3c 79 43 23 tbitw \$0x3:s,0x2343:m\(r12\)
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142: 11 00 32 c1 tbitw \$0x3:s,0x2345:l\(r2\)
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142: 11 00 32 c1 tbitw \$0x3:s,0x12345:l\(r2\)
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146: 45 23
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148: 11 00 38 c4 tbitw \$0x3:s,0xabcd:l\(r8\)
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148: 11 00 38 c4 tbitw \$0x3:s,0x4abcd:l\(r8\)
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14c: cd ab
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14e: 11 00 3d df tbitw \$0x3:s,0xfabcd:l\(r13\)
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152: cd ab
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154: 11 00 38 cf tbitw \$0x3:s,0xabcd:l\(r8\)
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154: 11 00 38 cf tbitw \$0x3:s,0xfabcd:l\(r8\)
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158: cd ab
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15a: 11 00 39 cf tbitw \$0x3:s,0xabcd:l\(r9\)
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15a: 11 00 39 cf tbitw \$0x3:s,0xfabcd:l\(r9\)
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15e: cd ab
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160: 11 00 39 c4 tbitw \$0x3:s,0xabcd:l\(r9\)
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160: 11 00 39 c4 tbitw \$0x3:s,0x4abcd:l\(r9\)
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164: cd ab
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166: 11 00 f2 c0 tbitw \$0xf:s,0x0:l\(r2\)
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16a: 00 00
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@ -123,17 +123,17 @@ Disassembly of section .text:
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190: dd 79 ff 0f tbitw \$0xd:s,0xfff:m\(r13\)
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194: dd 79 ff ff tbitw \$0xd:s,0xffff:m\(r13\)
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198: dc 79 43 23 tbitw \$0xd:s,0x2343:m\(r12\)
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19c: 11 00 d2 c1 tbitw \$0xd:s,0x2345:l\(r2\)
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19c: 11 00 d2 c1 tbitw \$0xd:s,0x12345:l\(r2\)
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1a0: 45 23
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1a2: 11 00 d8 c4 tbitw \$0xd:s,0xabcd:l\(r8\)
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1a2: 11 00 d8 c4 tbitw \$0xd:s,0x4abcd:l\(r8\)
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1a6: cd ab
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1a8: 11 00 dd df tbitw \$0xd:s,0xfabcd:l\(r13\)
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1ac: cd ab
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1ae: 11 00 d8 cf tbitw \$0xd:s,0xabcd:l\(r8\)
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1ae: 11 00 d8 cf tbitw \$0xd:s,0xfabcd:l\(r8\)
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1b2: cd ab
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1b4: 11 00 d9 cf tbitw \$0xd:s,0xabcd:l\(r9\)
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1b4: 11 00 d9 cf tbitw \$0xd:s,0xfabcd:l\(r9\)
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1b8: cd ab
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1ba: 11 00 d9 c4 tbitw \$0xd:s,0xabcd:l\(r9\)
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1ba: 11 00 d9 c4 tbitw \$0xd:s,0x4abcd:l\(r9\)
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1be: cd ab
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1c0: 31 7e tbitw \$0x3:s,0x0:s\(r2,r1\)
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1c2: 51 79 01 00 tbitw \$0x5:s,0x1:m\(r2,r1\)
|
||||
|
||||
@ -1,3 +1,12 @@
|
||||
2020-08-30 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* cr16-dis.c: Formatting.
|
||||
(parameter): Delete struct typedef. Use dwordU instead
|
||||
throughout file.
|
||||
(make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
|
||||
and tbitb.
|
||||
(make_argument <arg_cr>): Extract 20-bit field not 16-bit.
|
||||
|
||||
2020-08-29 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR 26446
|
||||
|
||||
@ -29,19 +29,13 @@
|
||||
#define ESCAPE_16_BIT 0xB
|
||||
|
||||
/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
|
||||
#define EXTRACT(a, offs, n_bits) \
|
||||
#define EXTRACT(a, offs, n_bits) \
|
||||
(((a) >> (offs)) & ((1ul << ((n_bits) - 1) << 1) - 1))
|
||||
|
||||
/* Set Bit Mask - a mask to set all bits in a 32-bit word starting
|
||||
from offset 'offs'. */
|
||||
#define SBM(offs) ((1ul << 31 << 1) - (1ul << (offs)))
|
||||
|
||||
typedef struct
|
||||
{
|
||||
dwordU val;
|
||||
int nbits;
|
||||
} parameter;
|
||||
|
||||
/* Structure to map valid 'cinv' instruction options. */
|
||||
|
||||
typedef struct
|
||||
@ -287,14 +281,10 @@ getprocpregname (int reg_index)
|
||||
0 16 32 48
|
||||
words [0] [1] [2] */
|
||||
|
||||
static parameter
|
||||
static inline dwordU
|
||||
makelongparameter (ULONGLONG val, int start, int end)
|
||||
{
|
||||
parameter p;
|
||||
|
||||
p.val = (dwordU) EXTRACT (val, 48 - end, end - start);
|
||||
p.nbits = end - start;
|
||||
return p;
|
||||
return EXTRACT (val, 48 - end, end - start);
|
||||
}
|
||||
|
||||
/* Build a mask of the instruction's 'constant' opcode,
|
||||
@ -330,10 +320,10 @@ cr16_match_opcode (void)
|
||||
mask = build_mask ();
|
||||
|
||||
if ((doubleWord & mask) == BIN (instruction->match,
|
||||
instruction->match_bits))
|
||||
return 1;
|
||||
instruction->match_bits))
|
||||
return 1;
|
||||
else
|
||||
instruction--;
|
||||
instruction--;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -344,7 +334,7 @@ static void
|
||||
make_argument (argument * a, int start_bits)
|
||||
{
|
||||
int inst_bit_size;
|
||||
parameter p;
|
||||
dwordU p;
|
||||
|
||||
if ((instruction->size == 3) && a->size >= 16)
|
||||
inst_bit_size = 48;
|
||||
@ -357,75 +347,72 @@ make_argument (argument * a, int start_bits)
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->r = p.val;
|
||||
a->r = p;
|
||||
break;
|
||||
|
||||
case arg_rp:
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->rp = p.val;
|
||||
a->rp = p;
|
||||
break;
|
||||
|
||||
case arg_pr:
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->pr = p.val;
|
||||
a->pr = p;
|
||||
break;
|
||||
|
||||
case arg_prp:
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->prp = p.val;
|
||||
a->prp = p;
|
||||
break;
|
||||
|
||||
case arg_ic:
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
break;
|
||||
|
||||
case arg_cc:
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
|
||||
a->cc = p.val;
|
||||
a->cc = p;
|
||||
break;
|
||||
|
||||
case arg_idxr:
|
||||
if ((IS_INSN_MNEMONIC ("cbitb"))
|
||||
|| (IS_INSN_MNEMONIC ("sbitb"))
|
||||
|| (IS_INSN_MNEMONIC ("tbitb")))
|
||||
if (IS_INSN_TYPE (CSTBIT_INS) && instruction->mnemonic[4] == 'b')
|
||||
p = makelongparameter (cr16_allWords, 8, 9);
|
||||
else
|
||||
p = makelongparameter (cr16_allWords, 9, 10);
|
||||
a->i_r = p.val;
|
||||
a->i_r = p;
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - a->size, inst_bit_size);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
break;
|
||||
|
||||
case arg_idxrp:
|
||||
p = makelongparameter (cr16_allWords, start_bits + 12, start_bits + 13);
|
||||
a->i_r = p.val;
|
||||
a->i_r = p;
|
||||
p = makelongparameter (cr16_allWords, start_bits + 13, start_bits + 16);
|
||||
a->rp = p.val;
|
||||
a->rp = p;
|
||||
if (inst_bit_size > 32)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - start_bits - 12,
|
||||
inst_bit_size);
|
||||
a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000));
|
||||
a->constant = (p & 0xffff) | (p >> 8 & 0xf0000);
|
||||
}
|
||||
else if (instruction->size == 2)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - 22,
|
||||
inst_bit_size);
|
||||
a->constant = (p.val & 0xf) | (((p.val >>20) & 0x3) << 4)
|
||||
| ((p.val >>14 & 0x3) << 6) | (((p.val >>7) & 0x1f) <<7);
|
||||
a->constant = ((p & 0xf) | (((p >> 20) & 0x3) << 4)
|
||||
| ((p >> 14 & 0x3) << 6) | (((p >>7) & 0x1f) << 7));
|
||||
}
|
||||
else if (instruction->size == 1 && a->size == 0)
|
||||
a->constant = 0;
|
||||
@ -434,17 +421,17 @@ make_argument (argument * a, int start_bits)
|
||||
|
||||
case arg_rbase:
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size, inst_bit_size);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - (start_bits + 4),
|
||||
inst_bit_size - start_bits);
|
||||
a->r = p.val;
|
||||
inst_bit_size - start_bits);
|
||||
a->r = p;
|
||||
break;
|
||||
|
||||
case arg_cr:
|
||||
p = makelongparameter (cr16_allWords, start_bits + 12, start_bits + 16);
|
||||
a->r = p.val;
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - 16, inst_bit_size);
|
||||
a->constant = p.val;
|
||||
a->r = p;
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - 28, inst_bit_size);
|
||||
a->constant = ((p >> 8) & 0xf0000) | (p & 0xffff);
|
||||
break;
|
||||
|
||||
case arg_crp:
|
||||
@ -452,19 +439,19 @@ make_argument (argument * a, int start_bits)
|
||||
p = makelongparameter (cr16_allWords, 12, 16);
|
||||
else
|
||||
p = makelongparameter (cr16_allWords, start_bits + 12, start_bits + 16);
|
||||
a->rp = p.val;
|
||||
a->rp = p;
|
||||
|
||||
if (inst_bit_size > 32)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - start_bits - 12,
|
||||
inst_bit_size);
|
||||
a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000));
|
||||
a->constant = ((p & 0xffff) | (p >> 8 & 0xf0000));
|
||||
}
|
||||
else if (instruction->size == 2)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, inst_bit_size - 16,
|
||||
inst_bit_size);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
}
|
||||
else if (instruction->size == 1 && a->size != 0)
|
||||
{
|
||||
@ -473,9 +460,9 @@ make_argument (argument * a, int start_bits)
|
||||
|| IS_INSN_MNEMONIC ("loadd")
|
||||
|| IS_INSN_MNEMONIC ("storw")
|
||||
|| IS_INSN_MNEMONIC ("stord"))
|
||||
a->constant = (p.val * 2);
|
||||
a->constant = p * 2;
|
||||
else
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
}
|
||||
else /* below case for 0x0(reg pair) */
|
||||
a->constant = 0;
|
||||
@ -493,21 +480,21 @@ make_argument (argument * a, int start_bits)
|
||||
{
|
||||
case 8 :
|
||||
p = makelongparameter (cr16_allWords, 0, start_bits);
|
||||
a->constant = ((((p.val&0xf00)>>4)) | (p.val&0xf));
|
||||
a->constant = ((p & 0xf00) >> 4) | (p & 0xf);
|
||||
break;
|
||||
|
||||
case 24:
|
||||
if (instruction->size == 3)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, 16, inst_bit_size);
|
||||
a->constant = ((((p.val>>16)&0xf) << 20)
|
||||
| (((p.val>>24)&0xf) << 16)
|
||||
| (p.val & 0xffff));
|
||||
a->constant = ((((p >> 16) & 0xf) << 20)
|
||||
| (((p >> 24) & 0xf) << 16)
|
||||
| (p & 0xffff));
|
||||
}
|
||||
else if (instruction->size == 2)
|
||||
{
|
||||
p = makelongparameter (cr16_allWords, 8, inst_bit_size);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
}
|
||||
break;
|
||||
|
||||
@ -515,7 +502,7 @@ make_argument (argument * a, int start_bits)
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -524,7 +511,7 @@ make_argument (argument * a, int start_bits)
|
||||
p = makelongparameter (cr16_allWords,
|
||||
inst_bit_size - (start_bits + a->size),
|
||||
inst_bit_size - start_bits);
|
||||
a->constant = p.val;
|
||||
a->constant = p;
|
||||
}
|
||||
break;
|
||||
|
||||
@ -721,18 +708,18 @@ print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *inf
|
||||
|
||||
/* For "bal (ra), disp17" instruction only. */
|
||||
if ((IS_INSN_MNEMONIC ("bal")) && (i == 0) && instruction->size == 2)
|
||||
{
|
||||
info->fprintf_func (info->stream, "(ra),");
|
||||
continue;
|
||||
}
|
||||
{
|
||||
info->fprintf_func (info->stream, "(ra),");
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((INST_HAS_REG_LIST) && (i == 2))
|
||||
info->fprintf_func (info->stream, "RA");
|
||||
info->fprintf_func (info->stream, "RA");
|
||||
else
|
||||
print_arg (¤tInsn->arg[i], memaddr, info);
|
||||
print_arg (¤tInsn->arg[i], memaddr, info);
|
||||
|
||||
if ((i != currentInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b")))
|
||||
info->fprintf_func (info->stream, ",");
|
||||
info->fprintf_func (info->stream, ",");
|
||||
}
|
||||
}
|
||||
|
||||
@ -814,17 +801,18 @@ print_insn_cr16 (bfd_vma memaddr, struct disassemble_info *info)
|
||||
if (is_decoded > 0 && (cr16_words[0] != 0 || cr16_words[1] != 0))
|
||||
{
|
||||
if (strneq (instruction->mnemonic, "cinv", 4))
|
||||
info->fprintf_func (info->stream,"%s", getcinvstring (instruction->mnemonic));
|
||||
info->fprintf_func (info->stream,"%s",
|
||||
getcinvstring (instruction->mnemonic));
|
||||
else
|
||||
info->fprintf_func (info->stream, "%s", instruction->mnemonic);
|
||||
info->fprintf_func (info->stream, "%s", instruction->mnemonic);
|
||||
|
||||
if (((cr16_currInsn.nargs = get_number_of_operands ()) != 0)
|
||||
&& ! (IS_INSN_MNEMONIC ("b")))
|
||||
info->fprintf_func (info->stream, "\t");
|
||||
info->fprintf_func (info->stream, "\t");
|
||||
cr16_make_instruction ();
|
||||
/* For push/pop/pushrtn with RA instructions. */
|
||||
if ((INST_HAS_REG_LIST) && ((cr16_words[0] >> 7) & 0x1))
|
||||
cr16_currInsn.nargs +=1;
|
||||
cr16_currInsn.nargs +=1;
|
||||
print_arguments (&cr16_currInsn, memaddr, info);
|
||||
return cr16_currInsn.size;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user