diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index d63066e1f41..0d75181151a 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -1,3 +1,10 @@
+Mon Dec  4 12:22:24 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* gencode.c (tab): Added several sh3 opcodes.
+	(think): Added printonmatch for A_SSR and A_SPC.
+	* interp.c (SSR, SPC): Added definitions.
+	(saved_state_type): Added ssr and spc registers.
+
 Wed Nov 29 12:39:27 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
 
 	* gencode.c (tab): In shad/shld definitions, negate R[m] before
@@ -32,7 +39,7 @@ Sat Oct 21 13:01:18 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
 start-sanitize-sh3e
 Mon Oct 16 18:24:03 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
 
-	* interp.c (saved_start_type): Move FP registers to immediately
+	* interp.c (saved_state_type): Move FP registers to immediately
 	after SR.
 
 end-sanitize-sh3e
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index acba02a3c3f..a1874c00139 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -64,6 +64,7 @@ op tab[] =
   {"","","bt.s <bdisp8>", "10001101i8p1....","if(T) {ult = PC; PC+=(SEXT(i)<<1)+2;C+=2;SL(ult+2);}"},
   {"","","bf.s <bdisp8>", "10001111i8p1....","if(!T) {ult = PC; PC+=(SEXT(i)<<1)+2;C+=2;SL(ult+2);}"},
   {"","","clrmac", "0000000000101000", "MACH = MACL = 0;"},
+  {"","","clrs", "0000000001001000", "S= 0;"},
   {"","","clrt", "0000000000001000", "T= 0;"},
   {"","0","cmp/eq #<imm>,R0", "10001000i8*1....", ";T = R0 == SEXT(i);"},
   {"","mn","cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000", "T=R[n]==R[m];"},
@@ -84,18 +85,23 @@ op tab[] =
   {"n","m","extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101", "R[n] = R[m] & 0xffff;"},
   {"","n","jmp @<REG_N>", "0100nnnn00101011", "ult = PC; PC=R[n]-2; SL(ult+2);"},
   {"","n","jsr @<REG_N>", "0100nnnn00001011", "PR = PC + 4; PC=R[n]-2; if (~doprofile) gotcall(PR,PC+2);SL(PR-2);"},
-  {"","n","ldc <REG_N>,GBR", "0100nnnn00011110", "GBR=R[n];"},
   {"","n","ldc <REG_N>,SR", "0100nnnn00001110", "SET_SR(R[n]);"},
+  {"","n","ldc <REG_N>,GBR", "0100nnnn00011110", "GBR=R[n];"},
   {"","n","ldc <REG_N>,VBR", "0100nnnn00101110", "VBR=R[n];"},
-  {"","n","ldc.l @<REG_N>+,GBR", "0100nnnn00010111", "GBR=RLAT(R[n]);R[n]+=4;;"},
+  {"","n","ldc <REG_N>,SSR", "0100nnnn00111110", "SSR=R[n];"},
+  {"","n","ldc <REG_N>,SPC", "0100nnnn01001110", "SPC=R[n];"},
   {"","n","ldc.l @<REG_N>+,SR", "0100nnnn00000111", "SET_SR(RLAT(R[n]));R[n]+=4;;"},
+  {"","n","ldc.l @<REG_N>+,GBR", "0100nnnn00010111", "GBR=RLAT(R[n]);R[n]+=4;;"},
   {"","n","ldc.l @<REG_N>+,VBR", "0100nnnn00100111", "VBR=RLAT(R[n]);R[n]+=4;;"},
+  {"","n","ldc.l @<REG_N>+,SSR", "0100nnnn00110111", "SSR=RLAT(R[n]);R[n]+=4;;"},
+  {"","n","ldc.l @<REG_N>+,SPC", "0100nnnn01000111", "SPC=RLAT(R[n]);R[n]+=4;;"},
   {"","n","lds <REG_N>,MACH", "0100nnnn00001010", "MACH = R[n];"},
   {"","n","lds <REG_N>,MACL", "0100nnnn00011010", "MACL= R[n];"},
   {"","n","lds <REG_N>,PR", "0100nnnn00101010", "PR = R[n];"},
   {"","n","lds.l @<REG_N>+,MACH", "0100nnnn00000110", "MACH = SEXT(RLAT(R[n]));R[n]+=4;"},
   {"","n","lds.l @<REG_N>+,MACL", "0100nnnn00010110", "MACL = RLAT(R[n]);R[n]+=4;"},
   {"","n","lds.l @<REG_N>+,PR", "0100nnnn00100110", "PR = RLAT(R[n]);R[n]+=4;;"},
+  {"","","ldtlb", "0000000000111000", "/*XXX*/ abort();"},
   {"","n","mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", "macw(R0,memory,n,m);"},
   {"n","","mov #<imm>,<REG_N>", "1110nnnni8*1....", "R[n] = SEXT(i);"},
   {"n","m","mov <REG_M>,<REG_N>", "0110nnnnmmmm0011", "R[n] = R[m];"},
@@ -150,6 +156,7 @@ op tab[] =
   {"","","rte", "0000000000101011", 
     "{ int tmp = PC; PC=RLAT(R[15])+2;R[15]+=4;SET_SR(RLAT(R[15]) & 0x3f3);R[15]+=4;SL(tmp+2);}"},
   {"","","rts", "0000000000001011", "ult=PC;PC=PR-2;SL(ult+2);"},
+  {"","","sets", "0000000001011000", "S=1;"},
   {"","","sett", "0000000000011000", "T=1;"},
   {"n","mn","shad <REG_M>,<REG_N>", "0100nnnnmmmm1100",
     "R[n] = (R[m] < 0) ? (R[n] >> ((-R[m])&0x1f)) : (R[n] << (R[m] & 0x1f));"},
@@ -166,12 +173,16 @@ op tab[] =
   {"n","n","shlr2 <REG_N>", "0100nnnn00001001", "R[n]=UR[n]>>2;"},
   {"n","n","shlr8 <REG_N>", "0100nnnn00011001", "R[n]=UR[n]>>8;"},
   {"","","sleep", "0000000000011011", "trap(0xc3,R0,memory,maskl,maskw,little_endian);PC-=2;"},
+  {"n","","stc SR,<REG_N>",  "0000nnnn00000010", "R[n]=GET_SR();"},
   {"n","","stc GBR,<REG_N>", "0000nnnn00010010", "R[n]=GBR;"},
-  {"n","","stc SR,<REG_N>", "0000nnnn00000010", "R[n]=GET_SR();"},
   {"n","","stc VBR,<REG_N>", "0000nnnn00100010", "R[n]=VBR;"},
+  {"n","","stc SSR,<REG_N>", "0000nnnn00110010", "R[n]=SSR;"},
+  {"n","","stc SPC,<REG_N>", "0000nnnn01000010", "R[n]=SPC;"},
+  {"n","n","stc.l SR,@-<REG_N>",  "0100nnnn00000011", "R[n]-=4;WLAT(R[n],GET_SR());"},
   {"n","n","stc.l GBR,@-<REG_N>", "0100nnnn00010011", "R[n]-=4;WLAT(R[n],GBR);;"},
-  {"n","n","stc.l SR,@-<REG_N>", "0100nnnn00000011", "R[n]-=4;WLAT(R[n],GET_SR());"},
   {"n","n","stc.l VBR,@-<REG_N>", "0100nnnn00100011", "R[n]-=4;WLAT(R[n],VBR);"},
+  {"n","n","stc.l SSR,@-<REG_N>", "0100nnnn00110011", "R[n]-=4;WLAT(R[n],SSR);"},
+  {"n","n","stc.l SPC,@-<REG_N>", "0100nnnn01000011", "R[n]-=4;WLAT(R[n],SPC);"},
   {"n","","sts MACH,<REG_N>", "0000nnnn00001010", "R[n]=MACH;"},
   {"n","","sts MACL,<REG_N>", "0000nnnn00011010", "R[n]=MACL;"},
   {"n","","sts PR,<REG_N>", "0000nnnn00101010", "R[n]=PR;"},
@@ -307,6 +318,8 @@ char *arg_type_list[] =
   "A_REG_N",
   "A_SR",
   "A_VBR",
+  "A_SSR",
+  "A_SPC",
   0,
 };
 
@@ -423,6 +436,8 @@ think (o)
       printonmatch (&p, "SR", "A_SR");
       printonmatch (&p, "GBR", "A_GBR");
       printonmatch (&p, "VBR", "A_VBR");
+      printonmatch (&p, "SSR", "A_SSR");
+      printonmatch (&p, "SPC", "A_SPC");
       printonmatch (&p, "MACH", "A_MACH");
       printonmatch (&p, "MACL", "A_MACL");
       printonmatch (&p, "PR", "A_PR");