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Replace VexNDS, VexNDD and VexLWP with VexVVVV.
gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
e946488510
commit
2426c15ff8
@ -1,3 +1,10 @@
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2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (process_operands): Check vexvvvv instead
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of vexnds and vexndd.
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(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
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and vexlwp.
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2009-12-19 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (s_mips_ent): Also set BSF_FUNCTION for
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@ -4713,9 +4713,7 @@ process_operands (void)
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unnecessary segment overrides. */
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const seg_entry *default_seg = 0;
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if (i.tm.opcode_modifier.sse2avx
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&& (i.tm.opcode_modifier.vexnds
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|| i.tm.opcode_modifier.vexndd))
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if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
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{
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unsigned int dupl = i.operands;
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unsigned int dest = dupl - 1;
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@ -4959,7 +4957,7 @@ build_modrm_byte (void)
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It must have VexNDS and VexImmExt. */
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gas_assert ((i.reg_operands == 4
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexnds
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& i.tm.opcode_modifier.veximmext
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&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[dest], ®ymm)));
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@ -5005,10 +5003,9 @@ build_modrm_byte (void)
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a instruction with VEX prefix and 3 sources. */
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if (i.mem_operands == 0
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&& ((i.reg_operands == 2
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&& !i.tm.opcode_modifier.vexndd
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&& !i.tm.opcode_modifier.vexlwp)
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&& i.tm.opcode_modifier.vexvvvv <= VEXXDS)
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|| (i.reg_operands == 3
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&& i.tm.opcode_modifier.vexnds)
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS)
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|| (i.reg_operands == 4 && vex_3_sources)))
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{
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switch (i.operands)
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@ -5023,7 +5020,7 @@ build_modrm_byte (void)
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is an instruction with VexNDS. */
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gas_assert (i.imm_operands == 1
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|| (i.imm_operands == 0
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&& (i.tm.opcode_modifier.vexnds
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&& (i.tm.opcode_modifier.vexvvvv == VEXXDS
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|| i.types[0].bitfield.shiftcount)));
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if (operand_type_check (i.types[0], imm)
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|| i.types[0].bitfield.shiftcount)
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@ -5042,11 +5039,11 @@ build_modrm_byte (void)
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gas_assert ((i.imm_operands == 2
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&& i.types[0].bitfield.imm8
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&& i.types[1].bitfield.imm8)
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|| (i.tm.opcode_modifier.vexnds
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|| (i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& i.imm_operands == 1
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&& (i.types[0].bitfield.imm8
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|| i.types[i.operands - 1].bitfield.imm8)));
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if (i.tm.opcode_modifier.vexnds)
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if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
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{
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if (i.types[0].bitfield.imm8)
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source = 1;
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@ -5066,7 +5063,7 @@ build_modrm_byte (void)
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{
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dest = source + 1;
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if (i.tm.opcode_modifier.vexnds)
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if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
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{
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/* For instructions with VexNDS, the register-only
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source operand must be XMM or YMM register. It is
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@ -5356,7 +5353,7 @@ build_modrm_byte (void)
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i.rex |= REX_B;
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}
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}
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else if (i.tm.opcode_modifier.vexlwp)
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else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
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{
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i.vex.register_specifier = i.op[2].regs;
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if (!i.mem_operands)
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@ -5393,7 +5390,7 @@ build_modrm_byte (void)
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if (vex_3_sources)
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op = dest;
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else if (i.tm.opcode_modifier.vexnds)
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else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
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{
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/* For instructions with VexNDS, the register-only
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source operand is encoded in VEX prefix. */
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@ -5410,7 +5407,7 @@ build_modrm_byte (void)
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gas_assert (vex_reg < i.operands);
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}
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}
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else if (i.tm.opcode_modifier.vexndd)
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else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
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{
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/* For instructions with VexNDD, there should be
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no memory operand and the register destination
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@ -1,3 +1,22 @@
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2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
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VexLWP. Add VexVVVV.
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* i386-opc.h (VexNDS): Removed.
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(VexNDD): Likewise.
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(VexLWP): Likewise.
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(VEXXDS): New.
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(VEXNDD): Likewise.
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(VEXLWP): Likewise.
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(VexVVVV): Likewise.
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(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
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Add vexvvvv.
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* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
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VexVVVV=2 and VexLWP with VexVVVV=3.
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* i386-tbl.h: Regenerated.
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2009-12-18 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (operand_types): Move Imm1 before Imm8.
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@ -353,9 +353,7 @@ static bitfield opcode_modifiers[] =
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BITFIELD (Rex64),
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BITFIELD (Ugh),
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BITFIELD (Vex),
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BITFIELD (VexNDS),
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BITFIELD (VexNDD),
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BITFIELD (VexLWP),
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BITFIELD (VexVVVV),
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BITFIELD (VexW),
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BITFIELD (VexOpcode),
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BITFIELD (VexSources),
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@ -275,15 +275,23 @@ enum
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#define VEX128 1
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#define VEX256 2
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Vex,
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/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
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We use VexNDS on insns with VEX DDS since the register-only source
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is the second source register. */
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VexNDS,
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/* insn has VEX NDD. Register destination is encoded in Vex prefix. */
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VexNDD,
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/* insn has VEX NDD. Register destination is encoded in Vex prefix
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and one of the operands can access a memory location. */
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VexLWP,
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/* How to encode VEX.vvvv:
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0: VEX.vvvv must be 1111b.
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1: VEX.DNS. Register-only source is encoded in VEX.vvvv where
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the content of source registers will be preserved.
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VEX.DDS. The second register operand is encoded in VEX.vvvv
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where the content of first source register will be overwritten
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by the result.
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For assembler, there are no difference between VEX.DNS and
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VEX.DDS.
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2. VEX.NDD. Register destination is encoded in VEX.vvvv.
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3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
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of the operands can access a memory location.
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*/
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#define VEXXDS 1
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#define VEXNDD 2
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#define VEXLWP 3
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VexVVVV,
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/* How the VEX.W bit is used:
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0: Set by the REX.W bit.
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1: VEX.W0. Should always be 0.
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@ -373,9 +381,7 @@ typedef struct i386_opcode_modifier
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unsigned int rex64:1;
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unsigned int ugh:1;
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unsigned int vex:2;
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unsigned int vexnds:1;
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unsigned int vexndd:1;
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unsigned int vexlwp:1;
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unsigned int vexvvvv:2;
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unsigned int vexw:2;
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unsigned int vexopcode:3;
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unsigned int vexsources:2;
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1688
opcodes/i386-opc.tbl
1688
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
6984
opcodes/i386-tbl.h
6984
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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