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Add support for MIPS R6 evp and dvp instructions.
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. gas/testsuite/ * gas/mips/r6.s: Add evp and dvp instructions. * gas/mips/r6.d: Likewise. * gas/mips/r6-n32.d: Likewise. * gas/mips/r6-n64.d: Likewise.
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@ -1,3 +1,10 @@
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2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
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* gas/mips/r6.s: Add evp and dvp instructions.
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* gas/mips/r6.d: Likewise.
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* gas/mips/r6-n32.d: Likewise.
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* gas/mips/r6-n64.d: Likewise.
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2015-03-13 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/diagnostic.s: New testcases.
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@ -493,4 +493,8 @@ Disassembly of section .text:
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0+0588 <[^>]*> f8040000 jalrc a0
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0+058c <[^>]*> 04100000 nal
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0+0590 <[^>]*> 00000000 nop
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0+0594 <[^>]*> 41600004 evp
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0+0598 <[^>]*> 41600024 dvp
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0+059c <[^>]*> 41620004 evp v0
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0+05a0 <[^>]*> 41620024 dvp v0
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\.\.\.
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@ -749,4 +749,8 @@ Disassembly of section .text:
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0+0588 <[^>]*> f8040000 jalrc a0
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0+058c <[^>]*> 04100000 nal
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0+0590 <[^>]*> 00000000 nop
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0+0594 <[^>]*> 41600004 evp
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0+0598 <[^>]*> 41600024 dvp
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0+059c <[^>]*> 41620004 evp v0
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0+05a0 <[^>]*> 41620024 dvp v0
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\.\.\.
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@ -492,4 +492,8 @@ Disassembly of section .text:
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0+0588 <[^>]*> f8040000 jalrc a0
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0+058c <[^>]*> 04100000 nal
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0+0590 <[^>]*> 00000000 nop
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0+0594 <[^>]*> 41600004 evp
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0+0598 <[^>]*> 41600024 dvp
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0+059c <[^>]*> 41620004 evp v0
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0+05a0 <[^>]*> 41620024 dvp v0
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\.\.\.
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@ -261,6 +261,11 @@ new: maddf.s $f0,$f1,$f2
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jalrc $4
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nal
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evp
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dvp
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evp $2
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dvp $2
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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@ -1,3 +1,7 @@
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2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
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2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-opc.c: Add new IBM z13 instructions.
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@ -1147,6 +1147,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
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{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 },
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{"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
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{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 },
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{"dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
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{"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 },
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{"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 },
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{"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 },
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@ -1156,6 +1158,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 },
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{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 },
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{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
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{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 },
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{"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
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{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 },
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{"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
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{"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */
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