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opcodes: LoongArch: add "ret" instruction to reduce typing
This syntactic sugar is present in both classical and emerging architectures, like Alpha, SPARC and RISC-V, and assembler macros doing the same thing can already be found in the wild e.g. [1], proving the feature's popularity. It's better to provide support directly in the assembler so downstream users wouldn't have to re-invent this over and over again. [1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
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@ -28,3 +28,4 @@ Disassembly of section .text:
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[ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0x0
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[ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0x0
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[ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0x0
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[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0
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@ -20,3 +20,4 @@ bltu $r4,$r5,.L1
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bgtu $r4,$r5,.L1
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bgeu $r4,$r5,.L1
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bleu $r4,$r5,.L1
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ret
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@ -28,3 +28,4 @@ Disassembly of section .text:
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[ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0x0
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[ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0x0
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[ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0x0
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[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0
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@ -20,3 +20,4 @@ bltu $r4,$r5,.L1
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bgtu $r4,$r5,.L1
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bgeu $r4,$r5,.L1
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bleu $r4,$r5,.L1
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ret
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@ -841,6 +841,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
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{ 0x0, 0x0, "bgtu", "r,r,la", "bltu %2,%1,%%b16(%3)", 0, 0, 0 },
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{ 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 },
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{ 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 },
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{ 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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};
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