mirrors/binutils-gdb
0
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-30 13:33:53 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

2002-02-10 Chris Demetriou cgd@sibyte.com

Browse Source 
* mips.igen (ADDI): Print immediate value.
        (BREAK): Print code.
        (DADDIU, DSRAV, DSRLV): Print correct instruction name.
        (SLL): Print "nop" specially, and don't run the code
        that does the shift for the "nop" case.
This commit is contained in:
Chris Demetriou 2002-02-11 02:19:38 +00:00
parent d426c6b07f
commit 20ae00985d
2 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sim/mips/ChangeLog
View File

@ -1,3 +1,11 @@
2002-02-10 Chris Demetriou cgd@sibyte.com
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
2001-11-17 Fred Fish <fnf@redhat.com>
* sim-main.h (float_operation): Move enum declaration outside

16
sim/mips/mips.igen
View File

@ -245,7 +245,7 @@
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
"addi r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
@ -668,7 +668,7 @@
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
"break <CODE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
@ -747,7 +747,7 @@
}
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddu r<RT>, r<RS>, <IMMEDIATE>"
"daddiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
*vr4100:
@ -1113,7 +1113,7 @@
}
000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
"dsra32 r<RT>, r<RD>, r<RS>"
"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
*vr4100:
@ -1160,7 +1160,7 @@
000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
"dsrl32 r<RD>, r<RT>, r<RS>"
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*vr4100:
@ -2012,13 +2012,17 @@
}
00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
{
do_sll (SD_, RT, RD, SHIFT);
/* Skip shift for NOP, so that there won't be lots of extraneous
trace output. */
if (RD != 0 || RT != 0 || SHIFT != 0)
do_sll (SD_, RT, RD, SHIFT);
}