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* simops.c: Add logicals, mov, movhi, movea, add, addi, sub

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and subr.  No condition codes yet.
This commit is contained in:
Jeff Law 1996-08-29 19:53:37 +00:00
parent e7f3e5fbbf
commit 1fe983dcdf
2 changed files with 158 additions and 51 deletions
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5
sim/v850/ChangeLog
View File

@ -1,3 +1,8 @@
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
and subr. No condition codes yet.
Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,

204
sim/v850/simops.c
View File

@ -2,11 +2,6 @@
#include "v850_sim.h"
#include "simops.h"
void
OP_1A0 ()
{
}
void
OP_280 ()
{
@ -32,11 +27,6 @@ OP_760 ()
{
}
void
OP_6A0 ()
{
}
void
OP_580 ()
{
@ -147,11 +137,6 @@ OP_660 ()
{
}
void
OP_100 ()
{
}
void
OP_E0 ()
{
@ -167,14 +152,57 @@ OP_16007E0 ()
{
}
void
OP_600 ()
{
}
/* add reg, reg
XXX condition codes. */
void
OP_1C0 ()
{
State.regs[OP[1]] += State.regs[OP[0]];
}
/* add sign_extend(imm5), reg
XXX condition codes. */
void
OP_240 ()
{
int value = OP[0];
value = (value << 27) >> 27;
State.regs[OP[1]] += value;
}
/* addi sign_extend(imm16), reg, reg
XXX condition codes. */
void
OP_600 ()
{
int value = OP[0];
value = (value << 16) >> 16;
State.regs[OP[2]] = State.regs[OP[1]] + value;
}
/* sub reg1, reg2
XXX condition codes */
void
OP_1A0 ()
{
State.regs[OP[1]] -= State.regs[OP[0]];
}
/* subr reg1, reg2
XXX condition codes */
void
OP_180 ()
{
State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
}
void
@ -192,11 +220,6 @@ OP_12007E0 ()
{
}
void
OP_240 ()
{
}
void
OP_4007E0 ()
{
@ -212,11 +235,6 @@ OP_780 ()
{
}
void
OP_6C0 ()
{
}
void
OP_720 ()
{
@ -237,24 +255,49 @@ OP_87C0 ()
{
}
void
OP_180 ()
{
}
void
OP_300 ()
{
}
/* mov reg, reg */
void
OP_0 ()
{
State.regs[OP[1]] = State.regs[OP[0]];
}
/* mov sign_extend(imm5), reg */
void
OP_680 ()
OP_200 ()
{
int value = OP[0];
value = (value << 27) >> 27;
State.regs[OP[1]] = value;
}
/* movea sign_extend(imm16), reg, reg */
void
OP_620 ()
{
int value = OP[0];
value = (value << 16) >> 16;
State.regs[OP[2]] = State.regs[OP[1]] + value;
}
/* movhi imm16, reg, reg */
void
OP_640 ()
{
int value = OP[0];
value = (value & 0xffff) << 16;
State.regs[OP[2]] = State.regs[OP[1]] + value;
}
void
@ -262,21 +305,11 @@ OP_7C0 ()
{
}
void
OP_120 ()
{
}
void
OP_1687E0 ()
{
}
void
OP_620 ()
{
}
void
OP_1E0 ()
{
@ -292,11 +325,6 @@ OP_260 ()
{
}
void
OP_200 ()
{
}
void
OP_6E0 ()
{
@ -317,9 +345,13 @@ OP_14007E0 ()
{
}
/* not reg1, reg2
XXX condition codes */
void
OP_20 ()
{
State.regs[OP[1]] = ~State.regs[OP[0]];
}
void
@ -357,14 +389,70 @@ OP_7E0 ()
{
}
/* or reg, reg
XXX condition codes. */
void
OP_100 ()
{
State.regs[OP[1]] |= State.regs[OP[0]];
}
/* ori zero_extend(imm16), reg, reg
XXX condition codes */
void
OP_680 ()
{
int value = OP[0];
value &= 0xffff;
State.regs[OP[2]] = State.regs[OP[1]] | value;
}
/* and reg, reg
XXX condition codes. */
void
OP_140 ()
{
State.regs[OP[1]] &= State.regs[OP[0]];
}
/* andi zero_extend(imm16), reg, reg
XXX condition codes. */
void
OP_640 ()
OP_6C0 ()
{
int value = OP[0];
value &= 0xffff;
State.regs[OP[2]] = State.regs[OP[1]] & value;
}
/* xor reg, reg
XXX condition codes. */
void
OP_120 ()
{
State.regs[OP[1]] ^= State.regs[OP[0]];
}
/* xori zero_extend(imm16), reg, reg
XXX condition codes. */
void
OP_6A0 ()
{
int value = OP[0];
value &= 0xffff;
State.regs[OP[2]] = State.regs[OP[1]] ^ value;
}
void
@ -372,3 +460,17 @@ OP_C0 ()
{
}
void
OP_480 ()
{
}
void
OP_380 ()
{
}
void
OP_501 ()
{
}