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Expose the BTI BTYPE more explicitly in the registers

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Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:

cpsr           0x60001000          [ EL=0 BTYPE=0 SSBS C Z ]
This commit is contained in:
Luis Machado 2021-11-17 10:02:44 -03:00
parent c9dcc18f8d
commit 1aed145ad6
2 changed files with 4 additions and 0 deletions
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1
gdb/features/aarch64-core.c
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@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
tdesc_add_flag (type_with_fields, 7, "I");
tdesc_add_flag (type_with_fields, 8, "A");
tdesc_add_flag (type_with_fields, 9, "D");
tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11);
tdesc_add_flag (type_with_fields, 12, "SSBS");
tdesc_add_flag (type_with_fields, 20, "IL");
tdesc_add_flag (type_with_fields, 21, "SS");

3
gdb/features/aarch64-core.xml
View File

@ -61,6 +61,9 @@
<!-- Debug exception mask. -->
<field name="D" start="9" end="9"/>
<!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
<field name="BTYPE" start="10" end="11"/>
<!-- ARMv8.0-A: Speculative Store Bypass. -->
<field name="SSBS" start="12" end="12"/>