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[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
This commit is contained in:
Sudakshina Das
parent
73b605ec3f
commit
193614f2b9
@ -1,3 +1,13 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_operands): Add switch case for
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AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add "memtag"
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@ -5742,6 +5742,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SIMM5:
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case AARCH64_OPND_FBITS:
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case AARCH64_OPND_UIMM4:
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case AARCH64_OPND_UIMM4_ADDG:
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case AARCH64_OPND_UIMM10:
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case AARCH64_OPND_UIMM3_OP1:
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case AARCH64_OPND_UIMM3_OP2:
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case AARCH64_OPND_IMM_VLSL:
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35
gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
Normal file
35
gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
Normal file
@ -0,0 +1,35 @@
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#as: -march=armv8.5-a+memtag
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# objdump: -d
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.*: .*
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Disassembly of section \.text:
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0+0 <func>:
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.*: 9ac01000 irg x0, x0, x0
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.*: 9ac0101b irg x27, x0, x0
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.*: 9ac01360 irg x0, x27, x0
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.*: 9adb1000 irg x0, x0, x27
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.*: 9adb137b irg x27, x27, x27
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.*: 9adf101f irg sp, x0
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.*: 9adf13e0 irg x0, sp
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.*: 9ac01400 gmi x0, x0, x0
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.*: 9ac0141b gmi x27, x0, x0
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.*: 9ac01760 gmi x0, x27, x0
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.*: 9adb1400 gmi x0, x0, x27
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.*: 9adb177b gmi x27, x27, x27
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.*: 9ac017e0 gmi x0, sp, x0
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.*: 9ac0141f gmi xzr, x0, x0
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.*: 91800000 addg x0, x0, #0x0, #0x0
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.*: 9180001b addg x27, x0, #0x0, #0x0
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.*: 91800360 addg x0, x27, #0x0, #0x0
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.*: 9180037b addg x27, x27, #0x0, #0x0
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.*: 91bf3fe0 addg x0, sp, #0x3f0, #0xf
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.*: 91aa3c1f addg sp, x0, #0x2a0, #0xf
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.*: d1800000 subg x0, x0, #0x0, #0x0
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.*: d180001b subg x27, x0, #0x0, #0x0
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.*: d1800360 subg x0, x27, #0x0, #0x0
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.*: d180037b subg x27, x27, #0x0, #0x0
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.*: d1bf3fe0 subg x0, sp, #0x3f0, #0xf
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.*: d1bf141f subg sp, x0, #0x3f0, #0x5
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37
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
Normal file
37
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
Normal file
@ -0,0 +1,37 @@
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func:
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# OP x[0,30], x[0,30], x[0,30]
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.macro expand_3_reg op
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\op x0, x0, x0
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\op x27, x0, x0
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\op x0, x27, x0
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\op x0, x0, x27
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\op x27, x27, x27
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.endm
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# OP x[0,30], x[0,30], #[0,30], #[0,14]
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.macro expand_2_reg op
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\op x0, x0, #0, #0
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\op x27, x0, #0, #0
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\op x0, x27, #0, #0
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\op x27, x27, #0, #0
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.endm
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# IRG
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expand_3_reg irg
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irg sp, x0
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irg x0, sp
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# GMI
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expand_3_reg gmi
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gmi x0, sp, x0
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gmi xzr, x0, x0
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# ADDG
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expand_2_reg addg
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addg x0, sp, #0x3f0, #0xf
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addg sp, x0, #0x2a0, #0xf
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# SUBG
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expand_2_reg subg
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subg x0, sp, #0x3f0, #0xf
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subg sp, x0, #0x3f0, #0x5
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3
gas/testsuite/gas/aarch64/illegal-memtag.d
Normal file
3
gas/testsuite/gas/aarch64/illegal-memtag.d
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@ -0,0 +1,3 @@
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#as: -march=armv8.5-a+memtag
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#source: illegal-memtag.s
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#error_output: illegal-memtag.l
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14
gas/testsuite/gas/aarch64/illegal-memtag.l
Normal file
14
gas/testsuite/gas/aarch64/illegal-memtag.l
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@ -0,0 +1,14 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `addg x1,x2,#0x3ef,#0x6'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,#0x400,#0x3'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
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[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
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[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `gmi x1,x2,sp'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `gmi sp,x2,x3'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `gmi x1,xzr,x3'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `addg xzr,x2,#0,#0'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subg x1,xzr,#0,#0'
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19
gas/testsuite/gas/aarch64/illegal-memtag.s
Normal file
19
gas/testsuite/gas/aarch64/illegal-memtag.s
Normal file
@ -0,0 +1,19 @@
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func:
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# ADDG/SUBG : Fail uimm6
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addg x1, x2, #0x3ef, #0x6
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subg x1, x2, #0x400, #0x3
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subg x1, x2, -16, #0x3
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# ADDG/SUBG : Fail uimm4
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addg x1, x2, #0x3f0, #0x10
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subg x1, x2, #0x3f0, -4
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# Illegal SP/XZR registers
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irg xzr, x2, x3
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irg x1, xzr, x3
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irg x1, x2, sp
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gmi x1, x2, sp
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gmi sp, x2, x3
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gmi x1, xzr, x3
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addg xzr, x2, #0, #0
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subg x1, xzr, #0, #0
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@ -1,3 +1,8 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (aarch64_opnd): Add
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AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
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@ -246,7 +246,9 @@ enum aarch64_opnd
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AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
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AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
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AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
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AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
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AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
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AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
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AARCH64_OPND_BIT_NUM, /* Immediate. */
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AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
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AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
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@ -1,3 +1,20 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
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(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
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* aarch64-opc.c (fields): Add entry for imm4_3.
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(operand_general_constraint_met_p): Add cases for
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AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
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(aarch64_print_operand): Likewise.
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* aarch64-tbl.h (QL_ADDG): New.
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(aarch64_opcode_table): Add addg, subg, irg and gmi.
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(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
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* aarch64-asm.c (aarch64_ins_imm): Add case for
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operand_need_shift_by_four.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_memtag): New.
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File diff suppressed because it is too large
Load Diff
@ -381,6 +381,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
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imm = info->imm.value;
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if (operand_need_shift_by_two (self))
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imm >>= 2;
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if (operand_need_shift_by_four (self))
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imm >>= 4;
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insert_all_fields (self, code, imm);
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return TRUE;
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}
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File diff suppressed because it is too large
Load Diff
@ -665,6 +665,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
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if (operand_need_shift_by_two (self))
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imm <<= 2;
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else if (operand_need_shift_by_four (self))
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imm <<= 4;
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if (info->type == AARCH64_OPND_ADDR_ADRP)
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imm <<= 12;
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@ -83,7 +83,9 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_3}, "a 4-bit unsigned Logical Address Tag modifier"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
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@ -228,86 +230,86 @@ const struct aarch64_operand aarch64_operands[] =
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static const unsigned op_enum_table [] =
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{
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0,
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873,
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874,
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875,
|
||||
877,
|
||||
878,
|
||||
879,
|
||||
880,
|
||||
881,
|
||||
882,
|
||||
876,
|
||||
877,
|
||||
883,
|
||||
884,
|
||||
906,
|
||||
907,
|
||||
908,
|
||||
885,
|
||||
886,
|
||||
880,
|
||||
881,
|
||||
887,
|
||||
888,
|
||||
910,
|
||||
911,
|
||||
912,
|
||||
913,
|
||||
914,
|
||||
915,
|
||||
909,
|
||||
910,
|
||||
916,
|
||||
917,
|
||||
965,
|
||||
966,
|
||||
967,
|
||||
968,
|
||||
12,
|
||||
634,
|
||||
635,
|
||||
1160,
|
||||
1162,
|
||||
1164,
|
||||
972,
|
||||
1163,
|
||||
1161,
|
||||
316,
|
||||
622,
|
||||
633,
|
||||
632,
|
||||
918,
|
||||
919,
|
||||
913,
|
||||
914,
|
||||
920,
|
||||
921,
|
||||
969,
|
||||
970,
|
||||
629,
|
||||
626,
|
||||
618,
|
||||
617,
|
||||
971,
|
||||
972,
|
||||
12,
|
||||
636,
|
||||
637,
|
||||
1164,
|
||||
1166,
|
||||
1168,
|
||||
976,
|
||||
1167,
|
||||
1165,
|
||||
318,
|
||||
624,
|
||||
625,
|
||||
628,
|
||||
630,
|
||||
635,
|
||||
634,
|
||||
974,
|
||||
631,
|
||||
980,
|
||||
662,
|
||||
628,
|
||||
620,
|
||||
619,
|
||||
626,
|
||||
627,
|
||||
630,
|
||||
632,
|
||||
633,
|
||||
984,
|
||||
664,
|
||||
667,
|
||||
670,
|
||||
665,
|
||||
668,
|
||||
663,
|
||||
666,
|
||||
817,
|
||||
176,
|
||||
177,
|
||||
821,
|
||||
178,
|
||||
179,
|
||||
514,
|
||||
751,
|
||||
387,
|
||||
180,
|
||||
181,
|
||||
516,
|
||||
755,
|
||||
389,
|
||||
411,
|
||||
391,
|
||||
413,
|
||||
1233,
|
||||
1238,
|
||||
1231,
|
||||
1230,
|
||||
415,
|
||||
1237,
|
||||
1242,
|
||||
1235,
|
||||
1234,
|
||||
1241,
|
||||
1243,
|
||||
1244,
|
||||
1240,
|
||||
1246,
|
||||
1238,
|
||||
1245,
|
||||
129,
|
||||
1247,
|
||||
1248,
|
||||
1244,
|
||||
1250,
|
||||
1249,
|
||||
131,
|
||||
};
|
||||
|
||||
/* Given the opcode enumerator OP, return the pointer to the corresponding
|
||||
|
||||
@ -243,6 +243,7 @@ const aarch64_field fields[] =
|
||||
{ 15, 6 }, /* imm6_2: in rmif instructions. */
|
||||
{ 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
|
||||
{ 0, 4 }, /* imm4_2: in rmif instructions. */
|
||||
{ 10, 4 }, /* imm4_3: in adddg/subg instructions. */
|
||||
{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
|
||||
{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
|
||||
{ 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
|
||||
@ -2091,6 +2092,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
case AARCH64_OPND_CCMP_IMM:
|
||||
case AARCH64_OPND_EXCEPTION:
|
||||
case AARCH64_OPND_UIMM4:
|
||||
case AARCH64_OPND_UIMM4_ADDG:
|
||||
case AARCH64_OPND_UIMM7:
|
||||
case AARCH64_OPND_UIMM3_OP1:
|
||||
case AARCH64_OPND_UIMM3_OP2:
|
||||
@ -2108,6 +2110,21 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_UIMM10:
|
||||
/* Scaled unsigned 10 bits immediate offset. */
|
||||
if (!value_in_range_p (opnd->imm.value, 0, 1008))
|
||||
{
|
||||
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!value_aligned_p (opnd->imm.value, 16))
|
||||
{
|
||||
set_unaligned_error (mismatch_detail, idx, 16);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SIMM5:
|
||||
case AARCH64_OPND_SVE_SIMM5:
|
||||
case AARCH64_OPND_SVE_SIMM5B:
|
||||
@ -3434,7 +3451,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_NZCV:
|
||||
case AARCH64_OPND_EXCEPTION:
|
||||
case AARCH64_OPND_UIMM4:
|
||||
case AARCH64_OPND_UIMM4_ADDG:
|
||||
case AARCH64_OPND_UIMM7:
|
||||
case AARCH64_OPND_UIMM10:
|
||||
if (optional_operand_p (opcode, idx) == TRUE
|
||||
&& (opnd->imm.value ==
|
||||
(int64_t) get_optional_operand_default_value (opcode)))
|
||||
|
||||
@ -70,6 +70,7 @@ enum aarch64_field_kind
|
||||
FLD_imm6_2,
|
||||
FLD_imm4,
|
||||
FLD_imm4_2,
|
||||
FLD_imm4_3,
|
||||
FLD_imm5,
|
||||
FLD_imm7,
|
||||
FLD_imm8,
|
||||
@ -199,6 +200,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_LSB 5
|
||||
#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
|
||||
#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
|
||||
value by 4 to get the value
|
||||
of an immediate operand. */
|
||||
|
||||
|
||||
/* Register flags. */
|
||||
|
||||
@ -252,6 +257,12 @@ operand_need_shift_by_two (const aarch64_operand *operand)
|
||||
return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
static inline bfd_boolean
|
||||
operand_need_shift_by_four (const aarch64_operand *operand)
|
||||
{
|
||||
return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
static inline bfd_boolean
|
||||
operand_maybe_stack_pointer (const aarch64_operand *operand)
|
||||
{
|
||||
|
||||
@ -240,6 +240,12 @@
|
||||
QLF4(X,X,imm_0_63,imm_0_63), \
|
||||
}
|
||||
|
||||
/* e.g. ADDG <Xd>, <Xn>, #<uimm10>, #<uimm4>. */
|
||||
#define QL_ADDG \
|
||||
{ \
|
||||
QLF4(X,X,NIL,imm_0_15), \
|
||||
} \
|
||||
|
||||
/* e.g. BFC <Wd>, #<immr>, #<imms>. */
|
||||
#define QL_BF1 \
|
||||
{ \
|
||||
@ -2298,6 +2304,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
|
||||
CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
|
||||
CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
|
||||
MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
|
||||
MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
|
||||
/* Add/subtract (shifted register). */
|
||||
CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
|
||||
CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
|
||||
@ -3036,6 +3044,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
|
||||
CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
|
||||
CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
|
||||
MEMTAG_INSN ("irg", 0x9ac01000, 0xffe0fc00, dp_2src, OP3 (Rd_SP, Rn_SP, Rm), QL_I3SAMEX, F_OPD2_OPT | F_DEFAULT (0x1f)),
|
||||
MEMTAG_INSN ("gmi", 0x9ac01400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm), QL_I3SAMEX, 0),
|
||||
V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
|
||||
/* CRC instructions. */
|
||||
_CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
|
||||
@ -4559,8 +4569,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"a 3-bit unsigned immediate") \
|
||||
Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
|
||||
"a 4-bit unsigned immediate") \
|
||||
Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \
|
||||
"a 4-bit unsigned Logical Address Tag modifier") \
|
||||
Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
|
||||
"a 7-bit unsigned immediate") \
|
||||
Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \
|
||||
"a 10-bit unsigned multiple of 16") \
|
||||
Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
|
||||
"the bit number to be tested") \
|
||||
Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user