mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-26 19:44:11 +08:00
* m32r-sim.h (m32r_trap): Update prototype.
* traps.c (m32r_trap): New arg `pc'. * sem.c,sem-switch.c: Regenerated. * cpux.h,readx.c,semx.c: Regenerated.
This commit is contained in:
Doug Evans
parent
3efbfbebdc
commit
190659a22d
@ -1,5 +1,33 @@
|
||||
Wed Sep 9 15:29:36 1998 Doug Evans <devans@canuck.cygnus.com>
|
||||
|
||||
* m32r-sim.h (m32r_trap): Update prototype.
|
||||
* traps.c (m32r_trap): New arg `pc'.
|
||||
* sem.c,sem-switch.c: Regenerated.
|
||||
start-sanitize-m32rx
|
||||
* cpux.h,readx.c,semx.c: Regenerated.
|
||||
end-sanitize-m32rx
|
||||
|
||||
Mon Aug 3 12:59:17 1998 Doug Evans <devans@seba.cygnus.com>
|
||||
|
||||
Rename cpu m32r to m32rb to distinguish from architecture name.
|
||||
* Makefile.in (mloop.c): cpu m32r renamed to m32rb.
|
||||
(stamp-cpu): Ditto.
|
||||
* sim-main.h (WANT_CPU_M32RB): Renamed from WANT_CPU_M32R.
|
||||
* tconfig.in (WANT_CPU_M32RB): Ditto.
|
||||
* m32r.c (WANT_CPU_M32RB): Ditto.
|
||||
(*): m32r_ cpu fns renamed to m32rb_.
|
||||
* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Update.
|
||||
* arch.h,arch.c: Regenerate.
|
||||
* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
|
||||
* sem-switch.c,sem.c: Regenerate.
|
||||
|
||||
* sim-if.c (sim_open): Don't allocate memory on top of any user
|
||||
specified memory.
|
||||
(h_gr_get,h_gr_set): Delete.
|
||||
* sim-main.h (h_gr_get,h_gr_set): Delete.
|
||||
* traps.c (m32r_trap): Replace calls to h_gr_[gs]et with
|
||||
a_m32r_h_gr_[gs]et.
|
||||
|
||||
* Makefile.in (INCLUDE_DEPS): Add include/opcode/cgen.h.
|
||||
|
||||
* sim-if.c (sim_open): Open opcode table.
|
||||
|
||||
@ -100,6 +100,7 @@ typedef struct {
|
||||
#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
|
||||
} M32RX_CPU_DATA;
|
||||
|
||||
/* Cover fns for register access. */
|
||||
USI m32rx_h_pc_get (SIM_CPU *);
|
||||
void m32rx_h_pc_set (SIM_CPU *, USI);
|
||||
SI m32rx_h_gr_get (SIM_CPU *, UINT);
|
||||
@ -285,19 +286,11 @@ struct argbuf {
|
||||
UINT f_acc;
|
||||
UINT f_r2;
|
||||
} fmt_machi_a;
|
||||
struct { /* e.g. macwhi $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_macwhi;
|
||||
struct { /* e.g. mulhi $src1,$src2,$acc */
|
||||
UINT f_r1;
|
||||
UINT f_acc;
|
||||
UINT f_r2;
|
||||
} fmt_mulhi_a;
|
||||
struct { /* e.g. mulwhi $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_mulwhi;
|
||||
struct { /* e.g. mv $dr,$sr */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
@ -395,6 +388,10 @@ struct argbuf {
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_macwu1;
|
||||
struct { /* e.g. msblo $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_msblo;
|
||||
struct { /* e.g. mulwu1 $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
@ -959,20 +956,6 @@ struct scache {
|
||||
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MACWHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_MACWHI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MULHI_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
@ -989,20 +972,6 @@ struct scache {
|
||||
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MULWHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_MULWHI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MV_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
@ -1363,6 +1332,20 @@ struct scache {
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MSBLO_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_MSBLO_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_MULWU1_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
@ -1544,19 +1527,10 @@ struct parexec {
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_machi_a;
|
||||
struct { /* e.g. macwhi $src1,$src2 */
|
||||
DI accum;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_macwhi;
|
||||
struct { /* e.g. mulhi $src1,$src2,$acc */
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_mulhi_a;
|
||||
struct { /* e.g. mulwhi $src1,$src2 */
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_mulwhi;
|
||||
struct { /* e.g. mv $dr,$sr */
|
||||
SI sr;
|
||||
} fmt_mv;
|
||||
@ -1629,8 +1603,8 @@ struct parexec {
|
||||
SI src1;
|
||||
} fmt_st_plus;
|
||||
struct { /* e.g. trap $uimm4 */
|
||||
USI pc;
|
||||
USI h_cr_0;
|
||||
SI pc;
|
||||
SI uimm4;
|
||||
} fmt_trap;
|
||||
struct { /* e.g. unlock $src1,@$src2 */
|
||||
@ -1654,6 +1628,11 @@ struct parexec {
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_macwu1;
|
||||
struct { /* e.g. msblo $src1,$src2 */
|
||||
DI accum;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_msblo;
|
||||
struct { /* e.g. mulwu1 $src1,$src2 */
|
||||
SI src1;
|
||||
SI src2;
|
||||
|
||||
@ -33,12 +33,25 @@ typedef struct {
|
||||
unsigned int fillnop_count;
|
||||
/* number of parallel insns */
|
||||
unsigned int parallel_count;
|
||||
|
||||
/* FIXME: generalize this to handle all insn lengths, move to common. */
|
||||
/* number of short insns, not including parallel ones */
|
||||
unsigned int short_count;
|
||||
/* number of long insns */
|
||||
unsigned int long_count;
|
||||
|
||||
/* Working area for computing cycle counts. */
|
||||
unsigned long insn_cycles;
|
||||
unsigned long cti_stall;
|
||||
unsigned long load_stall;
|
||||
unsigned long biggest_cycles;
|
||||
} M32R_MISC_PROFILE;
|
||||
|
||||
/* Initialize the working area. */
|
||||
void m32r_init_insn_cycles (SIM_CPU *, int);
|
||||
/* Update the totals for the insn. */
|
||||
void m32r_record_insn_cycles (SIM_CPU *, int);
|
||||
|
||||
/* This is invoked by the nop pattern in the .cpu file. */
|
||||
#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
|
||||
do { \
|
||||
@ -78,7 +91,9 @@ do { \
|
||||
- NEW_PC_SKIP, sc/snc insn
|
||||
- NEW_PC_2, 2 byte non-branch non-sc/snc insn
|
||||
- NEW_PC_4, 4 byte non-branch insn
|
||||
The special values have bit 1 set so it's cheap to distinguish them. */
|
||||
The special values have bit 1 set so it's cheap to distinguish them.
|
||||
This works because all cti's are defined to zero the bottom two bits. */
|
||||
/* FIXME: replace 0xffff0001 with 1? */
|
||||
#define NEW_PC_BASE 0xffff0001
|
||||
#define NEW_PC_SKIP NEW_PC_BASE
|
||||
#define NEW_PC_2 (NEW_PC_BASE + 2)
|
||||
@ -154,6 +169,6 @@ extern device m32r_devices;
|
||||
struct _device { int foo; };
|
||||
|
||||
/* Handle the trap insn. */
|
||||
USI m32r_trap (SIM_CPU *, int);
|
||||
USI m32r_trap (SIM_CPU *, PCADDR, int);
|
||||
|
||||
#endif /* M32R_SIM_H */
|
||||
|
||||
@ -852,8 +852,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
|
||||
EXTRACT_FMT_TRAP_CODE
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (pc) = CPU (h_pc);
|
||||
OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 0));
|
||||
OPRND (pc) = CPU (h_pc);
|
||||
OPRND (uimm4) = f_uimm4;
|
||||
#undef OPRND
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
1532
sim/m32r/sem.c
1532
sim/m32r/sem.c
File diff suppressed because it is too large
Load Diff
@ -3853,7 +3853,7 @@ do {
|
||||
TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
|
||||
}
|
||||
{
|
||||
SI opval = m32r_trap (current_cpu, OPRND (uimm4));
|
||||
SI opval = m32r_trap (current_cpu, OPRND (pc), OPRND (uimm4));
|
||||
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
|
||||
taken_p = 1;
|
||||
TRACE_RESULT (current_cpu, "pc", 'x', opval);
|
||||
|
||||
@ -103,7 +103,7 @@ syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
|
||||
Preprocessing like saving the various registers has already been done. */
|
||||
|
||||
USI
|
||||
a_m32r_trap (SIM_CPU *current_cpu, int num)
|
||||
m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
host_callback *cb = STATE_CALLBACK (sd);
|
||||
@ -115,7 +115,7 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
|
||||
{
|
||||
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
|
||||
it doesn't return. Otherwise it returns and let's us try. */
|
||||
sim_handle_breakpoint (sd, current_cpu, sim_pc_get (current_cpu));
|
||||
sim_handle_breakpoint (sd, current_cpu, pc);
|
||||
/* Fall through. */
|
||||
}
|
||||
#endif
|
||||
@ -135,25 +135,24 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
|
||||
CB_SYSCALL s;
|
||||
|
||||
CB_SYSCALL_INIT (&s);
|
||||
s.func = h_gr_get (current_cpu, 0);
|
||||
s.arg1 = h_gr_get (current_cpu, 1);
|
||||
s.arg2 = h_gr_get (current_cpu, 2);
|
||||
s.arg3 = h_gr_get (current_cpu, 3);
|
||||
s.func = a_m32r_h_gr_get (current_cpu, 0);
|
||||
s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
|
||||
s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
|
||||
s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
|
||||
|
||||
if (s.func == TARGET_SYS_exit)
|
||||
{
|
||||
sim_engine_halt (sd, current_cpu, NULL, sim_pc_get (current_cpu),
|
||||
sim_exited, s.arg1);
|
||||
sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
|
||||
}
|
||||
|
||||
s.p1 = (PTR) sd;
|
||||
s.p2 = (PTR) current_cpu;
|
||||
s.read_mem = syscall_read_mem;
|
||||
s.write_mem = syscall_write_mem;
|
||||
cb_syscall (STATE_CALLBACK (sd), &s);
|
||||
h_gr_set (current_cpu, 2, s.errcode);
|
||||
h_gr_set (current_cpu, 0, s.result);
|
||||
h_gr_set (current_cpu, 1, s.result2);
|
||||
cb_syscall (cb, &s);
|
||||
a_m32r_h_gr_set (current_cpu, 2, s.errcode);
|
||||
a_m32r_h_gr_set (current_cpu, 0, s.result);
|
||||
a_m32r_h_gr_set (current_cpu, 1, s.result2);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -170,5 +169,5 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
|
||||
}
|
||||
|
||||
/* Fake an "rte" insn. */
|
||||
return (sim_pc_get (current_cpu) & -4) + 4;
|
||||
return (pc & -4) + 4;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user