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TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.

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This commit is contained in:
Andrew Cagney 1997-04-22 17:46:07 +00:00
parent 81f464815d
commit 15c1649391
27 changed files with 4000 additions and 79 deletions
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6
gdb/ChangeLog
View File

@ -1,3 +1,9 @@
start-sanitize-tic80
Mon Apr 21 22:44:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
* config/tic80/tic80.mt (SIM): Link in simulator.
end-sanitize-tic80
Tue Apr 22 09:02:10 1997 Stu Grossman (grossman@critters.cygnus.com)
* config/alpha/alpha-osf3.mh config/i386/{i386gnu linux}.mh

4
gdb/config/tic80/tic80.mt
View File

@ -3,5 +3,5 @@ TDEPFILES= tic80-tdep.o
TM_FILE= tm-tic80.h
# Disable using the simulator until it is ready.
#SIM_OBS = remote-sim.o
#SIM = ../sim/tic80/libsim.a -lm
SIM_OBS = remote-sim.o
SIM = ../sim/tic80/libsim.a -lm

105
sim/.Sanitize
View File

@ -15,13 +15,6 @@
Do-first:
v850_files="v850"
if ( echo $* | grep keep\-v850 > /dev/null ) ; then
keep_these_too="${v850_files} ${keep_these_too}"
else
lose_these_too="${v850_files} ${lose_these_too}"
fi
d30v_files="d30v igen testsuite"
if ( echo $* | grep keep\-d30v > /dev/null ) ; then
keep_these_too="${d30v_files} ${keep_these_too}"
@ -29,6 +22,20 @@ else
lose_these_too="${d30v_files} ${lose_these_too}"
fi
tic80_files="tic80 igen"
if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
keep_these_too="${tic80_files} ${keep_these_too}"
else
lose_these_too="${tic80_files} ${lose_these_too}"
fi
v850_files="v850"
if ( echo $* | grep keep\-v850 > /dev/null ) ; then
keep_these_too="${v850_files} ${keep_these_too}"
else
lose_these_too="${v850_files} ${lose_these_too}"
fi
# All files listed between the "Things-to-keep:" line and the
# "Files-to-sed:" line will be kept. All other files will be removed.
# Directories listed in this section will have their own Sanitize
@ -62,34 +69,6 @@ Things-to-lose:
Do-last:
v850_files="configure configure.in ChangeLog"
if ( echo $* | grep keep\-v850 > /dev/null ) ; then
for i in $v850_files ; do
if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Keeping v850 stuff in $i
fi
fi
done
else
for i in $v850_files ; do
if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Removing traces of \"v850\" from $i...
fi
cp $i new
sed '/start\-sanitize\-v850/,/end-\sanitize\-v850/d' < $i > new
if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
if [ -n "${verbose}" ] ; then
echo Caching $i in .Recover...
fi
mv $i .Recover
fi
mv new $i
fi
done
fi
d30v_files="configure configure.in ChangeLog"
if ( echo $* | grep keep\-d30v > /dev/null ) ; then
for i in $d30v_files ; do
@ -118,6 +97,62 @@ else
done
fi
tic80_files="configure configure.in ChangeLog"
if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
for i in $tic80_files ; do
if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Keeping tic80 stuff in $i
fi
fi
done
else
for i in $tic80_files ; do
if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Removing traces of \"tic80\" from $i...
fi
cp $i new
sed '/start\-sanitize\-tic80/,/end-\sanitize\-tic80/d' < $i > new
if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
if [ -n "${verbose}" ] ; then
echo Caching $i in .Recover...
fi
mv $i .Recover
fi
mv new $i
fi
done
fi
v850_files="configure configure.in ChangeLog"
if ( echo $* | grep keep\-v850 > /dev/null ) ; then
for i in $v850_files ; do
if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Keeping v850 stuff in $i
fi
fi
done
else
for i in $v850_files ; do
if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Removing traces of \"v850\" from $i...
fi
cp $i new
sed '/start\-sanitize\-v850/,/end-\sanitize\-v850/d' < $i > new
if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
if [ -n "${verbose}" ] ; then
echo Caching $i in .Recover...
fi
mv $i .Recover
fi
mv new $i
fi
done
fi
for i in * ; do
if test ! -d $i && (grep sanitize $i > /dev/null) ; then
echo '***' Some mentions of Sanitize are still left in $i! 1>&2

16
sim/ChangeLog
View File

@ -1,3 +1,19 @@
Mon Apr 21 22:57:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (.NOEXPORT, MAKEOVERRIDES): Moved to end, BSD make
thought that .NOEXPORT was the default target.
start-sanitize-tic80
Mon Apr 21 22:26:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (tic80-*-*): New target.
end-sanitize-tic80
Fri Apr 11 17:18:07 1997 Ian Lance Taylor <ian@cygnus.com>
* Makefile.in (clean mostlyclean): Restore targets accidentally
deleted in earlier change.
Thu Apr 3 12:20:32 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
* Makefile.in (autoheader-common, autoheader-changelog,

17
sim/Makefile.in
View File

@ -61,10 +61,6 @@ RANLIB = @RANLIB@
SUBDIRS = @subdirs@
.NOEXPORT:
MAKEOVERRIDES=
INCDIR = $(srcdir)/../include
CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
DEP = mkdep
@ -133,6 +129,16 @@ all:
else true; fi; \
done
clean mostlyclean:
@rootme=`pwd` ; export rootme ; \
for dir in . ${SUBDIRS}; do \
if [ "$$dir" = "." ]; then \
true; \
elif [ -d $$dir ]; then \
(cd $$dir; $(MAKE) $(FLAGS_TO_PASS) $@); \
else true; fi; \
done
distclean maintainer-clean realclean:
@rootme=`pwd` ; export rootme ; \
for dir in . ${SUBDIRS}; do \
@ -178,6 +184,9 @@ dvi:
###
###
.NOEXPORT:
MAKEOVERRIDES=
.PHONY: check installcheck
check:
installcheck:

6
sim/common/ChangeLog
View File

@ -1,3 +1,9 @@
Wed Apr 23 02:55:54 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-events.c (insert_sim_event): Call sim_io_error instead of
less well defined engine_error.
* sim-core.c: Ditto.
Tue Apr 22 08:48:16 1997 Stu Grossman (grossman@critters.cygnus.com)
* Make-common.in: Change clean targets to use :: so that other

21
sim/configure vendored
View File

@ -1273,6 +1273,7 @@ fi
# Assume simulator can be built with cc.
# If the user passes --enable-sim built it regardless of $(CC).
only_if_gcc=no
extra_subdirs=common
# WHEN ADDING ENTRIES TO THIS MATRIX:
# Make sure that the left side always has two dashes. Otherwise you
@ -1282,6 +1283,13 @@ only_if_gcc=no
case "${target}" in
arm*-*-*) sim_target=arm ;;
d10v-*-*) sim_target=d10v ;;
# start-sanitize-d30v
d30v-*-*)
sim_target=d30v
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen testsuite"
;;
# end-sanitize-d30v
h8300*-*-*) sim_target=h8300 ;;
h8500-*-*) sim_target=h8500 ;;
mips*-*-*)
@ -1294,6 +1302,9 @@ case "${target}" in
sim_target=mn10300
only_if_gcc=yes
;;
mn10200*-*-*)
sim_target=mn10200
;;
sh*-*-*) sim_target=sh ;;
powerpc*-*-eabi* | powerpc*-*-solaris* | powerpc*-*-sysv4* | powerpc*-*-elf* | powerpc*-*-linux* )
# The PowerPC simulator uses the GCC extension long long as well as
@ -1301,7 +1312,15 @@ case "${target}" in
# unless asked to.
sim_target=ppc
only_if_gcc=yes
#extra_subdirs="${extra_subdirs}"
;;
# start-sanitize-tic80
tic80-*-*)
sim_target=tic80
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
# end-sanitize-tic80
# start-sanitize-v850
v850-*-*)
# The V850 simulator can only be compiled by gcc.
@ -1342,7 +1361,7 @@ yes)
esac
if test x"${sim_target}" != xnone ; then
configdirs="common ${sim_target}"
configdirs="${extra_subdirs} ${sim_target}"
subdirs="$configdirs"
fi

7
sim/configure.in
View File

@ -79,6 +79,13 @@ case "${target}" in
only_if_gcc=yes
#extra_subdirs="${extra_subdirs}"
;;
# start-sanitize-tic80
tic80-*-*)
sim_target=tic80
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
# end-sanitize-tic80
# start-sanitize-v850
v850-*-*)
# The V850 simulator can only be compiled by gcc.

22
sim/igen/ChangeLog
View File

@ -1,3 +1,25 @@
Tue Apr 22 21:46:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
* igen.c (main), igen.h: Support new option - delayed-branch -
generate code to drive a delayed branch processor.
* gen-idecode.c (gen_idecode_h): Define instruction_address type.
* igen.c (print_icache_function_formal): Replace address_word with
instruction_address.
(print_semantic_function_formal): Ditto.
(print_semantic_function_type): Ditto.
* gen-idecode.c (print_idecode_issue_function_body): Ditto.
* gen-semantics.c (print_semantic_body): Ditto.
(print_c_semantic): Ditto.
* gen-support.c (support_c_function): Return a zeroed CIA instead
of just zero - works with any cia type.
* igen.c (print_itrace): For delayed branch case, print just the
current instruction.
Thu Apr 17 07:02:33 1997 Doug Evans <dje@canuck.cygnus.com>
* igen.c (print_itrace): Use TRACE_FOO_P and trace_printf.

75
sim/igen/gen-idecode.c
View File

@ -732,22 +732,22 @@ print_idecode_issue_function_body(lf *file,
{
lf_printf(file, "{\n");
lf_indent(file, +2);
lf_printf(file, "address_word nia;\n");
lf_printf(file, "instruction_address nia;\n");
if (!(code & generate_with_icache)) {
print_idecode_body(file, table, "nia =");;
}
else {
error("FIXME - idecode with cache?\n");
lf_putstr(file, "idecode_cache *cache_entry =\n");
lf_putstr(file, " cpu_icache_entry(processor, cia);\n");
lf_putstr(file, " cpu_icache_entry(cpu, cia);\n");
lf_putstr(file, "if (cache_entry->address == cia) {\n");
lf_putstr(file, " /* cache hit */\n");
lf_putstr(file, " idecode_semantic *const semantic = cache_entry->semantic;\n");
lf_putstr(file, " cia = semantic(processor, cache_entry, cia);\n");
lf_putstr(file, " cia = semantic(cpu, cache_entry, cia);\n");
/* tail */
if (can_stop) {
lf_putstr(file, "if (keep_running != NULL && !*keep_running)\n");
lf_putstr(file, " cpu_halt(processor, cia, was_continuing, 0/*ignore*/);\n");
lf_putstr(file, " cpu_halt(cpu, cia, was_continuing, 0/*ignore*/);\n");
}
lf_putstr(file, "}\n");
lf_putstr(file, "else {\n");
@ -758,9 +758,9 @@ print_idecode_issue_function_body(lf *file,
lf_indent(file, -2);
}
lf_putstr(file, " instruction_word instruction =\n");
lf_putstr(file, " vm_instruction_map_read(cpu_instruction_map(processor), processor, cia);\n");
lf_putstr(file, " vm_instruction_map_read(cpu_instruction_map(cpu), cpu, cia);\n");
lf_putstr(file, " if (WITH_MON != 0)\n");
lf_putstr(file, " mon_event(mon_event_icache_miss, processor, cia);\n");
lf_putstr(file, " mon_event(mon_event_icache_miss, cpu, cia);\n");
if ((code & generate_with_semantic_icache)) {
lf_putstr(file, "{\n");
lf_indent(file, +2);
@ -770,7 +770,7 @@ print_idecode_issue_function_body(lf *file,
}
else {
print_idecode_body(file, table, "semantic =");
lf_putstr(file, " cia = semantic(processor, cache_entry, cia);\n");
lf_putstr(file, " cia = semantic(cpu, cache_entry, cia);\n");
}
lf_putstr(file, "}\n");
}
@ -788,22 +788,22 @@ print_jump(lf *file,
{
if (is_tail) {
lf_putstr(file, "if (keep_running != NULL && !*keep_running)\n");
lf_putstr(file, " cpu_halt(processor, nia, was_continuing, 0/*na*/);\n");
lf_putstr(file, " cpu_halt(cpu, nia, was_continuing, 0/*na*/);\n");
}
if (!generate_smp) {
lf_putstr(file, "if (WITH_EVENTS) {\n");
lf_putstr(file, " if (event_queue_tick(events)) {\n");
lf_putstr(file, " cpu_set_program_counter(processor, nia);\n");
lf_putstr(file, " cpu_set_program_counter(cpu, nia);\n");
lf_putstr(file, " event_queue_process(events);\n");
lf_putstr(file, " nia = cpu_get_program_counter(processor);\n");
lf_putstr(file, " nia = cpu_get_program_counter(cpu);\n");
lf_putstr(file, " }\n");
lf_putstr(file, "}\n");
}
if (generate_smp) {
if (is_tail)
lf_putstr(file, "cpu_set_program_counter(processor, nia);\n");
lf_putstr(file, "cpu_set_program_counter(cpu, nia);\n");
lf_putstr(file, "if (WITH_EVENTS) {\n");
lf_putstr(file, " current_cpu += 1;\n");
lf_putstr(file, " if (current_cpu >= nr_cpus) {\n");
@ -816,12 +816,12 @@ print_jump(lf *file,
lf_putstr(file, "else {\n");
lf_putstr(file, " current_cpu = (current_cpu + 1) % nr_cpus;\n");
lf_putstr(file, "}\n");
lf_putstr(file, "processor = processors[current_cpu];\n");
lf_putstr(file, "nia = cpu_get_program_counter(processor);\n");
lf_putstr(file, "cpu = cpus[current_cpu];\n");
lf_putstr(file, "nia = cpu_get_program_counter(cpu);\n");
}
if ((code & generate_with_icache)) {
lf_putstr(file, "cache_entry = cpu_icache_entry(processor, nia);\n");
lf_putstr(file, "cache_entry = cpu_icache_entry(cpu, nia);\n");
lf_putstr(file, "if (cache_entry->address == nia) {\n");
lf_putstr(file, " /* cache hit */\n");
lf_putstr(file, " goto *cache_entry->semantic;\n");
@ -1020,7 +1020,7 @@ print_jump_until_stop_body(lf *file,
lf_printf(file, "int *keep_running = NULL;\n");
lf_putstr(file, "jmp_buf halt;\n");
lf_putstr(file, "jmp_buf restart;\n");
lf_putstr(file, "cpu *processor = NULL;\n");
lf_putstr(file, "sim_cpu *cpu = NULL;\n");
lf_putstr(file, "unsigned_word nia = -1;\n");
lf_putstr(file, "instruction_word instruction = 0;\n");
if ((code & generate_with_icache)) {
@ -1039,7 +1039,7 @@ print_jump_until_stop_body(lf *file,
lf_putstr(file, "{\n");
lf_putstr(file, " int cpu_nr;\n");
lf_putstr(file, " for (cpu_nr = 0; cpu_nr < nr_cpus; cpu_nr++)\n");
lf_putstr(file, " cpu_flush_icache(processors[cpu_nr]);\n");
lf_putstr(file, " cpu_flush_icache(cpus[cpu_nr]);\n");
lf_putstr(file, "}\n");
}
@ -1055,8 +1055,8 @@ print_jump_until_stop_body(lf *file,
lf_putstr(file, "\n");
if (!generate_smp) {
lf_putstr(file, "processor = processors[0];\n");
lf_putstr(file, "nia = cpu_get_program_counter(processor);\n");
lf_putstr(file, "cpu = cpus[0];\n");
lf_putstr(file, "nia = cpu_get_program_counter(cpu);\n");
}
else {
lf_putstr(file, "current_cpu = psim_last_cpu(system);\n");
@ -1078,8 +1078,8 @@ print_jump_until_stop_body(lf *file,
}
lf_putstr(file, "instruction\n");
lf_putstr(file, " = vm_instruction_map_read(cpu_instruction_map(processor),\n");
lf_putstr(file, " processor, nia);\n");
lf_putstr(file, " = vm_instruction_map_read(cpu_instruction_map(cpu),\n");
lf_putstr(file, " cpu, nia);\n");
print_idecode_body(file, table, "/*IGORE*/");
/* print out a table of all the internals functions */
@ -1220,7 +1220,7 @@ print_idecode_validate(lf *file,
lf_printf(file, "\n");
lf_indent_suppress(file);
lf_printf(file, "#if defined(IS_FP_AVAILABLE)\n");
lf_printf(file, "/* Validate: FP available according to processor */\n");
lf_printf(file, "/* Validate: FP available according to cpu */\n");
lf_printf(file, "if (!IS_FP_AVAILABLE) {\n");
lf_indent(file, +2);
print_idecode_invalid(file, "return", invalid_fp_unavailable);
@ -1284,21 +1284,34 @@ print_idecode_issue_function_header(lf *file,
void
gen_idecode_h(lf *file,
insn_table *table,
cache_table *cache_rules)
gen_idecode_h (lf *file,
insn_table *table,
cache_table *cache_rules)
{
lf_printf(file, "typedef unsigned%d %sinstruction_word;\n",
insn_bit_size, global_name_prefix);
if ((code & generate_with_semantic_delayed_branch))
{
lf_printf (file, "typedef struct _instruction_address {\n");
lf_printf (file, " address_word ip; /* instruction pointer */\n");
lf_printf (file, " address_word dp; /* delayed-slot pointer */\n");
lf_printf (file, "} instruction_address;\n");
}
else
{
lf_printf (file, "typedef address_word instruction_address;\n");
}
lf_printf(file, "\n");
print_icache_struct(table, cache_rules, file);
lf_printf(file, "\n");
if ((code & generate_with_icache)) {
error("FIXME - idecode with icache incomplete");
}
else {
print_idecode_issue_function_header(file, 0/*is definition*/);
}
if ((code & generate_with_icache))
{
error("FIXME - idecode with icache incomplete");
}
else
{
print_idecode_issue_function_header(file, 0/*is definition*/);
}
}
@ -1328,7 +1341,7 @@ gen_idecode_c(lf *file,
cache_table *cache_rules)
{
/* the intro */
lf_printf(file, "#include \"engine.h\"\n");
lf_printf(file, "#include \"sim-main.h\"\n");
lf_printf(file, "#include \"%sidecode.h\"\n", global_name_prefix);
lf_printf(file, "#include \"%ssemantics.h\"\n", global_name_prefix);
lf_printf(file, "#include \"%sicache.h\"\n", global_name_prefix);

303
sim/igen/gen-semantics.c Normal file
View File

@ -0,0 +1,303 @@
/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "misc.h"
#include "lf.h"
#include "table.h"
#include "filter.h"
#include "ld-decode.h"
#include "ld-cache.h"
#include "ld-insn.h"
#include "igen.h"
#include "gen-semantics.h"
#include "gen-icache.h"
#include "gen-idecode.h"
static void
print_semantic_function_header(lf *file,
const char *basename,
insn_bits *expanded_bits,
int is_function_definition)
{
int indent;
lf_printf(file, "\n");
lf_print_function_type_function(file, print_semantic_function_type, "EXTERN_SEMANTICS",
(is_function_definition ? "\n" : " "));
indent = print_function_name(file,
basename,
expanded_bits,
function_name_prefix_semantics);
if (is_function_definition)
lf_indent(file, +indent);
else
lf_printf(file, "\n");
lf_printf(file, "(");
print_semantic_function_formal(file);
lf_printf(file, ")");
if (is_function_definition)
lf_indent(file, -indent);
else
lf_printf(file, ";");
lf_printf(file, "\n");
}
void
print_semantic_declaration(insn_table *entry,
lf *file,
void *data,
insn *instruction,
int depth)
{
if (generate_expanded_instructions) {
ASSERT(entry->nr_insn == 1);
print_semantic_function_header(file,
instruction->file_entry->fields[insn_name],
entry->expanded_bits,
0/* is not function definition*/);
}
else {
print_semantic_function_header(file,
instruction->file_entry->fields[insn_name],
NULL,
0/* is not function definition*/);
}
}
/* generate the semantics.c file */
void
print_idecode_invalid(lf *file,
const char *result,
invalid_type type)
{
const char *name;
switch (type) {
case invalid_illegal: name = "illegal"; break;
case invalid_fp_unavailable: name = "fp_unavailable"; break;
case invalid_wrong_slot: name = "wrong_slot"; break;
}
if ((code & generate_jumps))
lf_printf(file, "goto %s_%s;\n",
(code & generate_with_icache) ? "icache" : "semantic",
name);
else if ((code & generate_with_icache)) {
lf_printf(file, "%s %sicache_%s(", result, global_name_prefix, name);
print_icache_function_actual(file);
lf_printf(file, ");\n");
}
else {
lf_printf(file, "%s %ssemantic_%s(", result, global_name_prefix, name);
print_semantic_function_actual(file);
lf_printf(file, ");\n");
}
}
void
print_semantic_body(lf *file,
insn *instruction,
insn_bits *expanded_bits,
opcode_field *opcodes)
{
print_itrace(file, instruction->file_entry, 0/*put_value_in_cache*/);
/* validate the instruction, if a cache this has already been done */
if (!(code & generate_with_icache))
print_idecode_validate(file, instruction, opcodes);
/* generate the profiling call - this is delayed until after the
instruction has been verified */
lf_printf(file, "\n");
lf_indent_suppress(file);
lf_printf(file, "#if defined(WITH_MON)\n");
lf_printf(file, "/* monitoring: */\n");
lf_printf(file, "if (WITH_MON & MONITOR_INSTRUCTION_ISSUE) {\n");
lf_printf(file, " mon_issue(");
print_function_name(file,
instruction->file_entry->fields[insn_name],
NULL,
function_name_prefix_itable);
lf_printf(file, ", cpu, cia);\n");
lf_printf(file, "}\n");
lf_indent_suppress(file);
lf_printf(file, "#endif\n");
lf_printf(file, "\n");
/* determine the new instruction address */
lf_printf(file, "/* keep the next instruction address handy */\n");
if ((code & generate_with_semantic_returning_modified_nia_only))
lf_printf(file, "nia = -1;\n");
else if ((code & generate_with_semantic_delayed_branch)) {
lf_printf(file, "nia.ip = cia.dp; /* instruction pointer */\n");
lf_printf(file, "nia.dp = cia.dp + %d; /* delayed-slot pointer\n",
insn_bit_size / 8);
}
else
lf_printf(file, "nia = cia + %d;\n", insn_bit_size / 8);
/* if conditional, generate code to verify that the instruction
should be issued */
if (it_is("c", instruction->file_entry->fields[insn_options])
|| (code & generate_with_semantic_conditional_issue)) {
lf_printf(file, "\n");
lf_printf(file, "/* execute only if conditional passes */\n");
lf_printf(file, "if (IS_CONDITION_OK) {\n");
lf_indent(file, +2);
/* FIXME - need to log a conditional failure */
}
/* generate the code (or at least something */
lf_printf(file, "\n");
lf_printf(file, "/* semantics: */\n");
if (instruction->file_entry->annex != NULL) {
/* true code */
table_entry_print_cpp_line_nr(file, instruction->file_entry);
lf_printf(file, "{\n");
lf_indent(file, +2);
lf_print__c_code(file, instruction->file_entry->annex);
lf_indent(file, -2);
lf_printf(file, "}\n");
lf_print__internal_reference(file);
}
else if (it_is("nop", instruction->file_entry->fields[insn_flags])) {
lf_print__internal_reference(file);
}
else {
/* abort so it is implemented now */
table_entry_print_cpp_line_nr(file, instruction->file_entry);
lf_printf(file, "engine_error(system, \"%s:%d:0x%%08lx:%%s unimplemented\\n\",\n",
filter_filename(instruction->file_entry->file_name),
instruction->file_entry->line_nr);
lf_printf(file, " (long)cia, itable[MY_INDEX].name);\n");
lf_print__internal_reference(file);
}
/* Close off the conditional execution */
if (it_is("c", instruction->file_entry->fields[insn_options])
|| (code & generate_with_semantic_conditional_issue)) {
lf_indent(file, -2);
lf_printf(file, "}\n");
}
}
static void
print_c_semantic(lf *file,
insn *instruction,
insn_bits *expanded_bits,
opcode_field *opcodes,
cache_table *cache_rules)
{
lf_printf(file, "{\n");
lf_indent(file, +2);
print_my_defines(file, expanded_bits, instruction->file_entry);
lf_printf(file, "\n");
print_icache_body(file,
instruction,
expanded_bits,
cache_rules,
((code & generate_with_direct_access)
? define_variables
: declare_variables),
((code & generate_with_icache)
? get_values_from_icache
: do_not_use_icache));
lf_printf(file, "instruction_address nia;\n");
print_semantic_body(file,
instruction,
expanded_bits,
opcodes);
lf_printf(file, "return nia;\n");
/* generate something to clean up any #defines created for the cache */
if (code & generate_with_direct_access)
print_icache_body(file,
instruction,
expanded_bits,
cache_rules,
undef_variables,
((code & generate_with_icache)
? get_values_from_icache
: do_not_use_icache));
lf_indent(file, -2);
lf_printf(file, "}\n");
}
static void
print_c_semantic_function(lf *file,
insn *instruction,
insn_bits *expanded_bits,
opcode_field *opcodes,
cache_table *cache_rules)
{
/* build the semantic routine to execute the instruction */
print_semantic_function_header(file,
instruction->file_entry->fields[insn_name],
expanded_bits,
1/*is-function-definition*/);
print_c_semantic(file,
instruction,
expanded_bits,
opcodes,
cache_rules);
}
void
print_semantic_definition(insn_table *entry,
lf *file,
void *data,
insn *instruction,
int depth)
{
cache_table *cache_rules = (cache_table*)data;
if (generate_expanded_instructions) {
ASSERT(entry->nr_insn == 1
&& entry->opcode == NULL
&& entry->parent != NULL
&& entry->parent->opcode != NULL);
ASSERT(entry->nr_insn == 1
&& entry->opcode == NULL
&& entry->parent != NULL
&& entry->parent->opcode != NULL
&& entry->parent->opcode_rule != NULL);
print_c_semantic_function(file,
entry->insns,
entry->expanded_bits,
entry->parent->opcode,
cache_rules);
}
else {
print_c_semantic_function(file, instruction,
NULL, NULL,
cache_rules);
}
}

165
sim/igen/gen-support.c Normal file
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@ -0,0 +1,165 @@
/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "misc.h"
#include "lf.h"
#include "table.h"
#include "filter.h"
#include "ld-decode.h"
#include "ld-cache.h"
#include "ld-insn.h"
#include "igen.h"
#include "gen-semantics.h"
#include "gen-support.h"
static void
print_support_function_name(lf *file,
table_entry *function,
int is_function_definition)
{
if (it_is("internal", function->fields[insn_flags])) {
lf_print_function_type_function(file, print_semantic_function_type, "INLINE_SUPPORT",
(is_function_definition ? "\n" : " "));
print_function_name(file,
function->fields[function_name],
NULL,
function_name_prefix_semantics);
lf_printf(file, "\n(");
print_semantic_function_formal(file);
lf_printf(file, ")");
if (!is_function_definition)
lf_printf(file, ";");
lf_printf(file, "\n");
}
else {
/* map the name onto a globally valid name */
if (!is_function_definition && strcmp(global_name_prefix, "") != 0) {
lf_indent_suppress(file);
lf_printf(file, "#define %s %s%s\n",
function->fields[function_name],
global_name_prefix,
function->fields[function_name]);
}
lf_print_function_type(file,
function->fields[function_type],
"INLINE_SUPPORT",
(is_function_definition ? "\n" : " "));
lf_printf(file, "%s%s\n(",
global_name_prefix,
function->fields[function_name]);
if (generate_smp)
lf_printf(file, "sim_cpu *cpu");
else
lf_printf(file, "SIM_DESC sd");
if (strcmp(function->fields[function_param], "") != 0)
lf_printf(file, ", %s", function->fields[function_param]);
lf_printf(file, ")%s", (is_function_definition ? "\n" : ";\n"));
}
}
static void
support_h_function(insn_table *entry,
lf *file,
void *data,
table_entry *function)
{
ASSERT(function->fields[function_type] != NULL);
ASSERT(function->fields[function_param] != NULL);
print_support_function_name(file,
function,
0/*!is_definition*/);
lf_printf(file, "\n");
}
extern void
gen_support_h(insn_table *table,
lf *file)
{
/* output the definition of `_SD'*/
if (generate_smp) {
lf_printf(file, "#define _SD cpu\n");
lf_printf(file, "#define SD cpu->sd\n");
lf_printf(file, "#define CPU cpu\n");
}
else {
lf_printf(file, "#define _SD sd\n");
lf_printf(file, "#define SD sd\n");
lf_printf(file, "#define CPU (&sd->cpu)\n");
}
lf_printf(file, "\n");
/* output a declaration for all functions */
insn_table_traverse_function(table,
file, NULL,
support_h_function);
lf_printf(file, "\n");
lf_printf(file, "#if defined(SUPPORT_INLINE)\n");
lf_printf(file, "# if ((SUPPORT_INLINE & INCLUDE_MODULE)\\\n");
lf_printf(file, " && (SUPPORT_INLINE & INCLUDED_BY_MODULE))\n");
lf_printf(file, "# include \"%ssupport.c\"\n", global_name_prefix);
lf_printf(file, "# endif\n");
lf_printf(file, "#endif\n");
}
static void
support_c_function(insn_table *table,
lf *file,
void *data,
table_entry *function)
{
ASSERT (function->fields[function_type] != NULL);
print_support_function_name (file,
function,
1/*!is_definition*/);
table_entry_print_cpp_line_nr (file, function);
lf_printf (file, "{\n");
lf_indent (file, +2);
lf_print__c_code (file, function->annex);
if (it_is ("internal", function->fields[insn_flags]))
{
lf_printf (file, "sim_io_error (sd, \"Internal function must longjump\\n\");\n");
lf_printf (file, "memset (&cia, 0, sizeof cia);\n");
lf_printf (file, "return cia;\n");
}
lf_indent (file, -2);
lf_printf (file, "}\n");
lf_print__internal_reference (file);
lf_printf (file, "\n");
}
void
gen_support_c(insn_table *table,
lf *file)
{
lf_printf(file, "#include \"sim-main.h\"\n");
lf_printf(file, "#include \"%sidecode.h\"\n", global_name_prefix);
lf_printf(file, "#include \"%ssupport.h\"\n", global_name_prefix);
lf_printf(file, "\n");
/* output a definition (c-code) for all functions */
insn_table_traverse_function(table,
file, NULL,
support_c_function);
}

18
sim/igen/igen.c
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@ -64,13 +64,13 @@ print_semantic_function_formal(lf *file)
{
int nr;
if ((code & generate_with_icache))
nr = lf_printf(file, "SIM_DESC sd,\n %sidecode_cache *cache_entry,\n address_word cia",
nr = lf_printf(file, "SIM_DESC sd,\n %sidecode_cache *cache_entry,\n instruction_address cia",
global_name_prefix);
else if (generate_smp)
nr = lf_printf(file, "sim_cpu *cpu,\n %sinstruction_word instruction,\n address_word cia",
nr = lf_printf(file, "sim_cpu *cpu,\n %sinstruction_word instruction,\n instruction_address cia",
global_name_prefix);
else
nr = lf_printf(file, "SIM_DESC sd,\n %sinstruction_word instruction,\n address_word cia",
nr = lf_printf(file, "SIM_DESC sd,\n %sinstruction_word instruction,\n instruction_address cia",
global_name_prefix);
return nr;
}
@ -92,7 +92,7 @@ int
print_semantic_function_type(lf *file)
{
int nr;
nr = lf_printf(file, "address_word");
nr = lf_printf(file, "instruction_address");
return nr;
}
@ -108,7 +108,7 @@ print_icache_function_formal(lf *file)
else
nr += lf_printf(file, "SIM_DESC sd,\n");
nr += lf_printf(file, " %sinstruction_word instruction,\n", global_name_prefix);
nr += lf_printf(file, " address_word cia,\n");
nr += lf_printf(file, " instruction_address cia,\n");
nr += lf_printf(file, " %sidecode_cache *cache_entry", global_name_prefix);
return nr;
}
@ -257,7 +257,7 @@ print_itrace(lf *file,
lf_printf(file, " \"%s:%d:0x%%08lx:%%s\\n\", %s, %s);\n",
filter_filename(file_entry->file_name),
file_entry->line_nr,
"(long)cia",
((code & generate_with_semantic_delayed_branch) ? "(long)cia.ip" : "(long)cia"),
"itable[MY_INDEX].name");
lf_printf(file, "}\n");
lf_indent_suppress(file);
@ -450,6 +450,7 @@ main(int argc,
printf(" semantic-icache - include semantic code in cracking functions\n");
printf(" insn-in-icache - save original instruction when cracking\n");
printf(" default-nia-minus-one - instead of cia + insn-size\n");
printf(" delayed-branch - instead of cia + insn-size\n");
printf(" conditional-issue - conditionally issue each instruction\n");
printf(" validate-slot - perform slot verification as part of decode\n");
printf("\n");
@ -548,6 +549,11 @@ main(int argc,
}
else if (strcmp(optarg, "default-nia-minus-one") == 0) {
code |= generate_with_semantic_returning_modified_nia_only;
code &= ~generate_with_semantic_delayed_branch;
}
else if (strcmp(optarg, "delayed-branch") == 0) {
code |= generate_with_semantic_delayed_branch;
code &= ~generate_with_semantic_returning_modified_nia_only;
}
else if (strcmp(optarg, "conditional-issue") == 0) {
code |= generate_with_semantic_conditional_issue;

45
sim/tic80/.Sanitize Normal file
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@ -0,0 +1,45 @@
# .Sanitize for devo/sim/ppc.
# Each directory to survive it's way into a release will need a file
# like this one called "./.Sanitize". All keyword lines must exist,
# and must exist in the order specified by this file. Each directory
# in the tree will be processed, top down, in the following order.
# Hash started lines like this one are comments and will be deleted
# before anything else is done. Blank lines will also be squashed
# out.
# The lines between the "Do-first:" line and the "Things-to-keep:"
# line are executed as a /bin/sh shell script before anything else is
# done in this
Do-first:
# All files listed between the "Things-to-keep:" line and the
# "Files-to-sed:" line will be kept. All other files will be removed.
# Directories listed in this section will have their own Sanitize
# called. Directories not listed will be removed in their entirety
# with rm -rf.
Things-to-keep:
ChangeLog
Makefile.in
alu.h
config.in
configure
configure.in
cpu.h
dc
ic
insns
interp.c
sim-calls.c
sim-main.h
Things-to-lose:
Do-last:
# End of file.

0
sim/tic80/ChangeLog Normal file
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141
sim/tic80/Makefile.in Normal file
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@ -0,0 +1,141 @@
# Makefile for blah ...
# Copyright blah ...
## COMMON_PRE_CONFIG_FRAG
# These variables are given default values in COMMON_PRE_CONFIG_FRAG.
# We override the ones we need to here.
# Not all of these need to be mentioned, only the necessary ones.
# List of object files, less common parts.
SIM_OBJS = sim-endian.o sim-bits.o sim-config.o interp.o \
support.o idecode.o semantics.o itable.o \
sim-calls.o \
sim-events.o \
sim-core.o \
sim-io.o \
sim-utils.o \
sim-load.o \
sim-options.o \
sim-trace.o
# List of extra dependencies.
# Generally this consists of simulator specific files included by sim-main.h.
SIM_EXTRA_DEPS = itable.h idecode.h cpu.h alu.h
# List of generators
SIM_GEN=tmp-igen
# List of flags to always pass to $(CC).
SIM_WARNINGS=@sim_warnings@
SIM_ENDIAN=@sim_endian@
SIM_HOSTENDIAN=@sim_hostendian@
SIM_INLINE=@sim_inline@
SIM_RESERVED_BITS=@sim_reserved_bits@
SIM_EXTRA_CFLAGS = \
$(SIM_WARNINGS) \
$(SIM_ENDIAN) \
$(SIM_HOSTENDIAN) \
$(SIM_INLINE) \
$(SIM_RESERVED_BITS) \
-DWITH_TARGET_WORD_MSB=31
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
# Dependency of `clean' to clean any extra files.
SIM_EXTRA_CLEAN = clean-igen
## COMMON_POST_CONFIG_FRAG
# Rules need to build $(SIM_OBJS), plus whatever else the target wants.
# ... target specific rules ...
BUILT_SRC_FROM_IGEN = \
icache.h \
icache.c \
idecode.h \
idecode.c \
semantics.h \
semantics.c \
model.h \
model.c \
support.h \
support.c \
itable.h itable.c
$(BUILT_SRC_FROM_IGEN): tmp-igen
#
.PHONY: clean-igen
clean-igen:
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f tmp-igen tmp-insns
../igen/igen:
cd ../igen && $(MAKE)
tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen
cd ../igen && $(MAKE)
@echo "Generating short version ..."
../igen/igen \
-G direct-access \
-G delayed-branch \
-G omit-line-numbers \
-F short,emul \
-B 32 -H 31 \
-o $(srcdir)/dc \
-k $(srcdir)/ic \
-i $(srcdir)/insns \
-n icache.h -hc tmp-icache.h \
-n icache.c -c tmp-icache.c \
-n semantics.h -hs tmp-semantics.h \
-n semantics.c -s tmp-semantics.c \
-n idecode.h -hd tmp-idecode.h \
-n idecode.c -d tmp-idecode.c \
-n model.h -hm tmp-model.h \
-n model.c -m tmp-model.c \
-n support.h -hf tmp-support.h \
-n support.c -f tmp-support.c \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c
$(srcdir)/../../move-if-change tmp-icache.h icache.h
$(srcdir)/../../move-if-change tmp-icache.c icache.c
$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
$(srcdir)/../../move-if-change tmp-model.h model.h
$(srcdir)/../../move-if-change tmp-model.c model.c
$(srcdir)/../../move-if-change tmp-support.h support.h
$(srcdir)/../../move-if-change tmp-support.c support.c
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-igen
ENGINE_H = \
sim-main.h \
$(srcdir)/../common/sim-basics.h \
config.h \
$(srcdir)/../common/sim-config.h \
$(srcdir)/../common/sim-inline.h \
$(srcdir)/../common/sim-types.h \
$(srcdir)/../common/sim-bits.h \
$(srcdir)/../common/sim-endian.h \
itable.h \
idecode.h \
cpu.h \
alu.h \
$(srcdir)/../common/sim-alu.h \
$(srcdir)/../common/sim-core.h \
$(srcdir)/../common/sim-events.h \
idecode.o: $(ENGINE_H)
semantics.o: $(ENGINE_H)
interp.o: interp.c $(ENGINE_H)
sim-calls.o: sim-calls.c $(ENGINE_H)
cpu.o: cpu.c $(ENGINE_H)

34
sim/tic80/alu.h Normal file
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@ -0,0 +1,34 @@
#ifndef _TIC80_ALU_H_
#define _TIC80_ALU_H_
#define ALU_CARRY 0 /* FIXME */
#include "sim-alu.h"
#define ALU32_END(TARG) \
{ \
(TARG) = (unsigned32)alu_carry_val; /* FIXME */ \
}}
#define ALU_END(TARG) ALU32_END(TARG)
/* Bring data in from the cold */
#define IMEM(EA) sim_core_read_4(sd, sim_core_execute_map, (EA))
#define MEM(SIGN, EA, NR_BYTES) \
((SIGN##_##NR_BYTES) sim_core_read_##NR_BYTES(sd, sim_core_read_map, (EA)))
#define STORE(EA, NR_BYTES, VAL) \
do { \
sim_core_write_##NR_BYTES(sd, sim_core_write_map, (EA), (VAL)); \
} while (0)
#define long_immediate(VARIABLE) \
unsigned_word VARIABLE = MEM (unsigned, nia.ip, 4); \
nia.ip += sizeof (instruction_word); \
nia.dp += sizeof (instruction_word);
#endif

35
sim/tic80/config.in Normal file
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@ -0,0 +1,35 @@
/* config.in. Generated automatically from configure.in by autoheader. */
/* Define as the return type of signal handlers (int or void). */
#undef RETSIGTYPE
/* Define if your processor stores words with the most significant
byte first (like Motorola and SPARC, unlike Intel and VAX). */
#undef WORDS_BIGENDIAN
/* Define if you have the getrusage function. */
#undef HAVE_GETRUSAGE
/* Define if you have the time function. */
#undef HAVE_TIME
/* Define if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define if you have the <sys/resource.h> header file. */
#undef HAVE_SYS_RESOURCE_H
/* Define if you have the <sys/time.h> header file. */
#undef HAVE_SYS_TIME_H
/* Define if you have the <time.h> header file. */
#undef HAVE_TIME_H
/* Define if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H

1961
sim/tic80/configure vendored Executable file
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File diff suppressed because it is too large Load Diff

19
sim/tic80/configure.in Normal file
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@ -0,0 +1,19 @@
dnl Process this file with autoconf to produce a configure script.
sinclude(../common/aclocal.m4)
AC_PREREQ(2.5)dnl
AC_INIT(Makefile.in)
SIM_AC_COMMON
dnl Options available in this module
SIM_AC_OPTION_INLINE(0)
SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_WARNINGS
SIM_AC_OPTION_RESERVED_BITS(1)
dnl For UNIX emulation
AC_CHECK_HEADERS(stdlib.h unistd.h string.h strings.h)
SIM_AC_OUTPUT

7
sim/tic80/cpu.h Normal file
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@ -0,0 +1,7 @@
typedef struct _sim_cpu {
unsigned_word reg[32];
sim_cpu_base base;
instruction_address cia;
} sim_cpu;
#define GPR(N) ((CPU)->reg[N])

1
sim/tic80/dc Normal file
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@ -0,0 +1 @@
switch: 21: 12: 21: 12

25
sim/tic80/ic Normal file
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@ -0,0 +1,25 @@
compute:Dest:Dest:
compute:Dest:rDest:signed32 *:(&(CPU)->reg[Dest])
#
compute:Source1:Source1:
compute:Source1:rSource1:signed32:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
#
compute:Source2:Source2:
compute:Source2:rSource2:signed32:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
#
compute:Source:Source:
compute:Source:rSource:signed32:(Source == 0 ? 0 : (CPU)->reg[Source])
#
compute:IndOff:IndOff:
compute:IndOff:rIndOff:signed32:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
#
# Trap Number
compute:UTN:UTN:
compute:INDTR:INDTR:
compute:INDTR:UTN:unsigned32:(INDTR == 0 ? 0 : (CPU)->reg[INDTR])
#
compute:A:A:
#
compute:SI:SI:
compute:SI:SignedOffset:unsigned32:SEXT (SI, 14)
compute:BITNUM:BITNUM:

610
sim/tic80/insns Normal file
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@ -0,0 +1,610 @@
// The following is called when ever an illegal instruction is
// encountered
::internal::illegal
engine_error (sd, cia, "illegal instruction at 0x%lx", cia.ip);
// Signed Integer Add - add source1, source2, dest
void::function::do_add:signed_word *rDest, signed_word Source1, signed_word Source2
ALU_BEGIN (Source1);
ALU_ADD (Source2);
ALU_END (*rDest);
31.Dest,26.Source2,21.0b101100,15.0,14.SI::::add i
do_add (_SD, rDest, SI, rSource2);
31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
do_add (_SD, rDest, rSource1, rSource2);
31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
long_immediate (LSI);
do_add (_SD, rDest, LSI, rSource2);
// Unsigned Integer Add - addu source1, source2, dest
void::function::do_addu:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
*rDest = Source1 + Source2;
31.Dest,26.Source2,21.0b101100,15.1,14.SI::::addu i
do_addu (_SD, rDest, SI, rSource2);
31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
do_addu (_SD, rDest, rSource1, rSource2);
31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
long_immediate (LSI);
do_addu (_SD, rDest, LSI, rSource2);
#void::function::do_and:unsigned_word *rDest, unsigned_word source1, unsigned_word source2
# *rD = source1 & source2;
// and, and.tt
#31.Dest,26.Source2,21.0b0010001,14.SI::::and.tt i
# do_and (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b110010001,0,11./,4.Source1::::and.tt r
# do_and (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b110010001,1,11./::::and.tt l
# do_and (_SD, *rDest, LSI, rSource2);
// and.ff
#31.Dest,26.Source2,21.0b0010001,14.SI::::and.ff i
# do_and (_SD, *rDest, ~SI, ~rSource2);
#31.Dest,26.Source2,21.0b110010001,0,11./,4.Source1::::and.ff r
# do_and (_SD, *rDest, ~rSource1, ~rSource2);
#31.Dest,26.Source2,21.0b110010001,1,11./::::and.ff l
# do_and (_SD, *rDest, ~LSI, ~rSource2);
// and.ft
#31.Dest,26.Source2,21.0b0010001,14.SI::::and.ft i
# do_and (_SD, *rDest, ~SI, rSource2);
#31.Dest,26.Source2,21.0b110010001,0,11./,4.Source1::::and.ft r
# do_and (_SD, *rDest, ~rSource1, rSource2);
#31.Dest,26.Source2,21.0b110010001,1,11./::::and.ft l
# do_and (_SD, *rDest, ~LSI, rSource2);
// and.tf
#31.Dest,26.Source2,21.0b0010001,14.SI::::and.tf i
# do_and (_SD, *rDest, SI, ~rSource2);
#31.Dest,26.Source2,21.0b110010001,0,11./,4.Source1::::and.tf r
# do_and (_SD, *rDest, rSource1, ~rSource2);
#31.Dest,26.Source2,21.0b110010001,1,11./::::and.tf l
# do_and (_SD, *rDest, LSI, ~rSource2);
// bbo.[a]
#void::function::do_bbo:int annul, int bitnum, unsigned_word offset, unsigned_word source
# sim_io_error ("bbo");
#31.BM,26.Source2,21.0b100101,A,14.SI14::::and.tf i
# do_bbo (_SD, A, SI, rSource2);
#31.BM,26.Source2,21.0b11100101,A,0,11./,4.Source1::::and.tf r
# do_bbo (_SD, A, rSource1, rSource2);
#31.BM,26.Source2,21.0b11100101,A,1,11./::::and.tf l
# do_bbo (_SD, A, LSI, rSource2);
// bbz[.a]
instruction_address::function::do_bbz:instruction_address cia, instruction_address nia, int bitnum, unsigned_word source, int annul, unsigned_word offset
if (!MASKED32 (source, bitnum, bitnum))
{
if (annul)
nia.ip = -1;
nia.dp = cia.ip + 4 * offset;
}
return nia;
31.BITNUM,26.Source,21.0b100100,15.A,14.SI::::bbz i
nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, SignedOffset);
31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, rIndOff);
31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
long_immediate (LSI);
nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, LSI);
// bcnd[.a]
#void::function::do_bcnd:int annul, int bitnum, unsigned_word offset, unsigned_word source
# sim_io_error ("bcnd");
#31.BM,26.Source2,21.0b100110,A,14.SI::::and.tf i
# do_bcnd (_SD, A, SI, rSource2);
#31.BM,26.Source2,21.0b11100110,A,0,11./,4.Source1::::and.tf r
# do_bcnd (_SD, A, rSource1, rSource2);
#31.BM,26.Source2,21.0b11100110,A,1,11./::::and.tf l
# do_bcnd (_SD, A, LSI, rSource2);
// br[.a] - see bbz[.a]
// brcr
#void::function::do_brcr:unsigned_word offset
# sim_io_error ("brcr");
#31.//,27.0,26.//,21.0b0000110,14.CRN::::and.tf i
# do_brcr (_SD, rCRN_val);
#31.//,27.0,26.//,21.0b110000110,0,11./,4.Source1::::and.tf r
# do_brcr (_SD, CRN[rSource1]);
#31.//,27.0,26.//,21.0b110000110,1,11./::::and.tf l
# do_brcr (_SD, CRN[SL]);
// bsr[.a]
#void::function::do_bsr:int annul, int bitnum, unsigned_word offset, unsigned_word source
# sim_io_error ("bsr");
#31.Link,26.//,21.0b100000,A,14.SI::::and.tf i
# do_bsr (_SD, A, LK, SI);
#31.Link,26.//,21.0b11100000,A,0,11./,4.Source1::::and.tf r
# do_bsr (_SD, A, LK, rSource1);
#31.Link,26.//,21.0b11100000,A,1,11./::::and.tf l
# do_bsr (_SD, A, LK, SL);
// cmnd
#31./,21.0b0000010,14.UI::::cmnd i
#31./,21.0b110000010,12.0,11./,4.Source1::::cmnd r
#31./,21.0b110000010,12.1,11./::::cmnd l
// cmp
#void::function::do_cmp:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("cmp");
#31.Dest,26.Source2,21.0b1010000,14.SI::::cmp i
# do_cmp (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b111010000,0,11./,4.Source1::::cmp r
# do_cmp (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b111010000,1,11./::::cmp l
# do_cmp (_SD, *rDest, LSI, rSource2);
// dcache
#31./,27.F,26.S1,21.0b0111,M,00,14.SO::::dcache i
#31./,27.F,26.S1,21.0b110111,M,00,12.0,11./,4.Source1::::dcache r
#31./,27.F,26.S1,21.0b110111,M,00,12.1,11./::::dcache l
// dld[{.b|.h|.d}]
#void::function::do_dld:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("dld");
#31.Dest,26.Source2,21.0b110100,m,sz,0,S,1,9./,4.Source1::::dld r
# do_dld (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11110100,m,sz,1,S,1,9./::::dld l
# do_dld (_SD, *rDest, LSI, rSource2);
// dld.u[{.b|.h|.d}]
#void::function::do_dld_u:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("dld.u");
#31.Dest,26.Source2,21.0b110101,m,sz,0,S,1,9./,4.Source1::::dld.u r
# do_dld_u (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11110101,m,sz,1,S,1,9./::::dld.u l
# do_dld_u (_SD, *rDest, LSI, rSource2);
// dst[{.b|.h|.d}]
#void::function::do_dst:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("dst");
#31.Dest,26.Source2,21.0b110110,m,sz,0,S,1,9./,4.Source1::::dst r
# do_dst (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11110110,m,sz,1,S,1,9./::::dst l
# do_dst (_SD, *rDest, LSI, rSource2);
// estop
#31./,21.0b1111111,1,0,0,11./::::estop
// etrap
#31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
#31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
#31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
// exts - see shift.ds
// extu - see shift.dz
// fadd.{s|d}{s|d}{s|d}
#void::function::do_fadd:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fadd");
#31.Dest,26.Source2,21.0b111110000,0,r,PD,P2,P1,4.Source1::::fadd r
# do_fadd (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110000,1,r,PD,P2,P1,4./::::fadd l
# do_fadd (_SD, *rDest, LSI, rSource2);
// fcmp.{s|d}{s|d}{s|d}
#void::function::do_fcmp:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fcmp");
#31.Dest,26.Source2,21.0b111110101,0,/,00,P2,P1,4.Source1::::fcmp r
# do_fcmp (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110101,1,/,00,P2,P1,4./::::fcmp l
# do_fcmp (_SD, *rDest, LSI, rSource2);
// fdiv.{s|d}{s|d}{s|d}
#void::function::do_fdiv:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fdiv");
#31.Dest,26.Source2,21.0b111110011,0,/,PD,P2,P1,4.Source1::::fdiv r
# do_fdiv (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110011,1,/,PD,P2,P1,4./::::fdiv l
# do_fdiv (_SD, *rDest, LSI, rSource2);
// fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
#void::function::do_fmpy:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fmpy");
#31.Dest,26.Source2,21.0b111110010,0,/,PD,P2,P1,4.Source1::::fmpy r
# do_fmpy (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110010,1,/,PD,P2,P1,4./::::fmpy l
# do_fmpy (_SD, *rDest, LSI, rSource2);
// frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
#void::function::do_frndm:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("frndm");
#31.Dest,26.Source2,21.0b111110100,0,r,PD,11,P1,4.Source1::::frndm r
# do_frndm (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110100,1,r,PD,11,P1,4./::::frndm l
# do_frndm (_SD, *rDest, LSI, rSource2);
// frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
#void::function::do_frndn:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("frndn");
#31.Dest,26.Source2,21.0b111110100,0,r,PD,00,P1,4.Source1::::frndn r
# do_frndn (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110100,1,r,PD,00,P1,4./::::frndn l
# do_frndn (_SD, *rDest, LSI, rSource2);
// frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
#void::function::do_frndp:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("frndp");
#31.Dest,26.Source2,21.0b111110100,0,r,PD,10,P1,4.Source1::::frndp r
# do_frndp (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110100,1,r,PD,10,P1,4./::::frndp l
# do_frndp (_SD, *rDest, LSI, rSource2);
// frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
#void::function::do_frndz:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("frndz");
#31.Dest,26.Source2,21.0b111110100,0,r,PD,01,P1,4.Source1::::frndz r
# do_frndz (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110100,1,r,PD,01,P1,4./::::frndz l
# do_frndz (_SD, *rDest, LSI, rSource2);
// fsqrt.{s|d}{s|d}{s|d}
#void::function::do_fsqrt:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fsqrt");
#31.Dest,26.Source2,21.0b111110111,0,/,PD,//,P1,4.Source1::::fsqrt r
# do_fsqrt (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110111,1,/,PD,//,P1,4./::::fsqrt l
# do_fsqrt (_SD, *rDest, LSI, rSource2);
// fsub.{s|d}{s|d}{s|d}
#void::function::do_fsub:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("fsub");
#31.Dest,26.Source2,21.0b111110001,0,r,PD,P2,P1,4.Source1::::fsub r
# do_fsub (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11111110001,1,r,PD,P2,P1,4./::::fsub l
# do_fsub (_SD, *rDest, LSI, rSource2);
// illop
#31./,21.0b0000000,14./::::illop
#31./,21.0b111111111,12./::::illop l
// ins - see shift.im
// jsr[.a]
#void::function::do_jsr:int annul, int bitnum, unsigned_word offset, unsigned_word source
# sim_io_error ("jsr");
#31.Link,26.Base,21.0b100010,A,14.SI::::and.tf i
# do_jsr (_SD, A, LK, SI);
#31.Link,26.Base,21.0b11100010,A,0,11./,4.Source1::::and.tf r
# do_jsr (_SD, A, LK, rSource1);
#31.Link,26.Base,21.0b11100010,A,1,11./::::and.tf l
# do_jsr (_SD, A, LK, SL);
// ld[{.b.h.d}]
#void::function::do_ld:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("dld.u");
#31.Dest,26.Base,21.0b0100,m,sz,14.SI::::ld i
# do_ld (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Base,21.0b110100,m,sz,0,S,0,9./::::ld r
# do_ld (_SD, *rDest, LSI, rSource2);
#31.Dest,26.Base,21.0b110100,m,sz,1,S,0,9./::::ld l
# do_ld (_SD, *rDest, LSI, rSource2);
// ld.u[{.b.h.d}]
#void::function::do_ld_u:unsigned_word *rDest, unsigned_word Source1, unsigned_word Source2
# sim_io_error ("dld.u");
#31.Dest,26.Base,21.0b0100,m,sz,14.SI::::ld.u i
# do_ld_u (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Base,21.0b110100,m,sz,0,S,0,9./::::ld.u r
# do_ld_u (_SD, *rDest, LSI, rSource2);
#31.Dest,26.Base,21.0b110100,m,sz,1,S,0,9./::::ld.u l
# do_ld_u (_SD, *rDest, LSI, rSource2);
// lmo
#31.Dest,26.Source,111111000,0,11./::::lmo
// nop
#31.0,26.0,21.0b0000100,14.0::::nop
#void::function::do_or:unsigned_word *rDest, unsigned_word source1, unsigned_word source2
# *rD = source1 | source2;
// or, or.tt
#31.Dest,26.Source2,21.0b0010111,14.SI::::or.tt i
# do_or (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b110010111,0,11./,4.Source1::::or.tt r
# do_or (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b110010111,1,11./::::or.tt l
# do_or (_SD, *rDest, LSI, rSource2);
// or.ff
#31.Dest,26.Source2,21.0b0011110,14.SI::::or.ff i
# do_or (_SD, *rDest, ~SI, ~rSource2);
#31.Dest,26.Source2,21.0b110011110,0,11./,4.Source1::::or.ff r
# do_or (_SD, *rDest, ~rSource1, ~rSource2);
#31.Dest,26.Source2,21.0b110011110,1,11./::::or.ff l
# do_or (_SD, *rDest, ~LSI, ~rSource2);
// or.ft
#31.Dest,26.Source2,21.0b0011101,14.SI::::or.ft i
# do_or (_SD, *rDest, ~SI, rSource2);
#31.Dest,26.Source2,21.0b110011101,0,11./,4.Source1::::or.ft r
# do_or (_SD, *rDest, ~rSource1, rSource2);
#31.Dest,26.Source2,21.0b110011101,1,11./::::or.ft l
# do_or (_SD, *rDest, ~LSI, rSource2);
// or.tf
#31.Dest,26.Source2,21.0b0011011,14.SI::::or.tf i
# do_or (_SD, *rDest, SI, ~rSource2);
#31.Dest,26.Source2,21.0b110011011,0,11./,4.Source1::::or.tf r
# do_or (_SD, *rDest, rSource1, ~rSource2);
#31.Dest,26.Source2,21.0b110011011,1,11./::::or.tf l
# do_or (_SD, *rDest, LSI, ~rSource2);
// rdcr
#31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
#31.Dest,26.0,21.0b110000100,0,11./,4.INDCR::::rdcr r
#31.Dest,26.0,21.0b110000100,1,11./::::rdcr l
// rmo
#31.Dest,26.Source,21.0b111111001,0,11./::::rmo
// rotl - see shift.dz
//rotr - see shift.dz
// shl - see shift.iz
// sl.{d|e|i}{m|s|z}
#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.0,0,9.EndMask::::4.Rotate:sl i
#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.0,0,9.EndMask::::4.RotReg:sl r
// sli.{d|e|i}{m|s|z}
#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,0,9.EndMask::::4.Rotate:sli i
#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,0,9.EndMask::::4.RotReg:sli r
// sr.{d|e|i}{m|s|z}
#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.0,1,9.EndMask::::4.Rotate:sr i
#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.0,1,9.EndMask::::4.RotReg:sr r
// sra - see sr.es
// sri.{d|e|i}{m|s|z}
#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,1,9.EndMask::::4.Rotate:sri i
#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,1,9.EndMask::::4.RotReg:sri r
// srl - see sr.ez
// st[{.b|.h|.d}]
#31.Dest,26.Base,21.0b0110,m,sz,14.SO::::st i
#31.Dest,26.Base,21.0b110110,m,sz,0,S,0,14./,4.IO::::st i
#31.Dest,26.Base,21.0b110110,m,sz,1,S,0,14./::::st i
// sub
#void::function::do_sub:signed_word *rDest, signed_word Source1, signed_word Source2
# ALU_BEGIN (Source1);
# ALU_SUB (Source2);
# ALU_END (*rD);
#31.Dest,26.Source2,21.0b101100,0,14.SI::::sub i
# do_sub (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,0,11./,4.Source1::::sub r
# do_sub (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,1,11./::::sub l
# do_sub (_SD, *rDest, LSI, rSource2);
// subu
#void::function::do_subu:signed_word *rDest, signed_word Source1, signed_word Source2
# ALU_BEGIN (Source1);
# ALU_SUBU (Source2);
# ALU_END (*rD);
#31.Dest,26.Source,21.0b101100,0,14.SI::::subu i
# do_subu (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source,21.0b11101100,0,0,11./,4.Source1::::subu r
# do_subu (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source,21.0b11101100,0,1,11./::::subu l
# do_subu (_SD, *rDest, LSI, rSource2);
// swcr
#void::function::do_swcr:signed_word *rDest, signed_word Source1, signed_word Source2
#31.Dest,26.Source,21.0b000010,1,14.SI::::swcr i
# do_swcr (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source,21.0b11000010,1,0,11./,4.INDCR::::swcr r
# do_swcr (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source,21.0b11000010,1,1,11./::::swcr l
# do_swcr (_SD, *rDest, LSI, rSource2);
// trap
void::function::do_trap:instruction_address cia, unsigned_word trap_number
if (trap_number == 72)
{
switch (GPR(2))
{
case 1: /* EXIT */
{
engine_halt (SD, cia, sim_exited, GPR(3));
break;
}
case 4: /* WRITE */
{
int i;
if (GPR(3) != 1)
engine_error (SD, cia, "write to invalid fid %d", GPR(3));
for (i = 0; i < GPR(5); i++)
{
char c;
c = MEM (unsigned, GPR(4) + i, 1);
sim_io_write_stdout (SD, &c, 1);
}
GPR(2) = GPR(5);
break;
}
default:
engine_error (SD, cia, "unknown trap %d", GPR(2));
}
}
31./,27.0,26./,21.0b0000001,14.UTN::::trap i
do_trap (_SD, cia, UTN);
31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
do_trap (_SD, cia, UTN);
31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
long_immediate (UTN);
do_trap (_SD, cia, UTN);
// vadd.{s|d}{s|d}
#void::function::do_vadd:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vadd r
# do_vadd (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vadd l
# do_vadd (_SD, *rDest, LSI, rSource2);
// vld{0|1}.{s|d}
#31.Dest,26.*,21.0b11110,18.*,10.1,S,**,p,******::::vld r
// vmac.ss{s|d}
#31.*,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmac.ss ra
#31.Dest,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmac.ss rr
#31.*,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmac.ss ia
#31.Dest,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmac.ss ir
// vmpy.{s|d}{s|d}
#void::function::do_vmpy:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vmpy r
# do_vmpy (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vmpy l
# do_vmpy (_SD, *rDest, LSI, rSource2);
// vmsc.ss{s|d}
#31.*,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmsc.ss ra
#31.Dest,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmsc.ss rr
#31.*,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmsc.ss ia
#31.Dest,26.Source2,21.0b11110,a,110,0,a,**,Z,r,*,r,4.Source1::::vmsc.ss ir
// vmsub.{s|d}{s|d}
#void::function::do_vmsub:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vmsub r
# do_vmsub (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vmsub l
# do_vmsub (_SD, *rDest, LSI, rSource2);
// vrnd.{s|d}{s|d}
#void::function::do_vrnd:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vrnd r
# do_vrnd (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vrnd l
# do_vrnd (_SD, *rDest, LSI, rSource2);
// vrnd.{i|u}{s|d}
#void::function::do_vrnd:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vrnd r
# do_vrnd (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vrnd l
# do_vrnd (_SD, *rDest, LSI, rSource2);
// vst.{s|d}
#31.Source,26.*,21.0b1110,16.*,10.0,9.S,**,1,******::::vst
// vsub.{i|u}{s|d}
#void::function::do_vsub:signed_word *rDest, signed_word Source1, signed_word Source2
#31.*,26.Dest,21.0b11110,r,000,r,*,**,7.PD,6.*,5.P1,4.Source::::vsub r
# do_vsub (_SD, *rDest, SI, rSource2);
#31.*,26.Dest,21.0b1111110,r,000,r,*,**,7.PD,6.*,5.P1,4./::::vsub l
# do_vsub (_SD, *rDest, LSI, rSource2);
// wrcr
#void::function::do_wrcr:signed_word *rDest, signed_word Source1, signed_word Source2
#31.Dest,26.Source,21.0b000010,1,14.SI::::wrcr i
# do_wrcr (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source,21.0b11000010,1,0,11./,4.INDCR::::wrcr r
# do_wrcr (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source,21.0b11000010,1,1,11./::::wrcr l
# do_wrcr (_SD, *rDest, LSI, rSource2);
// xnor
#void::function::do_xnor:signed_word *rDest, signed_word Source1, signed_word Source2
# ALU_BEGIN (Source1);
# ALU_XNOR (Source2);
# ALU_END (*rD);
#31.Dest,26.Source2,21.0b101100,0,14.SI::::xnor i
# do_xnor (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,0,11./,4.Source1::::xnor r
# do_xnor (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,1,11./::::xnor l
# do_xnor (_SD, *rDest, LSI, rSource2);
// xor
#void::function::do_xor:signed_word *rDest, signed_word Source1, signed_word Source2
# ALU_BEGIN (Source1);
# ALU_XOR (Source2);
# ALU_END (*rD);
#31.Dest,26.Source2,21.0b101100,0,14.SI::::xor i
# do_xor (_SD, *rDest, SI, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,0,11./,4.Source1::::xor r
# do_xor (_SD, *rDest, rSource1, rSource2);
#31.Dest,26.Source2,21.0b11101100,0,1,11./::::xor l
# do_xor (_SD, *rDest, LSI, rSource2);

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/* This file is part of the GDB simulators.
Copyright (C) 1997, Free Software Foundation
Condtributed by Cyngnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "sim-main.h"
#include "idecode.h"
#include <signal.h>
void
engine_init (SIM_DESC sd)
{
memset (&STATE_CPU (sd, 0)->reg, 0, sizeof STATE_CPU (sd, 0)->reg);
memset (&STATE_CPU (sd, 0)->cia, 0, sizeof STATE_CPU (sd, 0)->cia);
CPU_STATE (STATE_CPU (sd, 0)) = sd;
}
/* Mechanisms for stopping/restarting the simulation */
void
engine_error (SIM_DESC sd,
instruction_address cia,
const char *fmt,
...)
{
va_list ap;
va_start (ap, fmt);
sim_io_evprintf (sd, fmt, ap);
va_end (ap);
if (sd->halt_ok)
{
sim_io_printf (sd, "\n");
engine_halt (sd, cia, sim_signalled, SIGABRT);
}
else
sim_io_error (sd, " - aborting simulation");
}
void
engine_halt (SIM_DESC sd,
instruction_address cia,
enum sim_stop reason,
int siggnal)
{
if (!sd->halt_ok)
sim_io_error (sd, "engine_halt - bad longjmp");
sd->reason = reason;
sd->siggnal = siggnal;
sd->halt_ok = 0;
sd->restart_ok = 0;
sd->cpu.cia = cia;
longjmp (sd->path_to_halt, 1);
}
void
engine_restart (SIM_DESC sd,
instruction_address cia)
{
if (!sd->restart_ok)
sim_io_error (sd, "engine_restart - bad longjmp");
sd->restart_ok = 0;
sd->cpu.cia = cia;
longjmp(sd->path_to_restart, 1);
}
void
engine_run_until_stop (SIM_DESC sd,
volatile int *keep_running)
{
if (!setjmp (sd->path_to_halt))
{
instruction_address cia;
sd->halt_ok = 1;
setjmp (sd->path_to_restart);
sd->restart_ok = 1;
cia = STATE_CPU (sd, 0)->cia;
do
{
if (cia.ip == -1)
{
/* anulled instruction */
cia.ip = cia.dp;
cia.dp = cia.dp + sizeof (instruction_word);
}
else
{
instruction_word insn = IMEM (cia.ip);
cia = idecode_issue (sd, insn, cia);
}
}
while (*keep_running);
engine_halt (sd, cia, sim_stopped, SIGINT);
}
}

212
sim/tic80/sim-calls.c Normal file
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/* This file is part of the program psim.
Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <signal.h> /* FIXME - should be machine dependant version */
#include <stdarg.h>
#include <ctype.h>
#include "bfd.h"
#include "sim-main.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#define SIM_ADDR unsigned
/* Structures used by the simulator, for gdb just have static structures */
struct sim_state simulation = { 0 };
SIM_DESC
sim_open (SIM_OPEN_KIND kind, char **argv)
{
/*FIXME - later make these configurable */
static void *eit_ram;
static int sizeof_eit_ram = 0x1000;
STATE_OPEN_KIND (&simulation) = kind;
/* establish the simulator configuration */
sim_config (&simulation,
LITTLE_ENDIAN/*d30v always big endian*/);
if (sim_pre_argv_init (&simulation, argv[0]) != SIM_RC_OK)
return 0;
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (&simulation, argv) != SIM_RC_OK)
return 0;
engine_init(&simulation);
/* external memory */
sim_core_attach(&simulation,
attach_raw_memory,
access_read_write_exec,
0, 0x2000000, 0x100000, NULL, NULL);
/* FIXME: for now */
return (SIM_DESC) &simulation;
}
/* NOTE: sim_size is going away */
void sim_size (int i);
void
sim_size (int i)
{
sim_io_error (NULL, "unexpected call to sim_size()");
}
void
sim_close (SIM_DESC sd, int quitting)
{
}
SIM_RC
sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty)
{
extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
bfd *prog_bfd;
prog_bfd = sim_load_file (sd, STATE_MY_NAME (sd),
STATE_CALLBACK (sd),
prog,
/* pass NULL for abfd, we always open our own */
NULL,
STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG);
if (prog_bfd == NULL)
return SIM_RC_FAIL;
sim_analyze_program (sd, prog_bfd);
return SIM_RC_OK;
}
void
sim_kill (SIM_DESC sd)
{
}
int
sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
{
sim_io_error (sd, "sim_read");
return 0;
}
int
sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
{
return sim_core_write_buffer (sd, sim_core_write_map,
buf, mem, length);
}
void
sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf)
{
sim_io_error (sd, "sim_fetch_register");
}
void
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf)
{
sim_io_error (sd, "sim_info");
}
void
sim_info (SIM_DESC sd, int verbose)
{
}
SIM_RC
sim_create_inferior (SIM_DESC sd,
char **argv,
char **envp)
{
STATE_CPU (sd, 0)->cia.ip = STATE_START_ADDR(sd);
STATE_CPU (sd, 0)->cia.dp = (STATE_START_ADDR(sd)
+ sizeof (instruction_word));
return SIM_RC_OK;
}
volatile int keep_running = 1;
void
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
{
*reason = simulation.reason;
*sigrc = simulation.siggnal;
keep_running = 1; /* ready for next run */
}
int
sim_stop (SIM_DESC sd)
{
keep_running = 0;
return 1;
}
void
sim_resume (SIM_DESC sd, int step, int siggnal)
{
/* keep_running = 1 - in sim_stop_reason */
if (step)
keep_running = 0;
engine_run_until_stop(sd, &keep_running);
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
sim_io_error (sd, "sim_do_command - unimplemented");
}
void
sim_set_callbacks (SIM_DESC sd, host_callback *callback)
{
STATE_CALLBACK (&simulation) = callback;
}

107
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/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SIM_MAIN_H_
#define _SIM_MAIN_H_
#include "sim-basics.h"
#include "sim-inline.h"
#include "sim-types.h"
#include "sim-bits.h"
#include "sim-endian.h"
/* These are generated files. */
#include "itable.h"
#include "idecode.h"
#include "idecode.h"
#include "cpu.h"
#include "alu.h"
#include "sim-core.h"
#include "sim-events.h"
#include "sim-io.h"
struct sim_state {
/* real time */
sim_events events;
/* memory and IO */
sim_core core;
/* escape route for inner functions */
int halt_ok;
jmp_buf path_to_halt;
int restart_ok;
jmp_buf path_to_restart;
/* status from last halt */
enum sim_stop reason;
int siggnal;
/* the processors proper */
sim_cpu cpu;
#define STATE_CPU(sd, n) (&(sd)->cpu)
/* The base class. */
sim_state_base base;
};
/* (re) initialize the simulator */
extern void engine_init
(SIM_DESC sd);
/* Mechanisms for stopping/restarting the simulation */
extern void engine_error
(SIM_DESC sd,
instruction_address cia,
const char *fmt,
...);
extern void engine_halt
(SIM_DESC sd,
instruction_address cia,
enum sim_stop reason,
int siggnal);
extern void engine_restart
(SIM_DESC sd,
instruction_address cia);
/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
thing (others later) */
extern void engine_run_until_stop
(SIM_DESC sd,
volatile int *keep_running);
#endif