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PowerPC VLE

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VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
This commit is contained in:
Alan Modra 2016-06-07 22:04:38 +09:30
parent 2091da296f
commit 14b57c7c6a
18 changed files with 3790 additions and 3644 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
bfd/ChangeLog
View File

@ -1,3 +1,19 @@
2016-06-07 Alan Modra <amodra@gmail.com>
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
2016-06-06 H.J. Lu <hongjiu.lu@intel.com>
* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.

7
bfd/bfd-in.h
View File

@ -951,13 +951,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
extern bfd_boolean elf32_tic6x_fix_exidx_coverage
(struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
/* PowerPC @tls opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tls_transform
(unsigned int, unsigned int);
/* PowerPC @tprel opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
extern void bfd_elf64_aarch64_init_maps
(bfd *);

7
bfd/bfd-in2.h
View File

@ -958,13 +958,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
extern bfd_boolean elf32_tic6x_fix_exidx_coverage
(struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
/* PowerPC @tls opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tls_transform
(unsigned int, unsigned int);
/* PowerPC @tprel opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
extern void bfd_elf64_aarch64_init_maps
(bfd *);

4
bfd/cpu-powerpc.c
View File

@ -35,6 +35,10 @@ powerpc_compatible (const bfd_arch_info_type *a,
default:
return NULL;
case bfd_arch_powerpc:
if (a->mach == bfd_mach_ppc_vle && b->bits_per_word == 32)
return a;
if (b->mach == bfd_mach_ppc_vle && a->bits_per_word == 32)
return b;
return bfd_default_compatible (a, b);
case bfd_arch_rs6000:
if (b->mach == bfd_mach_rs6k)

9
bfd/elf-bfd.h
View File

@ -2368,6 +2368,15 @@ extern bfd_boolean bfd_elf_lookup_section_flags
extern Elf_Internal_Phdr * _bfd_elf_find_segment_containing_section
(bfd * abfd, asection * section);
/* PowerPC @tls opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tls_transform
(unsigned int, unsigned int);
/* PowerPC @tprel opcode transform/validate. */
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
/* PowerPC elf_object_p tweak. */
extern bfd_boolean _bfd_elf_ppc_set_arch (bfd *);
/* Exported interface for writing elf corefile notes. */
extern char *elfcore_write_note
(bfd *, char *, int *, const char *, int, const void *, int);

109
bfd/elf32-ppc.c
View File

@ -2196,13 +2196,93 @@ ppc_elf_mkobject (bfd *abfd)
PPC32_ELF_DATA);
}
/* When defaulting arch/mach, decode apuinfo to find a better match. */
bfd_boolean
_bfd_elf_ppc_set_arch (bfd *abfd)
{
unsigned long mach = 0;
asection *s;
unsigned char *contents;
if (abfd->arch_info->bits_per_word == 32
&& bfd_big_endian (abfd))
{
for (s = abfd->sections; s != NULL; s = s->next)
if ((elf_section_data (s)->this_hdr.sh_flags & SHF_PPC_VLE) != 0)
break;
if (s != NULL)
mach = bfd_mach_ppc_vle;
}
if (mach == 0)
{
s = bfd_get_section_by_name (abfd, APUINFO_SECTION_NAME);
if (s != NULL && bfd_malloc_and_get_section (abfd, s, &contents))
{
unsigned int apuinfo_size = bfd_get_32 (abfd, contents + 4);
unsigned int i;
for (i = 20; i < apuinfo_size + 20 && i + 4 <= s->size; i += 4)
{
unsigned int val = bfd_get_32 (abfd, contents + i);
switch (val >> 16)
{
case PPC_APUINFO_PMR:
case PPC_APUINFO_RFMCI:
if (mach == 0)
mach = bfd_mach_ppc_titan;
break;
case PPC_APUINFO_ISEL:
case PPC_APUINFO_CACHELCK:
if (mach == bfd_mach_ppc_titan)
mach = bfd_mach_ppc_e500mc;
break;
case PPC_APUINFO_SPE:
case PPC_APUINFO_EFS:
case PPC_APUINFO_BRLOCK:
if (mach != bfd_mach_ppc_vle)
mach = bfd_mach_ppc_e500;
case PPC_APUINFO_VLE:
mach = bfd_mach_ppc_vle;
break;
default:
mach = -1ul;
}
}
free (contents);
}
}
if (mach != 0 && mach != -1ul)
{
const bfd_arch_info_type *arch;
for (arch = abfd->arch_info->next; arch; arch = arch->next)
if (arch->mach == mach)
{
abfd->arch_info = arch;
break;
}
}
return TRUE;
}
/* Fix bad default arch selected for a 32 bit input bfd when the
default is 64 bit. */
default is 64 bit. Also select arch based on apuinfo. */
static bfd_boolean
ppc_elf_object_p (bfd *abfd)
{
if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 64)
if (!abfd->arch_info->the_default)
return TRUE;
if (abfd->arch_info->bits_per_word == 64)
{
Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
@ -2213,7 +2293,7 @@ ppc_elf_object_p (bfd *abfd)
BFD_ASSERT (abfd->arch_info->bits_per_word == 32);
}
}
return TRUE;
return _bfd_elf_ppc_set_arch (abfd);
}
/* Function to set whether a module needs the -mrelocatable bit set. */
@ -2519,16 +2599,16 @@ ppc_elf_modify_segment_map (bfd *abfd,
static const struct bfd_elf_special_section ppc_elf_special_sections[] =
{
{ STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
{ STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
{ STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
{ STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
{ STRING_COMMA_LEN (".PPC.EMB.apuinfo"), 0, SHT_NOTE, 0 },
{ STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
{ NULL, 0, 0, 0, 0 }
{ STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
{ STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
{ STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
{ STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
{ STRING_COMMA_LEN (APUINFO_SECTION_NAME), 0, SHT_NOTE, 0 },
{ STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
{ STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
{ NULL, 0, 0, 0, 0 }
};
/* This is what we want for new plt/got. */
@ -2637,9 +2717,6 @@ apuinfo_list_finish (void)
head = NULL;
}
#define APUINFO_SECTION_NAME ".PPC.EMB.apuinfo"
#define APUINFO_LABEL "APUinfo"
/* Scan the input BFDs and create a linked list of
the APUinfo values that will need to be emitted. */

9
bfd/elf64-ppc.c
View File

@ -2888,12 +2888,15 @@ ppc64_elf_mkobject (bfd *abfd)
}
/* Fix bad default arch selected for a 64 bit input bfd when the
default is 32 bit. */
default is 32 bit. Also select arch based on apuinfo. */
static bfd_boolean
ppc64_elf_object_p (bfd *abfd)
{
if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 32)
if (!abfd->arch_info->the_default)
return TRUE;
if (abfd->arch_info->bits_per_word == 32)
{
Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
@ -2904,7 +2907,7 @@ ppc64_elf_object_p (bfd *abfd)
BFD_ASSERT (abfd->arch_info->bits_per_word == 64);
}
}
return TRUE;
return _bfd_elf_ppc_set_arch (abfd);
}
/* Support for core dump NOTE sections. */

10
gas/ChangeLog
View File

@ -1,3 +1,13 @@
2016-06-07 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.

32
gas/config/tc-ppc.c
View File

@ -1048,18 +1048,6 @@ static segT ppc_current_section;
#ifdef OBJ_ELF
symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
#define PPC_APUINFO_ISEL 0x40
#define PPC_APUINFO_PMR 0x41
#define PPC_APUINFO_RFMCI 0x42
#define PPC_APUINFO_CACHELCK 0x43
#define PPC_APUINFO_SPE 0x100
#define PPC_APUINFO_EFS 0x101
#define PPC_APUINFO_BRLOCK 0x102
#define PPC_APUINFO_VLE 0x104
/*
* We keep a list of APUinfo
*/
unsigned long *ppc_apuinfo_list;
unsigned int ppc_apuinfo_num;
unsigned int ppc_apuinfo_num_alloc;
@ -1563,6 +1551,18 @@ ppc_setup_opcodes (void)
bad_insn = TRUE;
}
}
if ((op->flags & PPC_OPCODE_VLE) != 0)
{
as_bad (_("%s is enabled by vle flag"), op->name);
bad_insn = TRUE;
}
if (PPC_OP (op->opcode) != 4
&& PPC_OP (op->opcode) != 31
&& (op->deprecated & PPC_OPCODE_VLE) == 0)
{
as_bad (_("%s not disabled by vle flag"), op->name);
bad_insn = TRUE;
}
bad_insn |= insn_validate (op);
}
@ -1634,10 +1634,6 @@ ppc_setup_opcodes (void)
}
}
if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
for (op = vle_opcodes; op < op_end; op++)
hash_insert (ppc_hash, op->name, (void *) op);
/* Insert the macros into a hash table. */
ppc_macro_hash = hash_new ();
@ -1736,7 +1732,7 @@ ppc_cleanup (void)
unsigned int i;
/* Create the .PPC.EMB.apuinfo section. */
apuinfo_secp = subseg_new (".PPC.EMB.apuinfo", 0);
apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0);
bfd_set_section_flags (stdoutput,
apuinfo_secp,
SEC_HAS_CONTENTS | SEC_READONLY);
@ -1751,7 +1747,7 @@ ppc_cleanup (void)
md_number_to_chars (p, (valueT) 2, 4);
p = frag_more (8);
strcpy (p, "APUinfo");
strcpy (p, APUINFO_LABEL);
for (i = 0; i < ppc_apuinfo_num; i++)
{

7
include/ChangeLog
View File

@ -1,3 +1,10 @@
2016-06-07 Alan Modra <amodra@gmail.com>
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding

13
include/elf/ppc.h
View File

@ -202,6 +202,19 @@ END_RELOC_NUMBERS (R_PPC_max)
specified in the associated \
symbol table entry. */
/* APUinfo note section. */
#define APUINFO_SECTION_NAME ".PPC.EMB.apuinfo"
#define APUINFO_LABEL "APUinfo"
#define PPC_APUINFO_ISEL 0x40
#define PPC_APUINFO_PMR 0x41
#define PPC_APUINFO_RFMCI 0x42
#define PPC_APUINFO_CACHELCK 0x43
#define PPC_APUINFO_SPE 0x100
#define PPC_APUINFO_EFS 0x101
#define PPC_APUINFO_BRLOCK 0x102
#define PPC_APUINFO_VLE 0x104
/* Object attribute tags. */
enum
{

6
ld/ChangeLog
View File

@ -1,3 +1,9 @@
2016-06-07 Alan Modra <amodra@gmail.com>
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-06 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/ld-x86-64/pass.out: New file.

8
ld/testsuite/ld-powerpc/apuinfo-vle2.s Normal file
View File

@ -0,0 +1,8 @@
.text
.global apuinfo2
apuinfo2:
evstdd 29,8(1)
mfbbear 29
mfpmr 29, 27
dcbtstls 1, 29, 28
se_rfmci

3
ld/testsuite/ld-powerpc/apuinfo1.s
View File

@ -1,9 +1,8 @@
.text
.global apuinfo1
apuinfo1:
apuinfo1:
evstdd 29,8(1)
isellt 29, 28, 27
efsabs 29, 28
.global _start
_start:
nop

2
ld/testsuite/ld-powerpc/powerpc.exp
View File

@ -104,7 +104,7 @@ set ppcelftests {
"-a32 -me500" {apuinfo1.s apuinfo-nul.s apuinfo2.s}
{{readelf -x2 apuinfo.rd}} "apuinfo"}
{"APUinfo VLE section processing" "-melf32ppc" ""
"-a32 -me500 -mvle" {apuinfo1.s apuinfo-vle.s apuinfo2.s}
"-a32 -me500 -mvle" {apuinfo1.s apuinfo-vle.s apuinfo-vle2.s}
{{readelf -x2 apuinfo-vle.rd}} "apuinfo-vle"}
{"APUinfo NULL section processing" "-melf32ppc" ""
"-a32 -me500" {apuinfo-nul1.s apuinfo-nul.s}

11
opcodes/ChangeLog
View File

@ -1,3 +1,14 @@
2016-06-07 Alan Modra <amodra@gmail.com>
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with

71
opcodes/ppc-dis.c
View File

@ -51,9 +51,9 @@ struct ppc_mopt {
};
struct ppc_mopt ppc_opts[] = {
{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
{ "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
0 },
{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
{ "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
0 },
{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
@ -64,48 +64,48 @@ struct ppc_mopt ppc_opts[] = {
{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
0 },
{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
{ "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
0 },
{ "603", (PPC_OPCODE_PPC),
{ "603", PPC_OPCODE_PPC,
0 },
{ "604", (PPC_OPCODE_PPC),
{ "604", PPC_OPCODE_PPC,
0 },
{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
{ "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
0 },
{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
{ "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
0 },
{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
{ "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
0 },
{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
{ "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
0 },
{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
{ "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
0 },
{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
{ "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
, 0 },
{ "821", (PPC_OPCODE_PPC | PPC_OPCODE_860),
{ "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
0 },
{ "850", (PPC_OPCODE_PPC | PPC_OPCODE_860),
{ "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
0 },
{ "860", (PPC_OPCODE_PPC | PPC_OPCODE_860),
{ "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
0 },
{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
| PPC_OPCODE_A2),
0 },
{ "altivec", (PPC_OPCODE_PPC),
{ "altivec", PPC_OPCODE_PPC,
PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
{ "any", 0,
PPC_OPCODE_ANY },
{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
{ "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
0 },
{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
{ "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
0 },
{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
0 },
{ "com", (PPC_OPCODE_COMMON),
{ "com", PPC_OPCODE_COMMON,
0 },
{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
@ -138,9 +138,9 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500),
0 },
{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
0 },
{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5),
@ -163,21 +163,21 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
0 },
{ "ppc", (PPC_OPCODE_PPC),
{ "ppc", PPC_OPCODE_PPC,
0 },
{ "ppc32", (PPC_OPCODE_PPC),
{ "ppc32", PPC_OPCODE_PPC,
0 },
{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
{ "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
0 },
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
{ "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
0 },
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
{ "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
0 },
{ "pwr", (PPC_OPCODE_POWER),
{ "pwr", PPC_OPCODE_POWER,
0 },
{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
{ "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
0 },
{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
{ "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5),
@ -203,18 +203,21 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
0 },
{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
{ "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
0 },
{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
PPC_OPCODE_SPE },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500),
PPC_OPCODE_VLE },
{ "vsx", (PPC_OPCODE_PPC),
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
{ "htm", (PPC_OPCODE_PPC),
{ "htm", PPC_OPCODE_PPC,
PPC_OPCODE_HTM },
};

7110
opcodes/ppc-opc.c
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