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[PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise.
This commit is contained in:
Andre Vieira
parent
f49bb598d9
commit
14b456f2a0
@ -1,3 +1,15 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (thumb32_opcodes): Add new instructions.
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(enum mve_instructions): Likewise.
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(enum mve_undefined): Add new reasons.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_size): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -253,6 +253,17 @@ enum mve_instructions
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MVE_VRMULH,
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MVE_VNEG_FP,
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MVE_VNEG_VEC,
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MVE_VPNOT,
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MVE_VPSEL,
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MVE_VQABS,
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MVE_VQADD_T1,
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MVE_VQADD_T2,
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MVE_VQSUB_T1,
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MVE_VQSUB_T2,
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MVE_VQNEG,
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MVE_VREV16,
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MVE_VREV32,
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MVE_VREV64,
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MVE_NONE
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};
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@ -290,6 +301,7 @@ enum mve_undefined
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UNDEF_SIZE_2, /* undefined because size == 2. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
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UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
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UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
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UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
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UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
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@ -2893,6 +2905,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xee300f01, 0xefb10f51,
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"vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VPNOT. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VPNOT,
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0xfe310f4d, 0xffffffff,
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"vpnot%v"},
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/* Vector VPSEL. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VPSEL,
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0xfe310f01, 0xffb11f51,
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"vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQABS. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQABS,
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0xffb00740, 0xffb31fd1,
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"vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQADD T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQADD_T1,
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0xef000050, 0xef811f51,
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"vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQADD T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQADD_T2,
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0xee000f60, 0xef811f70,
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"vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQDMULL T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMULL_T2,
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@ -2983,6 +3025,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xfe010e60, 0xff811f70,
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"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQNEG. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQNEG,
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0xffb007c0, 0xffb31fd1,
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"vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VQRSHL T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRSHL_T1,
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@ -3031,6 +3079,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xee800fc0, 0xffa00fd1,
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"vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VQSUB T1 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSUB_T1,
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0xef000250, 0xef811f51,
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"vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQSUB T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSUB_T2,
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0xee001f60, 0xef811f70,
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"vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VREV16. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VREV16,
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0xffb00140, 0xffb31fd1,
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"vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
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/* Vector VREV32. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VREV32,
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0xffb000c0, 0xffb31fd1,
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"vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VREV64. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VREV64,
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0xffb00040, 0xffb31fd1,
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"vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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@ -5239,6 +5317,8 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VQADD_T2:
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case MVE_VQSUB_T2:
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case MVE_VMUL_VEC_T2:
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case MVE_VMULH:
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case MVE_VRMULH:
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@ -5539,6 +5619,8 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VQADD_T1:
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case MVE_VQSUB_T1:
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case MVE_VMUL_VEC_T1:
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case MVE_VABD_VEC:
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case MVE_VADD_VEC_T1:
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@ -5881,6 +5963,8 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VQNEG:
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case MVE_VQABS:
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case MVE_VNEG_VEC:
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case MVE_VCLS:
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case MVE_VCLZ:
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@ -5892,6 +5976,36 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VREV16:
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if (arm_decode_field (given, 18, 19) == 0)
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return FALSE;
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else
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{
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*undefined_code = UNDEF_SIZE_NOT_0;
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return TRUE;
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}
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case MVE_VREV32:
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{
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unsigned long size = arm_decode_field (given, 18, 19);
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if ((size & 2) == 2)
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{
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*undefined_code = UNDEF_SIZE_2;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VREV64:
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if (arm_decode_field (given, 18, 19) != 3)
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return FALSE;
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else
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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default:
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return FALSE;
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}
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@ -5951,6 +6065,8 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VQADD_T2:
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case MVE_VQSUB_T2:
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case MVE_VMUL_FP_T2:
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case MVE_VMUL_VEC_T2:
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case MVE_VMLA:
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@ -6360,6 +6476,20 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VREV64:
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{
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unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
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if (qd == qm)
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{
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*unpredictable_code = UNPRED_Q_REGS_EQUAL;
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return TRUE;
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}
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else
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -6590,6 +6720,10 @@ print_mve_undefined (struct disassemble_info *info,
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func (stream, "size <= 1");
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break;
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case UNDEF_SIZE_NOT_0:
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func (stream, "size not equal to 0");
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break;
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case UNDEF_SIZE_NOT_2:
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func (stream, "size not equal to 2");
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break;
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@ -7094,6 +7228,9 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VPT_VEC_T4:
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case MVE_VPT_VEC_T5:
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case MVE_VPT_VEC_T6:
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case MVE_VQABS:
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case MVE_VQADD_T1:
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case MVE_VQADD_T2:
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case MVE_VQDMLADH:
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case MVE_VQRDMLADH:
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case MVE_VQDMLAH:
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@ -7106,10 +7243,15 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VQRDMULH_T2:
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case MVE_VQDMULH_T3:
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case MVE_VQRDMULH_T4:
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case MVE_VQNEG:
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case MVE_VQRSHL_T1:
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case MVE_VQRSHL_T2:
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case MVE_VQSHL_T1:
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case MVE_VQSHL_T4:
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case MVE_VQSUB_T1:
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case MVE_VQSUB_T2:
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case MVE_VREV32:
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case MVE_VREV64:
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case MVE_VRHADD:
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case MVE_VRINT_FP:
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case MVE_VRSHL_T1:
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