mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-25 11:04:18 +08:00
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
This commit is contained in:
Chris Demetriou
parent
c6f9085cab
commit
1423405663
@ -1,3 +1,17 @@
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2004-04-09 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (check_fmt): Remove.
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(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
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(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
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(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
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(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
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(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
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(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
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(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
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(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
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(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
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(C.cnd.fmta): Remove incorrect call to check_fmt_p.
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2004-04-09 Chris Demetriou <cgd@broadcom.com>
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* sb1.igen (check_sbx): New function.
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@ -3643,23 +3643,6 @@
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// ReservedInstruction exception if not.
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//
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// check_fmt checks that the format is single or double.
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:function:::void:check_fmt:int fmt, instruction_word insn
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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*mipsV:
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*mips32:
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*mips64:
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*vr4100:
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*vr5000:
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*r3900:
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{
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if ((fmt != fmt_single) && (fmt != fmt_double))
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SignalException (ReservedInstruction, insn);
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}
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// check_fmt_p checks that the format is single, double, or paired single.
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:function:::void:check_fmt_p:int fmt, instruction_word insn
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*mipsI:
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@ -3673,7 +3656,8 @@
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{
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/* None of these ISAs support Paired Single, so just fall back to
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the single/double check. */
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check_fmt (SD_, fmt, insn);
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if ((fmt != fmt_single) && (fmt != fmt_double))
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SignalException (ReservedInstruction, insn);
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}
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:function:::void:check_fmt_p:int fmt, instruction_word insn
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@ -3780,7 +3764,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
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010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
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"abs.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -3801,7 +3785,7 @@
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010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
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010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
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"add.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mipsI:
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*mipsII:
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@ -3902,7 +3886,7 @@
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}
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010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
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010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
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"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
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*mipsI:
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*mipsII:
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@ -3910,12 +3894,11 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt_p (SD_, fmt, instruction_0);
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Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
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TRACE_ALU_RESULT (ValueFCR (31));
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}
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010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
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010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
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"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
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"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
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*mipsIV:
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@ -3934,7 +3917,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
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"ceil.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -3946,13 +3929,12 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
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fmt_long));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
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"ceil.w.%s<FMT> f<FD>, f<FS>"
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*mipsII:
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*mipsIII:
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@ -3966,7 +3948,6 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
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fmt_word));
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}
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@ -4064,7 +4045,7 @@
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//
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// FIXME: Does not correctly differentiate between mips*
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//
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010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
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010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
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"cvt.d.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -4086,7 +4067,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
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"cvt.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4120,7 +4101,7 @@
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//
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// FIXME: Does not correctly differentiate between mips*
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//
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010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
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010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
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"cvt.s.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -4164,7 +4145,7 @@
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}
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010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
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"cvt.w.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -4186,7 +4167,7 @@
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}
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010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
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010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
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"div.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mipsI:
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*mipsII:
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@ -4201,7 +4182,6 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
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}
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@ -4283,7 +4263,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
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"floor.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4295,13 +4275,12 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
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fmt_long));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
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"floor.w.%s<FMT> f<FD>, f<FS>"
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*mipsII:
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*mipsIII:
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@ -4315,7 +4294,6 @@
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
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fmt_word));
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}
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@ -4408,7 +4386,7 @@
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010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
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"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -4453,7 +4431,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
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010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
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"mov.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -4491,7 +4469,7 @@
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// MOVF.fmt
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// MOVT.fmt
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010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
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010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
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"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
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*mipsIV:
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*mipsV:
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@ -4520,7 +4498,7 @@
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}
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010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
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010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
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"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
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*mipsIV:
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*mipsV:
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@ -4543,7 +4521,7 @@
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010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
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010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
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"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
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*mipsIV:
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*mipsV:
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@ -4559,7 +4537,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
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"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -4604,7 +4582,7 @@
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}
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010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
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010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
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"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mipsI:
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*mipsII:
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@ -4624,7 +4602,7 @@
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}
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010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
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010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
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"neg.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -4644,7 +4622,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
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"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -4660,7 +4638,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
|
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"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -4743,7 +4721,7 @@
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}
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|
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010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
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"recip.%s<FMT> f<FD>, f<FS>"
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*mipsIV:
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*mipsV:
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@ -4752,12 +4730,11 @@
|
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{
|
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int fmt = FMT;
|
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
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"round.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4769,13 +4746,12 @@
|
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{
|
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int fmt = FMT;
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check_fpu (SD_);
|
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
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fmt_long));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
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"round.w.%s<FMT> f<FD>, f<FS>"
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*mipsII:
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*mipsIII:
|
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@ -4789,13 +4765,12 @@
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{
|
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int fmt = FMT;
|
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check_fpu (SD_);
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check_fmt (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
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fmt_word));
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}
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|
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|
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010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
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"rsqrt.%s<FMT> f<FD>, f<FS>"
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||||
*mipsIV:
|
||||
*mipsV:
|
||||
@ -4804,7 +4779,6 @@
|
||||
{
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
check_fmt (SD_, fmt, instruction_0);
|
||||
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
|
||||
}
|
||||
|
||||
@ -4865,7 +4839,7 @@
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
|
||||
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
|
||||
"sqrt.%s<FMT> f<FD>, f<FS>"
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
@ -4879,12 +4853,11 @@
|
||||
{
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
check_fmt (SD_, fmt, instruction_0);
|
||||
StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
|
||||
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
|
||||
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
@ -4989,7 +4962,7 @@
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
|
||||
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
|
||||
"trunc.l.%s<FMT> f<FD>, f<FS>"
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
@ -5001,13 +4974,12 @@
|
||||
{
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
check_fmt (SD_, fmt, instruction_0);
|
||||
StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
||||
fmt_long));
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
|
||||
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
|
||||
"trunc.w.%s<FMT> f<FD>, f<FS>"
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
@ -5021,7 +4993,6 @@
|
||||
{
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
check_fmt (SD_, fmt, instruction_0);
|
||||
StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
||||
fmt_word));
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user