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opcodes cgen: remove use of PTR

Browse Source 
Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted,
due to failure of bpf to compile with that patch applied.

.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
   57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
plus other similar errors.

cpu/
	* mep.opc (print_tpreg, print_spreg): Delete unnecessary
	forward declarations.  Replace PTR with void *.
	* mt.opc (print_dollarhex, print_pcrel): Delete forward decls.
opcodes/
	* bpf-desc.c, * bpf-dis.c, * cris-desc.c,
	* epiphany-desc.c, * epiphany-dis.c,
	* fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c,
	* ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c,
	* lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c,
	* m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c,
	* mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c,
	* xc16x-desc.c, * xc16x-dis.c,
	* xstormy16-desc.c, * xstormy16-dis.c: Regenerate.
This commit is contained in:
Alan Modra 2022-05-10 08:52:07 +09:30
parent 455f32e3c3
commit 0dfdb5234a
31 changed files with 1286 additions and 1298 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
cpu/mep.opc
View File

@ -869,11 +869,8 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
#define CGEN_VALIDATE_INSN_SUPPORTED
static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void
print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
@ -883,7 +880,7 @@ print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
}
static void
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{

3
cpu/mt.opc
View File

@ -434,9 +434,6 @@ parse_type (CGEN_CPU_DESC cd,
}
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,

34
opcodes/bpf-desc.c
View File

@ -175,7 +175,7 @@ const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
{ "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
@ -224,10 +224,10 @@ const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
{ 0, { (const PTR) 0 } }
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -239,51 +239,51 @@ const CGEN_OPERAND bpf_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* dstle: destination register */
{ "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
/* srcle: source register */
{ "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
/* dstbe: destination register */
{ "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
/* srcbe: source register */
{ "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
/* disp16: 16-bit PC-relative address */
{ "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* disp32: 32-bit PC-relative address */
{ "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* imm32: 32-bit immediate */
{ "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* offset16: 16-bit offset */
{ "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* imm64: 64-bit immediate */
{ "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
{ 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
{ 3, { &BPF_F_IMM64_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* endsize: endianness size immediate: 16, 32 or 64 */
{ "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
{ 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};

2
opcodes/bpf-dis.c
View File

@ -136,7 +136,7 @@ print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void bpf_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

124
opcodes/cris-desc.c
View File

@ -710,25 +710,25 @@ const CGEN_HW_ENTRY cris_cgen_hw_table[] =
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
{ "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
{ "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
{ "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
{ "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
{ "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
{ "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
{ "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
{ "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
@ -820,15 +820,15 @@ const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
{ 0, { (const PTR) 0 } }
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -840,179 +840,179 @@ const CGEN_OPERAND cris_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_NIL] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: */
{ "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit-move: cbit for pre-V32, nothing for newer */
{ "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: */
{ "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit-move: vbit for pre-V32, nothing for newer */
{ "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: */
{ "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit-move: zbit for pre-V32, nothing for newer */
{ "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: */
{ "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit-move: nbit for pre-V32, nothing for newer */
{ "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* xbit: */
{ "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: */
{ "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ubit: */
{ "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
/* pbit: */
{ "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
/* rbit: carry bit for MCP+restore-P flag bit */
{ "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* sbit: */
{ "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* mbit: */
{ "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* qbit: */
{ "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* prefix-set: Instruction-prefixed flag */
{ "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* prefixreg: Prefix address */
{ "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Rs: Source general register */
{ "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* inc: Incrementness of indirect operand */
{ "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ps: Source special register */
{ "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ss: Source support register */
{ "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_CRISV32), 0 } } } } },
/* Sd: Destination support register */
{ "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_CRISV32), 0 } } } } },
/* i: Quick signed 6-bit */
{ "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S6] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_S6] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* j: Quick unsigned 6-bit */
{ "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U6] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* c: Quick unsigned 5-bit */
{ "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U5] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* qo: Quick unsigned 4-bit, PC-relative */
{ "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_QO] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_QO] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } },
/* Rd: Destination general register */
{ "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sconst8: Signed byte [PC+] */
{ "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* uconst8: Unsigned byte [PC+] */
{ "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* sconst16: Signed word [PC+] */
{ "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* uconst16: Unsigned word [PC+] */
{ "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* const32: Dword [PC+] */
{ "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* const32-pcrel: Dword [PC+] */
{ "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
{ 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } },
/* Pd: Destination special register */
{ "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* o: Signed 8-bit */
{ "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S8] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_S8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* o-pcrel: 9-bit signed immediate PC-rel */
{ "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8,
{ 2, { (const PTR) &CRIS_F_DISP9_MULTI_IFIELD[0] } },
{ 2, { &CRIS_F_DISP9_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* o-word-pcrel: 16-bit signed immediate PC-rel */
{ "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
{ 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* cc: Condition codes */
{ "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* n: Quick unsigned 4-bit */
{ "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U4] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* swapoption: Swap option */
{ "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4,
{ 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* list-of-flags: Flag bits as operand */
{ "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8,
{ 2, { (const PTR) &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
{ 2, { &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

244
opcodes/epiphany-desc.c
View File

@ -321,8 +321,8 @@ const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
@ -379,10 +379,10 @@ const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
{ "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -480,51 +480,51 @@ const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { (const PTR) 0 } }
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -536,371 +536,371 @@ const CGEN_OPERAND epiphany_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: integer zero bit */
{ "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: integer neg bit */
{ "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: integer carry bit */
{ "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: integer overflow bit */
{ "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bzbit: floating point zero bit */
{ "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bnbit: floating point neg bit */
{ "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvbit: floating point ovfl bit */
{ "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bcbit: floating point carry bit */
{ "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bubit: floating point underfl bit */
{ "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bibit: floating point invalid bit */
{ "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vsbit: integer overflow sticky */
{ "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvsbit: floating point overflow sticky */
{ "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bisbit: floating point invalid sticky */
{ "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* busbit: floating point underflow sticky */
{ "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause0bit: exceprion cause bit0 */
{ "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause1bit: exceprion cause bit1 */
{ "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause2bit: external load stalled bit */
{ "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* extFstallbit: external fetch stalled bit */
{ "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* trmbit: 0=round to nearest, 1=trunacte selct bit */
{ "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* invExcEnbit: invalid exception enable bit */
{ "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ovfExcEnbit: overflow exception enable bit */
{ "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* unExcEnbit: underflow exception enable bit */
{ "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit0: timer 0 mode selection 0 */
{ "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit1: timer 0 mode selection 1 */
{ "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit2: timer 0 mode selection 2 */
{ "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit3: timer 0 mode selection 3 */
{ "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit0: timer 1 mode selection 0 */
{ "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit1: timer 1 mode selection 1 */
{ "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit2: timer 1 mode selection 2 */
{ "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit3: timer 1 mode selection 3 */
{ "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* mbkptEnbit: multicore bkpt enable */
{ "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* clockGateEnbit: clock gate enable enable */
{ "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit0: arithmetic mode bit0 */
{ "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit1: arithmetic mode bit1 */
{ "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit2: arithmetic mode bit2 */
{ "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit12: core config bit 12 */
{ "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit13: core config bit 13 */
{ "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit14: core config bit 14 */
{ "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit15: core config bit 15 */
{ "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit16: core config bit 16 */
{ "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit20: core config bit 20 */
{ "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit21: core config bit 21 */
{ "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit24: core config bit 24 */
{ "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit25: core config bit 25 */
{ "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit26: core config bit 26 */
{ "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit27: core config bit 27 */
{ "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit28: core config bit 28 */
{ "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit29: core config bit 29 */
{ "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit30: core config bit 30 */
{ "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit31: core config bit 31 */
{ "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* gidisablebit: global interrupt disable bit */
{ "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* kmbit: kernel mode bit */
{ "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* caibit: core actibe indicator bit */
{ "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sflagbit: sflag bit */
{ "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* memaddr: memory effective address */
{ "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* simm24: branch address pc-relative */
{ "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: branch address pc-relative */
{ "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rd: destination register */
{ "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rn: source register */
{ "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rm: source register */
{ "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frd: fp destination register */
{ "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frn: fp source register */
{ "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frm: fp source register */
{ "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd6: destination register */
{ "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rn6: source register */
{ "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rm6: source register */
{ "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frd6: fp destination register */
{ "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frn6: fp source register */
{ "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frm6: fp source register */
{ "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sd: special destination */
{ "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sn: special source */
{ "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sd6: special destination register */
{ "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sn6: special source register */
{ "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sddma: dma register */
{ "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sndma: dma register */
{ "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmem: mem register */
{ "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmem: mem register */
{ "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmesh: mesh register */
{ "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmesh: mesh register */
{ "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* simm3: signed 3-bit literal */
{ "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* simm11: signed 11-bit literal */
{ "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
{ 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* disp3: short data displacement */
{ "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* trapnum6: parameter for swi or trap */
{ "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* swi_num: unsigned 6-bit swi# */
{ "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* disp11: sign-magnitude data displacement */
{ "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
{ 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shift: immediate shift amount */
{ "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: 16-bit unsigned literal */
{ "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
{ 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
{ 2, { &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* imm8: 8-bit unsigned literal */
{ "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* direction: +/- indexing */
{ "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dpmi: +/- magnitude immediate displacement */
{ "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
{ 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/epiphany-dis.c
View File

@ -137,7 +137,7 @@ print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void epiphany_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

120
opcodes/fr30-desc.c
View File

@ -263,13 +263,13 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
@ -352,9 +352,9 @@ const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
{ 0, { (const PTR) 0 } }
{ 0, { &fr30_cgen_ifld_table[FR30_F_I20_4] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_I20_16] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -366,203 +366,203 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
{ 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 2, { &FR30_F_I20_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0, { &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/fr30-dis.c
View File

@ -155,7 +155,7 @@ print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void fr30_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

250
opcodes/frv-desc.c
View File

@ -1869,32 +1869,32 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] =
{ "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
{ "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } } } } },
{ "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & frv_cgen_opval_gr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
{ "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, & frv_cgen_opval_spr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } } } } },
{ "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, & frv_cgen_opval_h_pack, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, & frv_cgen_opval_h_hint_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, & frv_cgen_opval_h_hint_not_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -2030,21 +2030,21 @@ const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } },
{ 0, { (const PTR) 0 } }
{ 0, { &frv_cgen_ifld_table[FRV_F_U12_H] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_U12_L] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } },
{ 0, { (const PTR) 0 } }
{ 0, { &frv_cgen_ifld_table[FRV_F_SPR_H] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_SPR_L] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } },
{ 0, { (const PTR) 0 } }
{ 0, { &frv_cgen_ifld_table[FRV_F_LABELH6] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LABELL18] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -2056,363 +2056,363 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* pack: packing bit */
{ "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_PACK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRi: source register 1 */
{ "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRj: source register 2 */
{ "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRk: destination register */
{ "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRkhi: destination register */
{ "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRklo: destination register */
{ "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRdoublek: destination register */
{ "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Si: signed accumulator */
{ "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Ui: unsigned accumulator */
{ "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Sk: target accumulator */
{ "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Uk: target accumulator */
{ "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGi: source register */
{ "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACCGI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGk: target register */
{ "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ACCGK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CPRi: source register */
{ "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CPRI] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRj: source register */
{ "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CPRJ] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRk: destination register */
{ "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRdoublek: destination register */
{ "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* FRinti: source register 1 */
{ "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintj: source register 2 */
{ "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintk: target register */
{ "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRi: source register 1 */
{ "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRj: source register 2 */
{ "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRk: destination register */
{ "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRkhi: destination register */
{ "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRklo: destination register */
{ "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublei: source register 1 */
{ "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublej: source register 2 */
{ "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublek: target register */
{ "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: source register 1 */
{ "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: source register 2 */
{ "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_int: destination register */
{ "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_float: destination register */
{ "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRk: destination register */
{ "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CCi: condition register */
{ "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CCI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_1: condition register */
{ "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_2: condition register */
{ "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_3: condition register */
{ "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_1: condition register */
{ "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_2: condition register */
{ "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_3: condition register */
{ "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCk: condition register */
{ "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FCCK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* eir: exception insn reg */
{ "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_EIR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u16: 16 bit unsigned immediate */
{ "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s16: 16 bit signed immediate */
{ "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6: 6 bit signed immediate */
{ "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6_1: 6 bit signed immediate */
{ "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S6_1] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u6: 6 bit unsigned immediate */
{ "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_U6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s5: 5 bit signed immediate */
{ "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S5] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* cond: conditional arithmetic */
{ "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_COND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ccond: lr branch condition */
{ "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_CCOND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint: 2 bit branch predictor */
{ "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint_taken: 2 bit branch predictor */
{ "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hint_not_taken: 2 bit branch predictor */
{ "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LI: link indicator */
{ "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lock: cache lock indicator */
{ "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LOCK] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* debug: debug mode indicator */
{ "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_DEBUG] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ae: all entries indicator */
{ "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_AE] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* label16: 18 bit pc relative address */
{ "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LABEL16] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* LRAE: Load Real Address E flag */
{ "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LRAE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAD: Load Real Address D flag */
{ "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LRAD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAS: Load Real Address S flag */
{ "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_LRAS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRopx: TLB Probe operation number */
{ "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRL: TLB Probe L flag */
{ "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A0: A==0 operand of mclracc */
{ "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A1: A==1 operand of mclracc */
{ "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintieven: (even) source register 1 */
{ "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintjeven: (even) source register 2 */
{ "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintkeven: (even) target register */
{ "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* d12: 12 bit signed immediate */
{ "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s12: 12 bit signed immediate */
{ "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u12: 12 bit signed immediate */
{ "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
{ 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
{ 2, { &FRV_F_U12_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* spr: special purpose register */
{ "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
{ 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 2, { &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for #lo() */
{ "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit unsigned immediate, for #lo() */
{ "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uhi16: 16 bit unsigned immediate, for #hi() */
{ "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label24: 26 bit pc relative address */
{ "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
{ 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 2, { &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_esr: PSR.ESR bit */
{ "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_s: PSR.S bit */
{ "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_ps: PSR.PS bit */
{ "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_et: PSR.ET bit */
{ "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bs: BPSR.BS bit */
{ "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bet: BPSR.BET bit */
{ "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tba: TBR.TBA */
{ "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tt: TBR.TT */
{ "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ldann: ld annotation */
{ "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lddann: ldd annotation */
{ "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* callann: call annotation */
{ "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/frv-dis.c
View File

@ -120,7 +120,7 @@ print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void frv_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

28
opcodes/ip2k-desc.c
View File

@ -334,59 +334,59 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* addr16cjp: 13-bit address */
{ "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* fr: register */
{ "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_REG] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* lit8: 8-bit signed literal */
{ "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitno: bit number */
{ "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16p: page number */
{ "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16h: high 8 bits of address */
{ "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16l: low 8 bits of address */
{ "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reti3: reti flags */
{ "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
{ 0, { &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* pabits: page bits */
{ "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcbit: digit carry bit */
{ "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/ip2k-dis.c
View File

@ -216,7 +216,7 @@ print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void ip2k_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

86
opcodes/iq2000-desc.c
View File

@ -224,7 +224,7 @@ const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -292,21 +292,21 @@ const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { (const PTR) 0 } }
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { (const PTR) 0 } }
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { (const PTR) 0 } }
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -318,135 +318,135 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* rs: register Rs */
{ "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rt: register Rt */
{ "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd: register Rd */
{ "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rs: register Rd from Rs */
{ "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
{ 2, { &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rt: register Rd from Rt */
{ "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
{ 2, { &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rt-rs: register Rt from Rs */
{ "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
{ 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
{ 2, { &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shamt: shift amount */
{ "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: immediate */
{ "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* offset: pc-relative offset */
{ "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* baseoff: base register offset */
{ "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptarg: jump target */
{ "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
{ "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskq10: iq10 mask */
{ "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskl: mask left */
{ "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* count: count */
{ "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* _index: index */
{ "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* execode: execcode */
{ "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bytecount: byte count */
{ "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-y: cam global opn y */
{ "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-z: cam global mask z */
{ "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3func: CM 3 bit fn field */
{ "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4func: CM 4 bit fn field */
{ "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3z: CM 3 bit Z field */
{ "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4z: CM 4 bit Z field */
{ "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* base: base register */
{ "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskr: mask right */
{ "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitnum: bit number */
{ "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate */
{ "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: 16 bit signed immediate, for low */
{ "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mlo16: negated 16 bit signed immediate */
{ "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptargq10: iq10 21-bit jump offset */
{ "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
{ 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/iq2000-dis.c
View File

@ -60,7 +60,7 @@ static int read_insn
void iq2000_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

42
opcodes/lm32-desc.c
View File

@ -224,8 +224,8 @@ const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -276,79 +276,79 @@ const CGEN_OPERAND lm32_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* r0: register 0 */
{ "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r1: register 1 */
{ "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r2: register 2 */
{ "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* shift: shift amout */
{ "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: signed immediate */
{ "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm: unsigned immediate */
{ "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* branch: branch offset */
{ "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* call: call offset */
{ "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* csr: csr */
{ "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* user: user */
{ "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* exception: exception */
{ "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16-bit immediate */
{ "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: low 16-bit immediate */
{ "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gp16: gp relative 16-bit immediate */
{ "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* got16: got 16-bit immediate */
{ "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotoffhi16: got offset high 16-bit immediate */
{ "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotofflo16: got offset low 16-bit immediate */
{ "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/lm32-dis.c
View File

@ -60,7 +60,7 @@ static int read_insn
void lm32_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

660
opcodes/m32c-desc.c
View File

File diff suppressed because it is too large Load Diff

2
opcodes/m32c-dis.c
View File

@ -276,7 +276,7 @@ print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
}
void m32c_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

64
opcodes/m32r-desc.c
View File

@ -241,10 +241,10 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
{ "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
{ "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
{ "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
@ -314,119 +314,119 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm3: 3 bit unsigned number */
{ "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm8: 8 bit unsigned immediate */
{ "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0, { &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/m32r-dis.c
View File

@ -168,7 +168,7 @@ my_print_insn (CGEN_CPU_DESC cd,
/* -- */
void m32r_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

406
opcodes/mep-desc.c
View File

@ -568,15 +568,15 @@ const CGEN_HW_ENTRY mep_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr64-w", HW_H_CR64_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};
@ -776,101 +776,101 @@ const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_5] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_7] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_11] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_C5_RM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -882,587 +882,587 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r0: register 0 */
{ "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn: register Rn */
{ "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rm: register Rm */
{ "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rl: register Rl */
{ "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RL] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3: register 0-7 */
{ "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rma: register Rm holding pointer */
{ "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } },
/* rnc: register Rn holding char */
{ "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnuc: register Rn holding unsigned char */
{ "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rns: register Rn holding short */
{ "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnus: register Rn holding unsigned short */
{ "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnl: register Rn holding long */
{ "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnul: register Rn holding unsigned long */
{ "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* rn3c: register 0-7 holding unsigned char */
{ "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3uc: register 0-7 holding byte */
{ "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3s: register 0-7 holding unsigned short */
{ "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3us: register 0-7 holding short */
{ "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3l: register 0-7 holding unsigned long */
{ "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3ul: register 0-7 holding long */
{ "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* lp: link pointer */
{ "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sar: shift amount register */
{ "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* hi: high result */
{ "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* lo: low result */
{ "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb0: modulo begin register 0 */
{ "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me0: modulo end register 0 */
{ "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb1: modulo begin register 1 */
{ "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me1: modulo end register 1 */
{ "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* psw: program status word */
{ "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* epc: exception prog counter */
{ "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* exc: exception cause */
{ "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* npc: nmi program counter */
{ "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* dbg: debug register */
{ "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* depc: debug exception pc */
{ "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* opt: option register */
{ "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r1: register 1 */
{ "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tp: tiny data area pointer */
{ "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sp: stack pointer */
{ "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tpr: comment */
{ "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* spr: comment */
{ "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* csrn: control/special register */
{ "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* csrn-idx: control/special reg idx */
{ "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* crn64: copro Rn (64-bit) */
{ "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crn: copro Rn (32-bit) */
{ "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx64: copro Rn (0-31, 64-bit) */
{ "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx: copro Rn (0-31, 32-bit) */
{ "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ccrn: copro control reg CCRn */
{ "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
{ 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_CCRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* cccc: copro flags */
{ "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* pcrel8a2: comment */
{ "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_8S8A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel12a2: comment */
{ "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_12S4A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel17a2: comment */
{ "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_17S16A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel24a2: comment */
{ "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcabs24a2: comment */
{ "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* sdisp16: comment */
{ "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm16: comment */
{ "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm16: comment */
{ "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* code16: uci/dsp code (16 bits) */
{ "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp2: SSARB addend (2 bits) */
{ "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_2U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm2: interrupt (2 bits) */
{ "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_2U10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm6: add const (6 bits) */
{ "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_6S8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8: mov const (8 bits) */
{ "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_8S8] } },
{ 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* addr24a4: comment */
{ "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
{ 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* code24: coprocessor code */
{ "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
{ 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_24U4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* callnum: system call number */
{ "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
{ 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
{ 4, { &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm3: bit immediate (3 bits) */
{ "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_3U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm4: bCC const (4 bits) */
{ "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_4U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm5: bit/shift val (5 bits) */
{ "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_5U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7: comment */
{ "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_7U9] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7a2: comment */
{ "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_7U9A2] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
/* udisp7a4: comment */
{ "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm7a4: comment */
{ "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm24: immediate (24 bits) */
{ "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
{ 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_24U8N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm4: cache immed'te (4 bits) */
{ "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm5: clip immediate (5 bits) */
{ "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10: comment */
{ "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a2: comment */
{ "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a4: comment */
{ "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a8: comment */
{ "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* zero: Zero operand */
{ "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rl5: register Rl c5 */
{ "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_RL5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp12: copro addend (12 bits) */
{ "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_12S20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* c5rmuimm20: 20-bit immediate in rm and imm16 */
{ "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
{ 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
{ "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
{ 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cp_flag: branch condition register */
{ "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_csar0: ivc2_csar0 */
{ "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cc: ivc2_cc */
{ "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofr0: ivc2_cofr0 */
{ "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofr1: ivc2_cofr1 */
{ "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofa0: ivc2_cofa0 */
{ "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofa1: ivc2_cofa1 */
{ "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_csar1: ivc2_csar1 */
{ "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_0: acc0_0 */
{ "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_1: acc0_1 */
{ "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_2: acc0_2 */
{ "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_3: acc0_3 */
{ "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_4: acc0_4 */
{ "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_5: acc0_5 */
{ "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_6: acc0_6 */
{ "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_7: acc0_7 */
{ "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_0: acc1_0 */
{ "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_1: acc1_1 */
{ "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_2: acc1_2 */
{ "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_3: acc1_3 */
{ "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_4: acc1_4 */
{ "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_5: acc1_5 */
{ "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_6: acc1_6 */
{ "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_7: acc1_7 */
{ "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* croc: $CRo C3 */
{ "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqc: $CRq C3 */
{ "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpc: $CRp C3 */
{ "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-1: filler */
{ "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-2: filler */
{ "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-3: filler */
{ "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p4: Imm3p4 */
{ "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p9: Imm3p9 */
{ "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p8: Imm4p8 */
{ "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p7: Imm5p7 */
{ "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm6p6: Imm6p6 */
{ "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p4: Imm8p4 */
{ "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p4: sImm8p4 */
{ "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p5: Imm3p5 */
{ "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p12: Imm3p12 */
{ "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p4: Imm4p4 */
{ "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p10: Imm4p10 */
{ "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p8: Imm5p8 */
{ "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p3: Imm5p3 */
{ "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm6p2: Imm6p2 */
{ "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p23: Imm5p23 */
{ "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p25: Imm3p25 */
{ "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p0: Imm8p0 */
{ "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p0: sImm8p0 */
{ "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p20: sImm8p20 */
{ "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p20: Imm8p20 */
{ "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* crop: $CRo Pn */
{ "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqp: $CRq Pn */
{ "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpp: $CRp Pn */
{ "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-2: filler */
{ "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-3: filler */
{ "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-4: filler */
{ "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-5: filler */
{ "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm16p0: comment */
{ "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
{ 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm16p0: comment */
{ "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
{ 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2rm: reg Rm */
{ "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
{ 0, { &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2crn: copro Rn (0-31, 64-bit */
{ "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
{ 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc2ccrn: copro control reg CCRn */
{ "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* ivc2c3ccrn: copro control reg CCRn */
{ "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
{ 2, { &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
};

9
opcodes/mep-dis.c
View File

@ -65,11 +65,8 @@ static int read_insn
#define CGEN_VALIDATE_INSN_SUPPORTED
static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void
print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
@ -79,7 +76,7 @@ print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
}
static void
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
@ -722,7 +719,7 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
/* -- opc.c */
void mep_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

114
opcodes/mt-desc.c
View File

@ -197,7 +197,7 @@ const CGEN_HW_ENTRY mt_cgen_hw_table[] =
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -312,227 +312,227 @@ const CGEN_OPERAND mt_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
{ 0, { &mt_cgen_ifld_table[MT_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr1: register */
{ "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
{ 0, { &mt_cgen_ifld_table[MT_F_SR1] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr2: register */
{ "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
{ 0, { &mt_cgen_ifld_table[MT_F_SR2] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdr: register */
{ "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_DR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdrrr: register */
{ "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_DRRR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: immediate value - sign extd */
{ "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16z: immediate value - zero extd */
{ "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
{ 0, { &mt_cgen_ifld_table[MT_F_IMM16U] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16o: immediate value */
{ "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rc: rc */
{ "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rcnum: rcnum */
{ "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RCNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* contnum: context number */
{ "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CONTNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rbbc: omega network configuration */
{ "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RBBC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* colnum: column number */
{ "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
{ 0, { &mt_cgen_ifld_table[MT_F_COLNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum: row number */
{ "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
{ 0, { &mt_cgen_ifld_table[MT_F_ROWNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum1: row number */
{ "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
{ 0, { &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum2: row number */
{ "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
{ 0, { &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc1: rc1 */
{ "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RC1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc2: rc2 */
{ "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbrb: data-bus orientation */
{ "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CBRB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cell: cell */
{ "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CELL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dup: dup */
{ "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
{ 0, { &mt_cgen_ifld_table[MT_F_DUP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ctxdisp: context displacement */
{ "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CTXDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbdisp: frame buffer displacement */
{ "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
{ 0, { &mt_cgen_ifld_table[MT_F_FBDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* type: type */
{ "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
{ 0, { &mt_cgen_ifld_table[MT_F_TYPE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
{ "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
{ 0, { &mt_cgen_ifld_table[MT_F_MASK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bankaddr: bank address */
{ "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_BANKADDR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incamt: increment amount */
{ "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
{ 0, { &mt_cgen_ifld_table[MT_F_INCAMT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* xmode: xmode */
{ "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
{ 0, { &mt_cgen_ifld_table[MT_F_XMODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask1: mask1 */
{ "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
{ 0, { &mt_cgen_ifld_table[MT_F_MASK1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball: b_all */
{ "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
{ 0, { &mt_cgen_ifld_table[MT_F_BALL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc: b_r_c */
{ "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
{ 0, { &mt_cgen_ifld_table[MT_F_BRC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rda: rd */
{ "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RDA] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* wr: wr */
{ "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_WR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball2: b_all2 */
{ "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
{ 0, { &mt_cgen_ifld_table[MT_F_BALL2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc2: b_r_c2 */
{ "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
{ 0, { &mt_cgen_ifld_table[MT_F_BRC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* perm: perm */
{ "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
{ 0, { &mt_cgen_ifld_table[MT_F_PERM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* a23: a23 */
{ "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
{ 0, { &mt_cgen_ifld_table[MT_F_A23] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cr: c-r */
{ "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbs: cbs */
{ "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CBS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incr: incr */
{ "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_INCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* length: length */
{ "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
{ 0, { &mt_cgen_ifld_table[MT_F_LENGTH] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbx: cbx */
{ "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccb: ccb */
{ "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CCB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cdb: cdb */
{ "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CDB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mode: mode */
{ "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
{ 0, { &mt_cgen_ifld_table[MT_F_MODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* id: i/d */
{ "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
{ 0, { &mt_cgen_ifld_table[MT_F_ID] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* size: size */
{ "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
{ 0, { &mt_cgen_ifld_table[MT_F_SIZE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbincr: fb incr */
{ "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_FBINCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* loopsize: immediate value */
{ "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
{ 0, { &mt_cgen_ifld_table[MT_F_LOOPO] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
/* imm16l: immediate value */
{ "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
{ 0, { &mt_cgen_ifld_table[MT_F_IMM16L] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* rc3: rc3 */
{ "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
{ 0, { &mt_cgen_ifld_table[MT_F_RC3] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1sel: cb1sel */
{ "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CB1SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb2sel: cb2sel */
{ "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CB2SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1incr: cb1incr */
{ "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CB1INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* cb2incr: cb2incr */
{ "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
{ 0, { &mt_cgen_ifld_table[MT_F_CB2INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

5
opcodes/mt-dis.c
View File

@ -59,9 +59,6 @@ static int read_insn
/* -- disassembler routines inserted here. */
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
@ -92,7 +89,7 @@ print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void mt_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

106
opcodes/or1k-desc.c
View File

@ -237,8 +237,8 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-fd32r", HW_H_FD32R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-i64r", HW_H_I64R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
@ -953,33 +953,33 @@ const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
{ 0, { (const PTR) 0 } }
{ 0, { &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
{ 0, { (const PTR) 0 } }
{ 0, { &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD OR1K_F_RDD32_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RDOFF_10_1] } },
{ 0, { (const PTR) 0 } }
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_RDOFF_10_1] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD OR1K_F_RAD32_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RAOFF_9_1] } },
{ 0, { (const PTR) 0 } }
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_RAOFF_9_1] } },
{ 0, { 0 } }
};
const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RBOFF_8_1] } },
{ 0, { (const PTR) 0 } }
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_RBOFF_8_1] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -991,147 +991,147 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sys-sr: supervision register */
{ "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-esr0: exception supervision register 0 */
{ "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-epcr0: exception PC register 0 */
{ "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-sr-lee: SR little endian enable bit */
{ "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-sr-f: SR flag bit */
{ "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-sr-cy: SR carry bit */
{ "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-sr-ov: SR overflow bit */
{ "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-sr-ove: SR overflow exception enable bit */
{ "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
{ "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-cpucfgr-nd: CPUCFGR no delay bit */
{ "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sys-fpcsr-rm: floating point round mode */
{ "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* mac-machi: MAC HI result register */
{ "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* mac-maclo: MAC LO result register */
{ "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* atomic-reserve: atomic reserve flag */
{ "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* atomic-address: atomic address */
{ "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* uimm6: uimm6 */
{ "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rD: destination register */
{ "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rA: source register A */
{ "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rB: source register B */
{ "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* disp26: pc-rel 26 bit */
{ "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* disp21: pc-rel 21 bit */
{ "disp21", OR1K_OPERAND_DISP21, HW_H_IADDR, 20, 21,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP21] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_DISP21] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* simm16: 16-bit signed immediate */
{ "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* uimm16: 16-bit unsigned immediate */
{ "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* simm16-split: split 16-bit signed immediate */
{ "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16,
{ 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* uimm16-split: split 16-bit unsigned immediate */
{ "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16,
{ 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rDSF: destination register (single floating point mode) */
{ "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rASF: source register A (single floating point mode) */
{ "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rBSF: source register B (single floating point mode) */
{ "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rDD32F: destination register (double floating point pair) */
{ "rDD32F", OR1K_OPERAND_RDD32F, HW_H_FD32R, 10, 6,
{ 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RDD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rDDI: destination register (double integer pair) */
{ "rDDI", OR1K_OPERAND_RDDI, HW_H_I64R, 10, 6,
{ 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RDD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rAD32F: source register A (double floating point pair) */
{ "rAD32F", OR1K_OPERAND_RAD32F, HW_H_FD32R, 9, 6,
{ 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RAD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rADI: source register A (double integer pair) */
{ "rADI", OR1K_OPERAND_RADI, HW_H_I64R, 9, 6,
{ 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RAD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rBD32F: source register B (double floating point pair) */
{ "rBD32F", OR1K_OPERAND_RBD32F, HW_H_FD32R, 8, 6,
{ 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RBD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* rBDI: source register B (double integer pair) */
{ "rBDI", OR1K_OPERAND_RBDI, HW_H_I64R, 8, 6,
{ 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
{ 2, { &OR1K_F_RBD32_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/or1k-dis.c
View File

@ -81,7 +81,7 @@ print_regpair (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void or1k_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

162
opcodes/xc16x-desc.c
View File

@ -634,21 +634,21 @@ const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
@ -740,267 +740,267 @@ const CGEN_OPERAND xc16x_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sr: source register */
{ "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dr: destination register */
{ "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dri: destination register */
{ "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* srb: source register */
{ "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* drb: destination register */
{ "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sr2: 2 bit source register */
{ "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R0] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src1: source register 1 */
{ "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src2: source register 2 */
{ "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* srdiv: source register 2 */
{ "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* RegNam: PSW bits */
{ "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm2: 2 bit unsigned number */
{ "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm3: 3 bit unsigned number */
{ "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm4: 4 bit unsigned number */
{ "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm7: 7 bit trap number */
{ "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
{ 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm8: 8 bit unsigned immediate */
{ "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* upof16: 16 bit unsigned immediate */
{ "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
{ 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* reg8: 8 bit word register number */
{ "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* regmem8: 8 bit word register number */
{ "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* regbmem8: 8 bit byte register number */
{ "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* regoff8: 8 bit word register number */
{ "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reghi8: 8 bit word register number */
{ "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* regb8: 8 bit byte register number */
{ "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* genreg: 8 bit word register number */
{ "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* seg: 8 bit segment number */
{ "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* seghi8: 8 bit hi segment number */
{ "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* caddr: 16 bit address offset */
{ "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rel: 8 bit signed relative offset */
{ "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* relhi: hi 8 bit signed relative offset */
{ "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* condbit: condition bit */
{ "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bit1: gap of 1 bit */
{ "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bit2: gap of 2 bits */
{ "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bit4: gap of 4 bits */
{ "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lbit4: gap of 4 bits */
{ "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lbit2: gap of 2 bits */
{ "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bit8: gap of 8 bits */
{ "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* u4: gap of 4 bits */
{ "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitone: field of 1 bit */
{ "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bit01: field of 1 bit */
{ "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cond: condition code */
{ "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* icond: indirect condition code */
{ "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* extcond: extended condition code */
{ "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* memory: 16 bit memory */
{ "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* memgr8: 16 bit memory */
{ "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* qbit: bit addr */
{ "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
{ 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* qlobit: bit addr */
{ "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
{ 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* qhibit: bit addr */
{ "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
{ 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* mask8: 8 bit mask */
{ "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* masklo8: 8 bit mask */
{ "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* pagenum: 10 bit page number */
{ "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* data8: 8 bit data */
{ "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* datahi8: 8 bit data */
{ "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* sgtdisbit: segmentation enable bit */
{ "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* upag16: 16 bit unsigned immediate */
{ "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
{ 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* useg8: 8 bit segment */
{ "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
{ 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* useg16: 16 bit address offset */
{ "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* usof16: 16 bit address offset */
{ "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
{ 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0, { &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
{ 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* hash: # prefix */
{ "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dot: . prefix */
{ "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* pof: pof: prefix */
{ "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* pag: pag: prefix */
{ "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sof: sof: prefix */
{ "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* segm: seg: prefix */
{ "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/xc16x-dis.c
View File

@ -201,7 +201,7 @@ print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void xc16x_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement

96
opcodes/xstormy16-desc.c
View File

@ -230,9 +230,9 @@ const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
@ -241,8 +241,8 @@ const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
{ "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@ -308,9 +308,9 @@ const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
{ 0, { (const PTR) 0 } }
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
{ 0, { 0 } }
};
/* The operand table. */
@ -322,163 +322,163 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-z8: */
{ "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-z16: */
{ "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-cy: */
{ "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-hc: */
{ "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-ov: */
{ "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-pt: */
{ "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psw-s: */
{ "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Rd: general register destination */
{ "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rdm: general register destination */
{ "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rm: general register for memory */
{ "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs: general register source */
{ "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rb: base register */
{ "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rbj: base register for jump */
{ "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bcond2: branch condition opcode */
{ "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ws2: word size opcode */
{ "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bcond5: branch condition opcode */
{ "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm2: 2 bit unsigned immediate */
{ "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm3: 3 bit unsigned immediate */
{ "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm3b: 3 bit unsigned immediate for bit tests */
{ "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm4: 4 bit unsigned immediate */
{ "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm8: 8 bit unsigned immediate */
{ "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm8small: 8 bit unsigned immediate */
{ "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm12: 12 bit signed immediate */
{ "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: 16 bit immediate */
{ "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* lmem8: 8 bit unsigned immediate low memory */
{ "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* hmem8: 8 bit unsigned immediate high memory */
{ "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rel8-2: 8 bit relative address */
{ "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rel8-4: 8 bit relative address */
{ "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rel12: 12 bit relative address */
{ "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rel12a: 12 bit relative address */
{ "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
{ 0, { &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* abs24: 24 bit absolute address */
{ "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
{ 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
{ 2, { &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* psw: program status word */
{ "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Rpsw: N0-N3 of the program status word */
{ "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sp: stack pointer */
{ "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* R0: R0 */
{ "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* R1: R1 */
{ "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* R2: R2 */
{ "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* R8: R8 */
{ "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};

2
opcodes/xstormy16-dis.c
View File

@ -60,7 +60,7 @@ static int read_insn
void xstormy16_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement