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https://sourceware.org/git/binutils-gdb.git
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AArch64/Arm: Update testcases fixing endiannes and linux targets
This fixes the testcases that are failing due to my recent patch. It turns out that the start address across baremetal and linux builds isn't entirely predictable without a linker script. Since the address themselves are not the important thing I am ignoring them now. Secondly I was encoding data using .word using non 0 values, however because .word is subjected to endiannes these non-zero values under big-endian happen to fall into the encoding space of instructions which changes the disassembly. Using 0 fixes this problem and the purpose of the test still holds, though objdump will dump ... for data only sections, which is ok as the data/insn mixed sections will test the patch. The ARM Attributes sections is not important and is ignored. binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order.s: Likewise. * testsuite/binutils-all/arm/in-order-all.d: Likewise. * testsuite/binutils-all/arm/in-order.d: Likewise. * testsuite/binutils-all/arm/out-of-order-all.d: Likewise. * testsuite/binutils-all/arm/out-of-order.d: Likewise. * testsuite/binutils-all/arm/out-of-order.s: Likewise.
This commit is contained in:
Tamar Christina
parent
974c89e088
commit
05805feba2
@ -1,3 +1,16 @@
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2019-03-26 Tamar Christina <tamar.christina@arm.com>
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* testsuite/binutils-all/aarch64/in-order-all.d: Update.
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* testsuite/binutils-all/aarch64/in-order.d: Likewise.
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* testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.
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* testsuite/binutils-all/aarch64/out-of-order.d: Likewise.
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* testsuite/binutils-all/aarch64/out-of-order.s: Likewise.
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* testsuite/binutils-all/arm/in-order-all.d: Likewise.
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* testsuite/binutils-all/arm/in-order.d: Likewise.
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* testsuite/binutils-all/arm/out-of-order-all.d: Likewise.
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* testsuite/binutils-all/arm/out-of-order.d: Likewise.
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* testsuite/binutils-all/arm/out-of-order.s: Likewise.
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2019-03-26 Nick Clifton <nickc@redhat.com>
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* MAINTAINERS: Take over Dave Brolley's maintainerships for FR30,
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@ -8,36 +8,31 @@
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Disassembly of section \.func1:
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0000000000400000 <v1>:
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400000: 8b010000 add x0, x0, x1
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400004: 00000000 \.inst 0x00000000 ; undefined
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.+ <v1>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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Disassembly of section \.func2:
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0000000000400008 <\.func2>:
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400008: 8b010000 add x0, x0, x1
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.+ <\.func2>:
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[^:]+: 8b010000 add x0, x0, x1
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Disassembly of section \.func3:
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000000000040000c <\.func3>:
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40000c: 8b010000 add x0, x0, x1
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400010: 8b010000 add x0, x0, x1
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400014: 8b010000 add x0, x0, x1
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400018: 8b010000 add x0, x0, x1
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40001c: 8b010000 add x0, x0, x1
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400020: 00000000 \.inst 0x00000000 ; undefined
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.+ <\.func3>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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Disassembly of section \.rodata:
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0000000000400024 <\.rodata>:
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400024: 00000004 \.inst 0x00000004 ; undefined
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.+ <\.rodata>:
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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Disassembly of section .global:
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0000000000410028 <__data_start>:
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410028: 00000001 \.inst 0x00000001 ; undefined
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41002c: 00000000 \.inst 0x00000000 ; undefined
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410030: 00000001 \.inst 0x00000001 ; undefined
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410034: 00000000 \.inst 0x00000000 ; undefined
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410038: 00000001 \.inst 0x00000001 ; undefined
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41003c: 00000000 \.inst 0x00000000 ; undefined
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.+ <.+>:
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...
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@ -8,21 +8,21 @@
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Disassembly of section \.func1:
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0000000000400000 <v1>:
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400000: 8b010000 add x0, x0, x1
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400004: 00000000 \.word 0x00000000
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.+ <v1>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.word 0x00000000
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Disassembly of section .func2:
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0000000000400008 <\.func2>:
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400008: 8b010000 add x0, x0, x1
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.+ <\.func2>:
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[^:]+: 8b010000 add x0, x0, x1
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Disassembly of section \.func3:
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000000000040000c <\.func3>:
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40000c: 8b010000 add x0, x0, x1
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400010: 8b010000 add x0, x0, x1
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400014: 8b010000 add x0, x0, x1
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400018: 8b010000 add x0, x0, x1
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40001c: 8b010000 add x0, x0, x1
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400020: 00000000 \.word 0x00000000
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.+ <\.func3>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.word 0x00000000
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@ -8,36 +8,31 @@
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Disassembly of section \.global:
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00000000ffe00000 <\.global>:
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ffe00000: 00000001 \.inst 0x00000001 ; undefined
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ffe00004: 00000000 \.inst 0x00000000 ; undefined
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ffe00008: 00000001 \.inst 0x00000001 ; undefined
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ffe0000c: 00000000 \.inst 0x00000000 ; undefined
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ffe00010: 00000001 \.inst 0x00000001 ; undefined
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ffe00014: 00000000 \.inst 0x00000000 ; undefined
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.+ <\.global>:
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...
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Disassembly of section \.func2:
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0000000004018280 <\.func2>:
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4018280: 8b010000 add x0, x0, x1
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.+ <\.func2>:
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[^:]+: 8b010000 add x0, x0, x1
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Disassembly of section \.func1:
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0000000004005000 <v1>:
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4005000: 8b010000 add x0, x0, x1
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4005004: 00000000 \.inst 0x00000000 ; undefined
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.+ <v1>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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Disassembly of section \.func3:
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0000000004015000 <\.func3>:
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4015000: 8b010000 add x0, x0, x1
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4015004: 8b010000 add x0, x0, x1
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4015008: 8b010000 add x0, x0, x1
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401500c: 8b010000 add x0, x0, x1
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4015010: 8b010000 add x0, x0, x1
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4015014: 00000000 \.inst 0x00000000 ; undefined
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.+ <\.func3>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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Disassembly of section \.rodata:
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0000000004015018 <\.rodata>:
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4015018: 00000004 \.inst 0x00000004 ; undefined
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.+ <\.rodata>:
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[^:]+: 00000000 \.inst 0x00000000 ; undefined
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@ -7,21 +7,21 @@
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Disassembly of section \.func2:
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0000000004018280 <\.func2>:
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4018280: 8b010000 add x0, x0, x1
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.+ <\.func2>:
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[^:]+: 8b010000 add x0, x0, x1
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Disassembly of section \.func1:
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0000000004005000 <v1>:
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4005000: 8b010000 add x0, x0, x1
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4005004: 00000000 \.word 0x00000000
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.+ <v1>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.word 0x00000000
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Disassembly of section \.func3:
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0000000004015000 <\.func3>:
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4015000: 8b010000 add x0, x0, x1
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4015004: 8b010000 add x0, x0, x1
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4015008: 8b010000 add x0, x0, x1
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401500c: 8b010000 add x0, x0, x1
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4015010: 8b010000 add x0, x0, x1
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4015014: 00000000 \.word 0x00000000
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.+ <\.func3>:
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 8b010000 add x0, x0, x1
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[^:]+: 00000000 \.word 0x00000000
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@ -20,9 +20,9 @@ v1:
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.data
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.section .global,"aw",@progbits
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.xword 1
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.xword 1
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.xword 1
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.xword 0
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.xword 0
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.xword 0
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.section .rodata
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.word 4
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.word 0
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@ -8,43 +8,41 @@
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Disassembly of section \.func1:
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00400000 <v1>:
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400000: e0800001 add r0, r0, r1
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400004: 00000000 andeq r0, r0, r0
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.+ <v1>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.func2:
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00400008 <\.func2>:
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400008: e0800001 add r0, r0, r1
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.+ <\.func2>:
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[^:]+: e0800001 add r0, r0, r1
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Disassembly of section \.func3:
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0040000c <\.func3>:
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40000c: e0800001 add r0, r0, r1
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400010: e0800001 add r0, r0, r1
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400014: e0800001 add r0, r0, r1
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400018: e0800001 add r0, r0, r1
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40001c: e0800001 add r0, r0, r1
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400020: 00000000 andeq r0, r0, r0
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.+ <\.func3>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.rodata:
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00400024 <\.rodata>:
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400024: 00000004 andeq r0, r0, r4
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.+ <\.rodata>:
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.global:
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00410028 <__data_start>:
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410028: 00000001 andeq r0, r0, r1
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41002c: 00000001 andeq r0, r0, r1
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410030: 00000001 andeq r0, r0, r1
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.+ <.+>:
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...
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Disassembly of section \.ARM\.attributes:
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00000000 <\.ARM\.attributes>:
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0: 00001141 andeq r1, r0, r1, asr #2
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4: 61656100 cmnvs r5, r0, lsl #2
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8: 01006962 tsteq r0, r2, ror #18
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c: 00000007 andeq r0, r0, r7
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10: Address 0x0000000000000010 is out of bounds.
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.+ <\.ARM\.attributes>:
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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@ -8,21 +8,21 @@
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Disassembly of section \.func1:
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00400000 <v1>:
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400000: e0800001 add r0, r0, r1
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400004: 00000000 \.word 0x00000000
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.+ <v1>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 \.word 0x00000000
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Disassembly of section \.func2:
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00400008 <\.func2>:
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400008: e0800001 add r0, r0, r1
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.+ <\.func2>:
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[^:]+: e0800001 add r0, r0, r1
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Disassembly of section \.func3:
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0040000c <\.func3>:
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40000c: e0800001 add r0, r0, r1
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400010: e0800001 add r0, r0, r1
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400014: e0800001 add r0, r0, r1
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400018: e0800001 add r0, r0, r1
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40001c: e0800001 add r0, r0, r1
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400020: 00000000 \.word 0x00000000
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.+ <\.func3>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 \.word 0x00000000
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@ -8,43 +8,41 @@
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Disassembly of section \.global:
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ffe00000 <\.global>:
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ffe00000: 00000001 andeq r0, r0, r1
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ffe00004: 00000001 andeq r0, r0, r1
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ffe00008: 00000001 andeq r0, r0, r1
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.+ <\.global>:
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...
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Disassembly of section \.func2:
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04018280 <\.func2>:
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4018280: e0800001 add r0, r0, r1
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.+ <\.func2>:
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[^:]+: e0800001 add r0, r0, r1
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Disassembly of section \.func1:
|
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04005000 <v1>:
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4005000: e0800001 add r0, r0, r1
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4005004: 00000000 andeq r0, r0, r0
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.+ <v1>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 andeq r0, r0, r0
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|
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Disassembly of section \.func3:
|
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|
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04015000 <\.func3>:
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4015000: e0800001 add r0, r0, r1
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4015004: e0800001 add r0, r0, r1
|
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4015008: e0800001 add r0, r0, r1
|
||||
401500c: e0800001 add r0, r0, r1
|
||||
4015010: e0800001 add r0, r0, r1
|
||||
4015014: 00000000 andeq r0, r0, r0
|
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.+ <\.func3>:
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: 00000000 andeq r0, r0, r0
|
||||
|
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Disassembly of section \.rodata:
|
||||
|
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04015018 <\.rodata>:
|
||||
4015018: 00000004 andeq r0, r0, r4
|
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.+ <\.rodata>:
|
||||
[^:]+: 00000000 andeq r0, r0, r0
|
||||
|
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Disassembly of section \.ARM\.attributes:
|
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|
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00000000 <\.ARM\.attributes>:
|
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0: 00001141 andeq r1, r0, r1, asr #2
|
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4: 61656100 cmnvs r5, r0, lsl #2
|
||||
8: 01006962 tsteq r0, r2, ror #18
|
||||
c: 00000007 andeq r0, r0, r7
|
||||
10: Address 0x0000000000000010 is out of bounds.
|
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.+ <\.ARM\.attributes>:
|
||||
[^:]+: .+
|
||||
[^:]+: .+
|
||||
[^:]+: .+
|
||||
[^:]+: .+
|
||||
[^:]+: .+
|
||||
|
||||
|
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@ -7,21 +7,21 @@
|
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|
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Disassembly of section \.func2:
|
||||
|
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04018280 <\.func2>:
|
||||
4018280: e0800001 add r0, r0, r1
|
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.+ <\.func2>:
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
|
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Disassembly of section \.func1:
|
||||
|
||||
04005000 <v1>:
|
||||
4005000: e0800001 add r0, r0, r1
|
||||
4005004: 00000000 \.word 0x00000000
|
||||
.+ <v1>:
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: 00000000 \.word 0x00000000
|
||||
|
||||
Disassembly of section \.func3:
|
||||
|
||||
04015000 <\.func3>:
|
||||
4015000: e0800001 add r0, r0, r1
|
||||
4015004: e0800001 add r0, r0, r1
|
||||
4015008: e0800001 add r0, r0, r1
|
||||
401500c: e0800001 add r0, r0, r1
|
||||
4015010: e0800001 add r0, r0, r1
|
||||
4015014: 00000000 \.word 0x00000000
|
||||
.+ <\.func3>:
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: e0800001 add r0, r0, r1
|
||||
[^:]+: 00000000 \.word 0x00000000
|
||||
|
||||
@ -21,9 +21,9 @@ v1:
|
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|
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.data
|
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.section .global,"aw",%progbits
|
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.word 1
|
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.word 1
|
||||
.word 1
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
|
||||
.section .rodata
|
||||
.word 4
|
||||
.word 0
|
||||
|
||||
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Reference in New Issue
Block a user