* mips16-opc.c: Add entries for argumentless "entry" and "exit"
	instructions.

gas/testsuite/
	* gas/mips/mips16.d, gas/mips/mips16-64.d: Remove trailing whitespace
	from ENTRY and EXIT lines.
This commit is contained in:
Richard Sandiford 2013-07-07 10:27:32 +00:00
parent 5c324c169b
commit 04c9d415c0
5 changed files with 16 additions and 4 deletions

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@ -1,3 +1,8 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/mips16.d, gas/mips/mips16-64.d: Remove trailing whitespace
from ENTRY and EXIT lines.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.

View File

@ -670,12 +670,12 @@ Disassembly of section .text:
84c: R_MIPS_NONE \*ABS\*
84c: R_MIPS_NONE \*ABS\*
850: 6500 nop
852: e809 entry
852: e809 entry
854: e909 entry a0
856: eb49 entry a0-a2,s0
858: e8a9 entry s0-s1,ra
85a: e829 entry ra
85c: ef09 exit
85c: ef09 exit
85e: ef49 exit s0
860: efa9 exit s0-s1,ra
862: ef29 exit ra

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@ -667,12 +667,12 @@ Disassembly of section .text:
84c: 1800 0000 jal 0 <data1>
84c: R_MIPS16_26 extern
850: 6500 nop
852: e809 entry
852: e809 entry
854: e909 entry a0
856: eb49 entry a0-a2,s0
858: e8a9 entry s0-s1,ra
85a: e829 entry ra
85c: ef09 exit
85c: ef09 exit
85e: ef49 exit s0
860: efa9 exit s0-s1,ra
862: ef29 exit ra

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@ -1,3 +1,8 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips16-opc.c: Add entries for argumentless "entry" and "exit"
instructions.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400

View File

@ -159,7 +159,9 @@ const struct mips_opcode mips16_opcodes[] =
{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 },
{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 },
{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 },
{"exit", "", 0xef09, 0xffff, TRAP, 0, I1 },
{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1 },
{"entry", "", 0xe809, 0xffff, TRAP, 0, I1 },
{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1 },
{"extend", "e", 0xf000, 0xf800, 0, 0, I1 },
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },