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2007-04-18 Paul Brook <paul@codesourcery.com>
gas/testsuite/ * gas/arm/thumb2_add.s: Add rsb #0 test. * gas/arm/thumb2_add.d: Update expected output. gas/ * config/tc-arm.c (do_t_rsb): Use 16-bit encoding when possible.
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@ -1,3 +1,7 @@
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2007-04-18 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (do_t_rsb): Use 16-bit encoding when possible.
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2007-04-16 Kaz Kojima <kkojima@rr.iij4u.or.jp>
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* config/tc-sh.c (sh_handle_align): Call as_bad_where instead
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@ -9956,8 +9956,37 @@ do_t_rsb (void)
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inst.instruction |= Rs << 16;
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if (!inst.operands[2].isreg)
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{
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inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
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inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
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bfd_boolean narrow;
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if ((inst.instruction & 0x00100000) != 0)
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narrow = (current_it_mask == 0);
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else
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narrow = (current_it_mask != 0);
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if (Rd > 7 || Rs > 7)
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narrow = FALSE;
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if (inst.size_req == 4 || !unified_syntax)
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narrow = FALSE;
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if (inst.reloc.exp.X_op != O_constant
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|| inst.reloc.exp.X_add_number != 0)
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narrow = FALSE;
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/* Turn rsb #0 into 16-bit neg. We should probably do this via
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relaxation, but it doesn't seem worth the hassle. */
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if (narrow)
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{
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inst.reloc.type = BFD_RELOC_UNUSED;
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inst.instruction = THUMB_OP16 (T_MNEM_negs);
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inst.instruction |= Rs << 3;
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inst.instruction |= Rd;
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}
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else
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{
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inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
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inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
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}
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}
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else
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encode_thumb32_shifted_operand (2);
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@ -1,3 +1,8 @@
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2007-04-18 Paul Brook <paul@codesourcery.com>
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* gas/arm/thumb2_add.s: Add rsb #0 test.
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* gas/arm/thumb2_add.d: Update expected output.
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2007-04-04 Paul Brook <paul@codesourcery.com>
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* gas/arm/neon-cov.s: Add new vext test.
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@ -27,4 +27,4 @@ Disassembly of section .text:
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0+04c <[^>]+> a840 add r0, sp, #256
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0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400
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0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101
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0+056 <[^>]+> bf00 nop
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0+056 <[^>]+> 4271 negs r1, r6
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@ -28,4 +28,4 @@ thumb2_add:
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add r0, sp, #0x100
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add r5, sp, #0x400
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add r9, sp, #0x101
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nop
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rsbs r1, r6, #0
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