aarch64: New instructions for maintenance of GPT entries cached in a TLB

This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS,
PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm
Management Extension).

gas/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Update news.
	* testsuite/gas/aarch64/rme.d: Update test.
	* testsuite/gas/aarch64/rme.s: Update test.

opcodes/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for
	TLBI instruction.
This commit is contained in:
Przemyslaw Wirkus 2021-04-19 15:00:07 +01:00
parent cd6608e49d
commit 02202574ec
6 changed files with 28 additions and 0 deletions

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@ -1,3 +1,9 @@
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update news.
* testsuite/gas/aarch64/rme.d: Update test.
* testsuite/gas/aarch64/rme.s: Update test.
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme.d: Update test.

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@ -2,6 +2,8 @@
* arm-symbianelf support removed.
* Add support for Realm Management Extension (RME) for AArch64.
Changes in 2.36:
* Add support for Intel AVX VNNI instructions.

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@ -14,3 +14,7 @@ Disassembly of section \.text:
10: d51e2180 msr gptbr_el3, x0
14: d50e7e20 dc cipapa, x0
18: d50e7ea0 dc cigdpapa, x0
1c: d50e8460 tlbi rpaos, x0
20: d50e84e0 tlbi rpalos, x0
24: d50e819f tlbi paallos
28: d50e879f tlbi paall

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@ -12,3 +12,9 @@ msr gptbr_el3, x0
/* RME data cache maintenance operations. */
dc cipapa, x0
dc cigdpapa, x0
/* RME instructions for maintenance of GPT entries cached in a TLB. */
tlbi rpaos, x0
tlbi rpalos, x0
tlbi paallos
tlbi paall

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@ -1,3 +1,8 @@
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
for TLBI instruction.
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for

View File

@ -4870,6 +4870,11 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
{ "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
{ "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
{ "rpaos", CPENS (6, C8, C4, 3), F_HASXT },
{ "rpalos", CPENS (6, C8, C4, 7), F_HASXT },
{ "paallos", CPENS (6, C8, C1, 4), 0},
{ "paall", CPENS (6, C8, C7, 4), 0},
{ 0, CPENS(0,0,0,0), 0 }
};