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aarch64: New instructions for maintenance of GPT entries cached in a TLB
This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.
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@ -1,3 +1,9 @@
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2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
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* NEWS: Update news.
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* testsuite/gas/aarch64/rme.d: Update test.
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* testsuite/gas/aarch64/rme.s: Update test.
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2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
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* testsuite/gas/aarch64/rme.d: Update test.
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gas/NEWS
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gas/NEWS
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* arm-symbianelf support removed.
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* Add support for Realm Management Extension (RME) for AArch64.
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Changes in 2.36:
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* Add support for Intel AVX VNNI instructions.
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@ -14,3 +14,7 @@ Disassembly of section \.text:
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10: d51e2180 msr gptbr_el3, x0
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14: d50e7e20 dc cipapa, x0
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18: d50e7ea0 dc cigdpapa, x0
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1c: d50e8460 tlbi rpaos, x0
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20: d50e84e0 tlbi rpalos, x0
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24: d50e819f tlbi paallos
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28: d50e879f tlbi paall
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@ -12,3 +12,9 @@ msr gptbr_el3, x0
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/* RME data cache maintenance operations. */
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dc cipapa, x0
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dc cigdpapa, x0
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/* RME instructions for maintenance of GPT entries cached in a TLB. */
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tlbi rpaos, x0
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tlbi rpalos, x0
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tlbi paallos
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tlbi paall
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@ -1,3 +1,8 @@
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2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
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* aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
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for TLBI instruction.
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2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
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* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
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@ -4870,6 +4870,11 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
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{ "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
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{ "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
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{ "rpaos", CPENS (6, C8, C4, 3), F_HASXT },
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{ "rpalos", CPENS (6, C8, C4, 7), F_HASXT },
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{ "paallos", CPENS (6, C8, C1, 4), 0},
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{ "paall", CPENS (6, C8, C7, 4), 0},
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{ 0, CPENS(0,0,0,0), 0 }
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};
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