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Fix incorrect register mask.
PR gold/22213 * sparc.cc (Target_sparc): Fix incorrect register mask.
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@ -1,3 +1,8 @@
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2017-09-26 Cary Coutant <ccoutant@gmail.com>
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PR gold/22213
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* sparc.cc (Target_sparc): Fix incorrect register mask.
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2017-09-22 Jim Wilson <jim.wilson@linaro.org>
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2017-09-22 Jim Wilson <jim.wilson@linaro.org>
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* aarch64.cc (Target_aarch64::aarch64_info): Set
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* aarch64.cc (Target_aarch64::aarch64_info): Set
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@ -4164,7 +4164,7 @@ Target_sparc<size, big_endian>::Relocate::relax_call(
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if (op3 != 0x3d)
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if (op3 != 0x3d)
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{
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{
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// First check RS1
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// First check RS1
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reg = (delay_insn >> 14) & 0x15;
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reg = (delay_insn >> 14) & 0x1f;
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if (reg == 15)
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if (reg == 15)
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return;
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return;
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