binutils-gdb/gas/doc/c-sh.texi

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@c Copyright (C) 1991-2014 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Renesas / SuperH SH Dependent Features
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@cindex SH support
@menu
* SH Options:: Options
* SH Syntax:: Syntax
* SH Floating Point:: Floating Point
* SH Directives:: SH Machine Directives
* SH Opcodes:: Opcodes
@end menu
@node SH Options
@section Options
@cindex SH options
@cindex options, SH
@code{@value{AS}} has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.
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@table @code
@kindex --little
@kindex --big
@kindex --relax
@kindex --small
@kindex --dsp
@kindex --renesas
@kindex --allow-reg-prefix
@item --little
Generate little endian code.
@item --big
Generate big endian code.
@item --relax
Alter jump instructions for long displacements.
@item --small
Align sections to 4 byte boundaries, not 16.
@item --dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item --renesas
Disable optimization with section symbol for compatibility with
Renesas assembler.
@item --allow-reg-prefix
Allow '$' as a register name prefix.
2010-05-21 Daniel Jacobowitz <dan@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Andrew Stubbs <ams@codesourcery.com> bfd/ * config.bfd (sh-*-uclinux* | sh[12]-*-uclinux*): Add bfd_elf32_shl_vec, and FDPIC vectors to targ_selvecs. * configure.in: Handle FDPIC vectors. * elf32-sh-relocs.h: Add FDPIC and movi20 relocations. * elf32-sh.c (DEFAULT_STACK_SIZE): Define. (SYMBOL_FUNCDESC_LOCAL): Define. Use it instead of SYMBOL_REFERENCES_LOCAL for function descriptors. (fdpic_object_p): New. (sh_reloc_map): Add FDPIC and movi20 relocations. (sh_elf_info_to_howto, sh_elf_relocate_section): Handle new invalid range. (struct elf_sh_plt_info): Add got20 and short_plt. Update all definitions. (FDPIC_PLT_ENTRY_SIZE, FDPIC_PLT_LAZY_OFFSET): Define. (fdpic_sh_plt_entry_be, fdpic_sh_plt_entry_le, fdpic_sh_plts): New. (FDPIC_SH2A_PLT_ENTRY_SIZE, FDPIC_SH2A_PLT_LAZY_OFFSET): Define. (fdpic_sh2a_plt_entry_be, fdpic_sh2a_plt_entry_le) (fdpic_sh2a_short_plt_be, fdpic_sh2a_short_plt_le, fdpic_sh2a_plts): New. (get_plt_info): Handle FDPIC. (MAX_SHORT_PLT): Define. (get_plt_index, get_plt_offset): Handle short_plt. (union gotref): New. (struct elf_sh_link_hash_entry): Add funcdesc, rename tls_type to got_type and adjust all uses. Add GOT_FUNCDESC. (struct sh_elf_obj_tdata): Add local_funcdesc. Rename local_got_tls_type to local_got_type. (sh_elf_local_got_type): Renamed from sh_elf_local_got_tls_type. All users changed. (sh_elf_local_funcdesc): Define. (struct elf_sh_link_hash_table): Add sfuncdesc, srelfuncdesc, fdpic_p, and srofixup. (sh_elf_link_hash_newfunc): Initialize new fields. (sh_elf_link_hash_table_create): Set fdpic_p. (sh_elf_omit_section_dynsym): New. (create_got_section): Create .got.funcdesc, .rela.got.funcdesc and .rofixup. (allocate_dynrelocs): Allocate local function descriptors and space for R_SH_FUNCDESC-related relocations, and for rofixups. Handle GOT_FUNCDESC. Create fixups. Handle GOT entries which require function descriptors. (sh_elf_always_size_sections): Handle PT_GNU_STACK and __stacksize. (sh_elf_modify_program_headers): New. (sh_elf_size_dynamic_sections): Allocate function descriptors for local symbols. Allocate .got.funcdesc contents. Allocate rofixups. Handle local GOT entries of type GOT_FUNCDESC. Create fixups for local GOT entries. Ensure that FDPIC libraries always have a PLTGOT entry in the .dynamic section. (sh_elf_add_dyn_reloc, sh_elf_got_offset, sh_elf_initialize_funcdesc) (sh_elf_add_rofixup, sh_elf_osec_to_segment) (sh_elf_osec_readonly_p, install_movi20_field): New functions. (sh_elf_relocate_section): Handle new relocations, R_SH_FUNCDESC, R_SH_GOTFUNCDESC and R_SH_GOTOFFFUNCDESC. Use sh_elf_got_offset and .got.plt throughout to find _GLOBAL_OFFSET_TABLE_. Add rofixup read-only section warnings. Handle undefined weak symbols. Generate fixups for R_SH_DIR32 and GOT entries. Check for cross-segment relocations and clear EF_SH_PIC. Handle 20-bit relocations. Always generate R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE. (sh_elf_gc_sweep_hook): Handle R_SH_FUNCDESC, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20, and R_SH_GOTOFFFUNCDESC. Handle 20-bit relocations. (sh_elf_copy_indirect_symbol): Copy function descriptor reference counts. (sh_elf_check_relocs): Handle new relocations. Make symbols dynamic for FDPIC relocs. Account for rofixups. Error for FDPIC symbol mismatches. Allocate a GOT for R_SH_DIR32. Allocate fixups for R_SH_DIR32. (sh_elf_copy_private_data): Copy PT_GNU_STACK size. (sh_elf_merge_private_data): Copy initial flags. Do not clobber non-mach flags. Set EF_SH_PIC for FDPIC. Reject FDPIC mismatches. (sh_elf_finish_dynamic_symbol): Do not handle got_funcdesc entries here. Rename sgot to sgotplt and srel to srelplt. Handle short_plt, FDPIC descriptors, and got20. Create R_SH_FUNCDESC_VALUE for FDPIC. Use install_movi20_field. Rename srel to srelgot. Always generate R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE. (sh_elf_finish_dynamic_sections): Fill in the GOT pointer in rofixup. Do not fill in reserved GOT entries for FDPIC. Correct DT_PLTGOT. Rename sgot to sgotplt. Assert that the right number of rofixups and dynamic relocations were allocated. (sh_elf_use_relative_eh_frame, sh_elf_encode_eh_address): New. (elf_backend_omit_section_dynsym): Use sh_elf_omit_section_dynsym. (elf_backend_can_make_relative_eh_frame) (elf_backend_can_make_lsda_relative_eh_frame) (elf_backend_encode_eh_address): Define. (TARGET_BIG_SYM, TARGET_BIG_NAME, TARGET_LITTLE_SYM) (TARGET_LITTLE_NAME, elf_backend_modify_program_headers, elf32_bed): Redefine for FDPIC vector. * reloc.c: Add SH FDPIC and movi20 relocations. * targets.c (_bfd_target_vector): Add FDPIC vectors. * configure, bfd-in2.h, libbfd.h: Regenerated. binutils/ * readelf.c (get_machine_flags): Handle EF_SH_PIC and EF_SH_FDPIC. gas/ * config/tc-sh.c (sh_fdpic): New. (sh_check_fixup): Handle relocations on movi20. (parse_exp): Do not reject PIC operators here. (build_Mytes): Check for unhandled PIC operators here. Use sh_check_fixup for movi20. (enum options): Add OPTION_FDPIC. (md_longopts, md_parse_option, md_show_usage): Add --fdpic. (sh_fix_adjustable, md_apply_fix): Handle FDPIC and movi20 relocations. (sh_elf_final_processing): Handle --fdpic. (sh_uclinux_target_format): New. (sh_parse_name): Handle FDPIC relocation operators. * config/tc-sh.h (TARGET_FORMAT): Define specially for TE_UCLINUX. (sh_uclinux_target_format): Declare for TE_UCLINUX. * configure.tgt (sh-*-uclinux* | sh[12]-*-uclinux*): Set em=uclinux. * doc/c-sh.texi (SH Options): Document --fdpic. gas/testsuite/ * gas/sh/basic.exp: Run new tests. Handle uClinux like Linux. * gas/sh/fdpic.d: New file. * gas/sh/fdpic.s: New file. * gas/sh/reg-prefix.d: Force big-endian. * gas/sh/sh2a-pic.d: New file. * gas/sh/sh2a-pic.s: New file. * lib/gas-defs.exp (is_elf_format): Include sh*-*-uclinux*. include/elf/ * sh.h (EF_SH_PIC, EF_SH_FDPIC): Define. (R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New. Adjust other invalid ranges. (R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20) (R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC) (R_SH_FUNCDESC_VALUE): New. ld/ * Makefile.am (ALL_EMULATIONS): Add eshelf_fd.o and eshlelf_fd.o. (eshelf_fd.c, eshlelf_fd.c): New rules. * Makefile.in: Regenerate. * configure.tgt (sh-*-uclinux*): Add shelf_fd and shlelf_fd emulations. * emulparams/shelf_fd.sh: New file. * emulparams/shlelf_fd.sh: New file. * emulparams/shlelf_linux.sh: Update comment. ld/testsuite/ * ld-sh/sh.exp: Handle uClinux like Linux. * lib/ld-lib.exp (is_elf_format): Include sh*-*-uclinux*. * ld-sh/fdpic-funcdesc-shared.d: New file. * ld-sh/fdpic-funcdesc-shared.s: New file. * ld-sh/fdpic-funcdesc-static.d: New file. * ld-sh/fdpic-funcdesc-static.s: New file. * ld-sh/fdpic-gotfuncdesc-shared.d: New file. * ld-sh/fdpic-gotfuncdesc-shared.s: New file. * ld-sh/fdpic-gotfuncdesc-static.d: New file. * ld-sh/fdpic-gotfuncdesc-static.s: New file. * ld-sh/fdpic-gotfuncdesci20-shared.d: New file. * ld-sh/fdpic-gotfuncdesci20-shared.s: New file. * ld-sh/fdpic-gotfuncdesci20-static.d: New file. * ld-sh/fdpic-gotfuncdesci20-static.s: New file. * ld-sh/fdpic-goti20-shared.d: New file. * ld-sh/fdpic-goti20-shared.s: New file. * ld-sh/fdpic-goti20-static.d: New file. * ld-sh/fdpic-goti20-static.s: New file. * ld-sh/fdpic-gotofffuncdesc-shared.d: New file. * ld-sh/fdpic-gotofffuncdesc-shared.s: New file. * ld-sh/fdpic-gotofffuncdesc-static.d: New file. * ld-sh/fdpic-gotofffuncdesc-static.s: New file. * ld-sh/fdpic-gotofffuncdesci20-shared.d: New file. * ld-sh/fdpic-gotofffuncdesci20-shared.s: New file. * ld-sh/fdpic-gotofffuncdesci20-static.d: New file. * ld-sh/fdpic-gotofffuncdesci20-static.s: New file. * ld-sh/fdpic-gotoffi20-shared.d: New file. * ld-sh/fdpic-gotoffi20-shared.s: New file. * ld-sh/fdpic-gotoffi20-static.d: New file. * ld-sh/fdpic-gotoffi20-static.s: New file. * ld-sh/fdpic-plt-be.d: New file. * ld-sh/fdpic-plt-le.d: New file. * ld-sh/fdpic-plt.s: New file. * ld-sh/fdpic-plti20-be.d: New file. * ld-sh/fdpic-plti20-le.d: New file. * ld-sh/fdpic-stack-default.d: New file. * ld-sh/fdpic-stack-size.d: New file. * ld-sh/fdpic-stack.s: New file.
2010-05-25 22:12:43 +08:00
@kindex --fdpic
@item --fdpic
Generate an FDPIC object file.
@item --isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item --isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item --isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item --isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
@end table
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@node SH Syntax
@section Syntax
@menu
* SH-Chars:: Special Characters
* SH-Regs:: Register Names
* SH-Addressing:: Addressing Modes
@end menu
@node SH-Chars
@subsection Special Characters
@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.
@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.
PR gas/12390 * doc/all.texi: Add NS32K * doc/as.texinfo: Remove target specific details of which characters act as comment initiators and statement separators into individual target specific files. * doc/c-alpha.texi (Alpha-Chars): Document special behaviour of the hash character at the start of a line. * doc/c-arm.texi (ARM-Chars): Likewise. * doc/c-avr.texi (AVR-Chars): Likewise. * doc/c-d10v.texi (D10V-Chars): Likewise. * doc/c-d30v.texi (D30V-Chars): Likewise. * doc/c-mmix.texi (MMIX-Chars): Likewise. * doc/c-s390.texi (s390 characters): Likewise. * doc/c-sh.texi (SH-Chars): Likewise. * doc/c-sh64.texi (SH64-Chars): Likewise. * doc/c-sparc.texi (SPARC-Chars): Likewise. * doc/c-tic6x.texi (TIC6X Syntax): Likewise. * doc/c-xtensa.texi (Xtensa Syntax): Likewise. * doc/c-z80.texi (Z80-Chars): Likewise. * doc/c-z8k.texi (Z8000-Chars): Likewise. * doc/c-pdp11.texi (PDP11-Syntax): Document line separator character. * doc/c-arc.texi (ARC-Chars): Fill in this subsection. * doc/c-bfin.texi (Blackfin Syntax): Document line comment and line separator characters. * doc/c-cr16.texi (CR16 Syntax): Likewise. * doc/c-i386.texi (i386-Chars): Likewise. * doc/c-i860.texi (i860-Chars): Likewise. * doc/c-i960.texi (i960-Chars): Likewise. * doc/c-ip2k.texi (IP2K-Chars): Likewise. * doc/c-lm32.texi (LM32-Chars): likewise. * doc/c-m32c.texi (M32C-Chars): Likewise. * doc/c-m68hc11.texi (M68HC11-syntax): Likewise. * doc/c-m68k.texi (M68K-Chars): Likewise. * doc/c-microblaze.texi (MicroBlaze-Chars): Likewise. * doc/c-msp430.texi (MSP430-Chars): Likewise. * doc/c-mt.texi (MT-Chars): Likewise. * doc/c-ns32k.texi (NS32K-Chars): Likewise. * doc/c-pj.texi (PJ-Chars): Likewise. * doc/c-ppc.texi (PowerPC-Chars): Likewise. * doc/c-rx.texi (RX-Chars): Likewise. * doc/c-score.texi (SCORE-Chars): Likewise. * doc/c-tic54x.texi (TIC54X-Chars): Likewise. * doc/c-v850.texi (V850-Chars): Likewise. * doc/c-vax.texi (VAX-Chars): Likewise. * doc/c-xc16x.texi (xc16x-Chars): Likewise.
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If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
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@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.
@node SH-Regs
@subsection Register Names
@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.
The SH also has these control registers:
@table @code
@item pr
procedure register (holds return address)
@item pc
program counter
@item mach
@itemx macl
high and low multiply accumulator registers
@item sr
status register
@item gbr
global base register
@item vbr
vector base register (for interrupt vectors)
@end table
@node SH-Addressing
@subsection Addressing Modes
@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.
@table @code
@item R@var{n}
Register direct
@item @@R@var{n}
Register indirect
@item @@-R@var{n}
Register indirect with pre-decrement
@item @@R@var{n}+
Register indirect with post-increment
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
@item @@(R0, R@var{n})
Register indexed
@item @@(@var{disp}, GBR)
@code{GBR} offset
@item @@(R0, GBR)
GBR indexed
@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory). The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.
@item #@var{imm}
Immediate data
@end table
@node SH Floating Point
@section Floating Point
@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
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SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
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SH groups can use @code{.float} directive to generate @sc{ieee}
floating-point numbers.
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SH2E and SH3E support single-precision floating point calculations as
well as entirely PCAPI compatible emulation of double-precision
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floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.
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In addition to single-precision and double-precision floating-point
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
engine that enables 32-bit floating-point data to be processed 128
bits at a time. It also supports 4 * 4 array operations and inner
product operations. Also, a superscalar architecture is employed that
enables simultaneous execution of two instructions (including FPU
instructions), providing performance of up to twice that of
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conventional architectures at the same frequency.
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@node SH Directives
@section SH Machine Directives
@cindex SH machine directives
@cindex machine directives, SH
@cindex @code{uaword} directive, SH
@cindex @code{ualong} directive, SH
@cindex @code{uaquad} directive, SH
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@table @code
@item uaword
@itemx ualong
@itemx uaquad
@code{@value{AS}} will issue a warning when a misaligned @code{.word},
@code{.long}, or @code{.quad} directive is used. You may use
@code{.uaword}, @code{.ualong}, or @code{.uaquad} to indicate that the
value is intentionally misaligned.
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@end table
@node SH Opcodes
@section Opcodes
@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Renesas) or
@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
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@code{@value{AS}} implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)
@example
mov.l bar,r0
@end example
@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:
@example
mov.l @@(@var{disp}, PC)
@end example
@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook. See comments below "@set SMALL" near top of this file.
Here is a summary of SH opcodes:
@page
@smallexample
@i{Legend:}
Rn @r{a numbered register}
Rm @r{another numbered register}
#imm @r{immediate data}
disp @r{displacement}
disp8 @r{8-bit displacement}
disp12 @r{12-bit displacement}
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add #imm,Rn lds.l @@Rn+,PR
add Rm,Rn mac.w @@Rm+,@@Rn+
addc Rm,Rn mov #imm,Rn
addv Rm,Rn mov Rm,Rn
and #imm,R0 mov.b Rm,@@(R0,Rn)
and Rm,Rn mov.b Rm,@@-Rn
and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
bf disp8 mov.b @@(disp,Rm),R0
bra disp12 mov.b @@(disp,GBR),R0
bsr disp12 mov.b @@(R0,Rm),Rn
bt disp8 mov.b @@Rm+,Rn
clrmac mov.b @@Rm,Rn
clrt mov.b R0,@@(disp,Rm)
cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
cmp/gt Rm,Rn mov.l Rm,@@-Rn
cmp/hi Rm,Rn mov.l Rm,@@Rn
cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
cmp/pl Rn mov.l @@(disp,GBR),R0
cmp/pz Rn mov.l @@(disp,PC),Rn
cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
div0s Rm,Rn mov.l @@Rm+,Rn
div0u mov.l @@Rm,Rn
div1 Rm,Rn mov.l R0,@@(disp,GBR)
exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
exts.w Rm,Rn mov.w Rm,@@-Rn
extu.b Rm,Rn mov.w Rm,@@Rn
extu.w Rm,Rn mov.w @@(disp,Rm),R0
jmp @@Rn mov.w @@(disp,GBR),R0
jsr @@Rn mov.w @@(disp,PC),Rn
ldc Rn,GBR mov.w @@(R0,Rm),Rn
ldc Rn,SR mov.w @@Rm+,Rn
ldc Rn,VBR mov.w @@Rm,Rn
ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
ldc.l @@Rn+,VBR mova @@(disp,PC),R0
lds Rn,MACH movt Rn
lds Rn,MACL muls Rm,Rn
lds Rn,PR mulu Rm,Rn
lds.l @@Rn+,MACH neg Rm,Rn
lds.l @@Rn+,MACL negc Rm,Rn
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@page
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nop stc VBR,Rn
not Rm,Rn stc.l GBR,@@-Rn
or #imm,R0 stc.l SR,@@-Rn
or Rm,Rn stc.l VBR,@@-Rn
or.b #imm,@@(R0,GBR) sts MACH,Rn
rotcl Rn sts MACL,Rn
rotcr Rn sts PR,Rn
rotl Rn sts.l MACH,@@-Rn
rotr Rn sts.l MACL,@@-Rn
rte sts.l PR,@@-Rn
rts sub Rm,Rn
sett subc Rm,Rn
shal Rn subv Rm,Rn
shar Rn swap.b Rm,Rn
shll Rn swap.w Rm,Rn
shll16 Rn tas.b @@Rn
shll2 Rn trapa #imm
shll8 Rn tst #imm,R0
shlr Rn tst Rm,Rn
shlr16 Rn tst.b #imm,@@(R0,GBR)
shlr2 Rn xor #imm,R0
shlr8 Rn xor Rm,Rn
sleep xor.b #imm,@@(R0,GBR)
stc GBR,Rn xtrct Rm,Rn
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stc SR,Rn
@end smallexample
@end ifset
@ifset Renesas-all
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@ifclear GENERIC
@raisesections
@end ifclear
@end ifset