2020-03-04 15:58:13 +08:00
|
|
|
|
2020-03-04 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
|
|
|
|
|
|
(prefix_table): Move vmmcall here. Add vmgexit.
|
|
|
|
|
|
(rm_table): Replace vmmcall entry by prefix_table[] escape.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
|
|
|
|
|
|
(cpu_flags): Add CpuSEV_ES entry.
|
|
|
|
|
|
* i386-opc.h (CpuSEV_ES): New.
|
|
|
|
|
|
(union i386_cpu_flags): Add cpusev_es field.
|
|
|
|
|
|
* i386-opc.tbl (vmgexit): New.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-04 03:24:16 +08:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
|
|
|
|
|
|
with MnemonicSize.
|
|
|
|
|
|
* i386-opc.h (IGNORESIZE): New.
|
|
|
|
|
|
(DEFAULTSIZE): Likewise.
|
|
|
|
|
|
(IgnoreSize): Removed.
|
|
|
|
|
|
(DefaultSize): Likewise.
|
|
|
|
|
|
(MnemonicSize): New.
|
|
|
|
|
|
(i386_opcode_modifier): Replace ignoresize/defaultsize with
|
|
|
|
|
|
mnemonicsize.
|
|
|
|
|
|
* i386-opc.tbl (IgnoreSize): New.
|
|
|
|
|
|
(DefaultSize): Likewise.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-03-04 00:31:42 +08:00
|
|
|
|
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25627
|
|
|
|
|
|
* z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
x86: Allow integer conversion without suffix in AT&T syntax
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
2020-03-03 23:39:18 +08:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25622
|
|
|
|
|
|
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
|
|
|
|
|
|
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-02-25 13:04:46 +08:00
|
|
|
|
2020-02-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c: Indent labels correctly.
|
|
|
|
|
|
* aarch64-dis.c: Likewise.
|
|
|
|
|
|
* aarch64-gen.c: Likewise.
|
|
|
|
|
|
* aarch64-opc.c: Likewise.
|
|
|
|
|
|
* alpha-dis.c: Likewise.
|
|
|
|
|
|
* i386-dis.c: Likewise.
|
|
|
|
|
|
* nds32-asm.c: Likewise.
|
|
|
|
|
|
* nfp-dis.c: Likewise.
|
|
|
|
|
|
* visium-dis.c: Likewise.
|
|
|
|
|
|
|
2020-02-25 16:27:07 +08:00
|
|
|
|
2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h (int_vector_base): Make it available for all ARC
|
|
|
|
|
|
CPUs.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 18:18:49 +08:00
|
|
|
|
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
|
|
|
|
|
|
changed.
|
|
|
|
|
|
|
2020-02-20 06:51:07 +08:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
|
|
|
|
|
|
c.mv/c.li if rs1 is zero.
|
|
|
|
|
|
|
2020-02-17 23:12:10 +08:00
|
|
|
|
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Replace CpuABM with
|
|
|
|
|
|
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
|
|
|
|
|
|
CPU_POPCNT_FLAGS.
|
|
|
|
|
|
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
|
|
|
|
|
|
* i386-opc.h (CpuABM): Removed.
|
|
|
|
|
|
(CpuPOPCNT): New.
|
|
|
|
|
|
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
|
|
|
|
|
|
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
|
|
|
|
|
|
popcnt. Remove CpuABM from lzcnt.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
x86: fold certain VCVT{,U}SI2S{S,D} templates
There don't really need to be separate Cpu64 and CpuNo64 templates for
these. One small issue with this is that slightly strange code
.intel_syntax noprefix
.code16
.arch i286
.arch .avx
vcvtsi2sd xmm0, xmm0, dword ptr [bx]
vcvtsi2sd xmm0, xmm0, qword ptr [bx]
vcvtsi2sd xmm0, xmm0, ebx
vcvtsi2sd xmm0, xmm0, rbx
now will match in behavior with the AVX512 counterparts in that not
only the 2nd vcvtsi2sd won't assemble, but also the first. The last
two, otoh, will continue to assemble fine (due to the lack of any
memory operand size specifier). As a result, another way to make
things behave more consistently would be to avoid the folding and
add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so
would be to add Cpu386 to any such insn template.
While doing this also make the usual cosmetic adjustments for the
insns touched anyway. Additionally drop the redundant Cpu64 from
the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of
64-bit mode due to there not being anything to match the Reg64
operand.
2020-02-17 15:59:52 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
|
|
|
|
|
|
Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
|
|
|
|
|
|
VexW1 instead of open-coding them.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 15:59:07 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (AddrPrefixOpReg): Define.
|
|
|
|
|
|
(monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
|
|
|
|
|
|
umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
|
|
|
|
|
|
templates. Drop NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 15:56:18 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/6518
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
|
|
|
|
|
|
vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
|
|
|
|
|
|
into Intel syntax instance (with Unpsecified) and AT&T one
|
|
|
|
|
|
(without).
|
|
|
|
|
|
(vcvtneps2bf16): Likewise, along with folding the two so far
|
|
|
|
|
|
separate ones.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 12:10:20 +08:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
|
|
|
|
|
|
CPU_ANY_SSE4A_FLAGS.
|
|
|
|
|
|
|
2020-02-17 09:07:38 +08:00
|
|
|
|
2020-02-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Correct last change.
|
|
|
|
|
|
|
2020-02-17 00:36:51 +08:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
|
|
|
|
|
|
CPU_ANY_SSE4_FLAGS.
|
|
|
|
|
|
|
2020-02-14 21:40:19 +08:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movsx): Remove Intel syntax comments.
|
|
|
|
|
|
(movzx): Likewise.
|
|
|
|
|
|
|
2020-02-14 21:27:28 +08:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
|
|
|
|
|
|
destination for Cpu64-only variant.
|
|
|
|
|
|
(movzx): Fold patterns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-13 17:19:28 +08:00
|
|
|
|
2020-02-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
|
|
|
|
|
|
CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
|
|
|
|
|
|
CPU_ANY_SSE4_FLAGS entry.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:20:56 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
|
|
|
|
|
|
with Unspecified, making the present one AT&T syntax only.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:19:52 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:19:03 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24546
|
|
|
|
|
|
* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
|
|
|
|
|
|
* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
|
|
|
|
|
|
Amd64 and Intel64 templates.
|
|
|
|
|
|
(call, jmp): Likewise for far indirect variants. Dro
|
|
|
|
|
|
Unspecified.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-11 18:20:55 +08:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
|
|
|
|
|
|
* i386-opc.h (ShortForm): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Remove shortform field.
|
|
|
|
|
|
* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
|
|
|
|
|
|
fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
|
|
|
|
|
|
fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
|
|
|
|
|
|
ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
|
|
|
|
|
|
Drop ShortForm.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-11 18:20:05 +08:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
|
|
|
|
|
|
fucompi): Drop ShortForm from operand-less templates.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
Ensure *valuep always written by extract_normal return
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2020-02-11 06:41:18 +08:00
|
|
|
|
2020-02-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
|
|
|
|
|
|
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
|
|
|
|
|
|
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
|
|
|
|
|
|
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
|
|
|
|
|
|
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-02-11 00:39:02 +08:00
|
|
|
|
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_cde): Define 'V' parse character.
|
|
|
|
|
|
(cde_opcodes): Add VCX* instructions.
|
|
|
|
|
|
|
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
2020-02-11 00:38:00 +08:00
|
|
|
|
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
|
|
|
|
|
|
Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (struct cdeopcode32): New.
|
|
|
|
|
|
(CDE_OPCODE): New macro.
|
|
|
|
|
|
(cde_opcodes): New disassembly table.
|
|
|
|
|
|
(regnames): New option to table.
|
|
|
|
|
|
(cde_coprocs): New global variable.
|
|
|
|
|
|
(print_insn_cde): New
|
|
|
|
|
|
(print_insn_thumb32): Use print_insn_cde.
|
|
|
|
|
|
(parse_arm_disassembler_options): Parse coprocN args.
|
|
|
|
|
|
|
2020-02-11 00:37:22 +08:00
|
|
|
|
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25516
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
|
|
|
|
|
|
with ISA64.
|
|
|
|
|
|
* i386-opc.h (AMD64): Removed.
|
|
|
|
|
|
(Intel64): Likewose.
|
|
|
|
|
|
(AMD64): New.
|
|
|
|
|
|
(INTEL64): Likewise.
|
|
|
|
|
|
(INTEL64ONLY): Likewise.
|
|
|
|
|
|
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
|
|
|
|
|
|
* i386-opc.tbl (Amd64): New.
|
|
|
|
|
|
(Intel64): Likewise.
|
|
|
|
|
|
(Intel64Only): Likewise.
|
|
|
|
|
|
Replace AMD64 with Amd64. Update sysenter/sysenter with
|
|
|
|
|
|
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-02-07 22:53:46 +08:00
|
|
|
|
2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25469
|
|
|
|
|
|
* z80-dis.c: Add support for GBZ80 opcodes.
|
|
|
|
|
|
|
2020-02-04 06:00:22 +08:00
|
|
|
|
2020-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
|
|
|
|
|
|
|
2020-02-03 08:56:30 +08:00
|
|
|
|
2020-02-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-02-01 10:38:43 +08:00
|
|
|
|
2020-02-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-31 21:29:18 +08:00
|
|
|
|
2020-01-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
|
|
|
|
|
|
(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
|
|
|
|
|
|
(OP_E_memory): Replace xmm_mdq_mode case label by
|
|
|
|
|
|
vex_scalar_w_dq_mode one.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
|
|
|
|
|
|
|
2020-01-31 21:28:43 +08:00
|
|
|
|
2020-01-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
|
|
|
|
|
|
(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
|
|
|
|
|
|
vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
|
|
|
|
|
|
(intel_operand_size): Drop vex_w_dq_mode case label.
|
|
|
|
|
|
|
2020-01-31 16:03:56 +08:00
|
|
|
|
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
|
|
|
|
|
|
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
|
|
|
|
|
|
|
2020-01-30 19:29:20 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 20:59:04 +08:00
|
|
|
|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bpf-opc.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 18:36:33 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
|
|
|
|
|
|
(dis386): Use them to replace C2/C3 table entries.
|
|
|
|
|
|
(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
|
|
|
|
|
|
* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
|
|
|
|
|
|
ones. Use Size64 instead of DefaultSize on Intel64 ones.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 18:33:53 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
|
|
|
|
|
|
forms.
|
|
|
|
|
|
(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
|
|
|
|
|
|
DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 14:36:54 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_dp): Make unsigned.
|
|
|
|
|
|
|
2020-01-27 20:38:10 +08:00
|
|
|
|
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/25445
|
|
|
|
|
|
* i386-dis.c (MOVSXD_Fixup): New function.
|
|
|
|
|
|
(movsxd_mode): New enum.
|
|
|
|
|
|
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
|
|
|
|
|
|
(intel_operand_size): Handle movsxd_mode.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
|
|
|
|
|
|
register on movsxd. Add movsxd with 16-bit destination register
|
|
|
|
|
|
for AMD64 and Intel64 ISAs.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-27 18:40:02 +08:00
|
|
|
|
2020-01-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25403
|
|
|
|
|
|
* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 15:28:25 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (sysret): Drop DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-21 15:25:31 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
|
|
|
|
|
|
Dword.
|
|
|
|
|
|
(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-20 23:10:23 +08:00
|
|
|
|
2020-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2020-01-20 10:02:37 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (fput_const): Remove useless cast.
|
|
|
|
|
|
|
2020-01-20 10:01:58 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Wrap 'T' value.
|
|
|
|
|
|
|
2020-01-18 22:12:07 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2020-01-18 21:50:25 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Binutils 2.34 branch created.
|
|
|
|
|
|
|
2020-01-18 02:34:03 +08:00
|
|
|
|
2020-01-17 Christian Biesinger <cbiesinger@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opintl.h: Fix spelling error (seperate).
|
|
|
|
|
|
|
2020-01-17 23:07:55 +08:00
|
|
|
|
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add {vex} pseudo prefix.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-16 21:50:52 +08:00
|
|
|
|
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25376
|
|
|
|
|
|
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
(select_arm_features): Make sure we enable MVE bits when selecting
|
|
|
|
|
|
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
|
|
|
|
|
|
any architecture.
|
|
|
|
|
|
|
2020-01-16 17:07:05 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop stale comment from XOP section.
|
|
|
|
|
|
|
2020-01-16 17:06:21 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
|
|
|
|
|
|
(extractps): Add VexWIG to SSE2AVX forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-16 17:05:35 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
|
|
|
|
|
|
Size64 from and use VexW1 on SSE2AVX forms.
|
|
|
|
|
|
(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
|
|
|
|
|
|
VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-15 13:37:16 +08:00
|
|
|
|
2020-01-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_version): Make unsigned long.
|
|
|
|
|
|
(optab, optab_special, registernames): New file scope vars.
|
|
|
|
|
|
(tic4x_print_register): Set up registernames rather than
|
|
|
|
|
|
malloc'd registertable.
|
|
|
|
|
|
(tic4x_disassemble): Delete optable and optable_special. Use
|
|
|
|
|
|
optab and optab_special instead. Throw away old optab,
|
|
|
|
|
|
optab_special and registernames when info->mach changes.
|
|
|
|
|
|
|
2020-01-14 21:13:57 +08:00
|
|
|
|
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25377
|
|
|
|
|
|
* z80-dis.c (suffix): Use .db instruction to generate double
|
|
|
|
|
|
prefix.
|
|
|
|
|
|
|
2020-01-14 06:47:09 +08:00
|
|
|
|
2020-01-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
|
|
|
|
|
|
values to unsigned before shifting.
|
|
|
|
|
|
|
Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
(detected_jumps): New variables.
(usage): Add the new jump visualization options.
(option_values): Add new option value.
(long_options): Add the new option.
(jump_info_new, jump_info_free): New functions.
(jump_info_min_address, jump_info_max_address): Likewise.
(jump_info_end_address, jump_info_is_start_address): Likewise.
(jump_info_is_end_address, jump_info_size): Likewise.
(jump_info_unlink, jump_info_insert): Likewise.
(jump_info_add_front, jump_info_move_linked): Likewise.
(jump_info_intersect, jump_info_merge): Likewise.
(jump_info_sort, jump_info_visualize_address): Likewise.
(disassemble_jumps): New function - used to locate jumps.
(disassemble_bytes): Add ascii art generation.
(disassemble_section): Add scan to locate jumps.
(main): Parse the new visualization option.
* doc/binutils.texi: Document the new feature.
* NEWS: Mention the new feature.
opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control
flow instructions.
(print_insn_thumb16, print_insn_thumb32): Likewise.
(print_insn): Initialize the insn info.
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
2020-01-13 20:36:55 +08:00
|
|
|
|
2020-01-13 Thomas Troeger <tstroege@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Fill in insn info fields for control
|
|
|
|
|
|
flow instructions.
|
|
|
|
|
|
(print_insn_thumb16, print_insn_thumb32): Likewise.
|
|
|
|
|
|
(print_insn): Initialize the insn info.
|
|
|
|
|
|
* i386-dis.c (print_insn): Initialize the insn info fields, and
|
|
|
|
|
|
detect jumps.
|
|
|
|
|
|
|
2020-01-13 17:16:47 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (C_NE): Make it required.
|
|
|
|
|
|
|
2020-01-13 16:21:30 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
|
|
|
|
|
|
reserved register name.
|
|
|
|
|
|
|
2020-01-13 15:28:02 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
|
|
|
|
|
|
(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
|
|
|
|
|
|
|
2020-01-13 11:57:19 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
|
|
|
|
|
|
result of wasm_read_leb128 in a uint64_t and check that bits
|
|
|
|
|
|
are not lost when copying to other locals. Use uint32_t for
|
|
|
|
|
|
most locals. Use PRId64 when printing int64_t.
|
|
|
|
|
|
|
2020-01-13 08:48:36 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c: Formatting.
|
|
|
|
|
|
* score7-dis.c: Formatting.
|
|
|
|
|
|
|
2020-01-13 08:16:55 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c (print_insn_score48): Use unsigned variables for
|
|
|
|
|
|
unsigned values. Don't left shift negative values.
|
|
|
|
|
|
(print_insn_score32): Likewise.
|
|
|
|
|
|
* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
|
|
|
|
|
|
|
2020-01-12 17:46:22 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_print_register): Remove dead code.
|
|
|
|
|
|
|
2020-01-11 10:02:11 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-11 09:53:47 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* xgate-dis.c (print_insn): Don't left shift signed value.
|
|
|
|
|
|
(ripBits): Formatting, use 1u.
|
|
|
|
|
|
|
2020-01-10 05:57:33 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
|
|
|
|
|
|
* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
|
|
|
|
|
|
|
2020-01-09 04:29:42 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
|
|
|
|
|
|
and XRREG value earlier to avoid a shift with negative exponent.
|
|
|
|
|
|
* m10200-dis.c (disassemble): Similarly.
|
|
|
|
|
|
|
2020-01-09 22:32:49 +08:00
|
|
|
|
2020-01-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25224
|
|
|
|
|
|
* z80-dis.c (ld_ii_ii): Use correct cast.
|
|
|
|
|
|
|
2020-01-09 19:47:44 +08:00
|
|
|
|
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25224
|
|
|
|
|
|
* z80-dis.c (ld_ii_ii): Use character constant when checking
|
|
|
|
|
|
opcode byte value.
|
|
|
|
|
|
|
2020-01-09 18:38:01 +08:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (SEP_Fixup): New.
|
|
|
|
|
|
(SEP): Define.
|
|
|
|
|
|
(dis386_twobyte): Use it for sysenter/sysexit.
|
|
|
|
|
|
(enum x86_64_isa): Change amd64 enumerator to value 1.
|
|
|
|
|
|
(OP_J): Compare isa64 against intel64 instead of amd64.
|
|
|
|
|
|
* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
|
|
|
|
|
|
forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-08 09:12:36 +08:00
|
|
|
|
2020-01-08 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z8k-dis.c: Include libiberty.h
|
|
|
|
|
|
(instr_data_s): Make max_fetched unsigned.
|
|
|
|
|
|
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
|
|
|
|
|
|
Don't exceed byte_info bounds.
|
|
|
|
|
|
(output_instr): Make num_bytes unsigned.
|
|
|
|
|
|
(unpack_instr): Likewise for nibl_count and loop.
|
|
|
|
|
|
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
|
|
|
|
|
|
idx unsigned.
|
|
|
|
|
|
* z8k-opc.h: Regenerate.
|
|
|
|
|
|
|
2020-01-07 21:25:15 +08:00
|
|
|
|
2020-01-07 Shahab Vahedi <shahab@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h (llock): Use 'LLOCK' as class.
|
|
|
|
|
|
(llockd): Likewise.
|
|
|
|
|
|
(scond): Use 'SCOND' as class.
|
|
|
|
|
|
(scondd): Likewise.
|
|
|
|
|
|
(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
|
|
|
|
|
|
(scondd): Likewise.
|
|
|
|
|
|
|
2020-01-04 17:23:19 +08:00
|
|
|
|
2020-01-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-06 06:22:39 +08:00
|
|
|
|
2020-01-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25344
|
|
|
|
|
|
* z80-dis.c (suffix): Don't use a local struct buffer copy.
|
|
|
|
|
|
Peek at next byte to prevent recursion on repeated prefix bytes.
|
|
|
|
|
|
Ensure uninitialised "mybuf" is not accessed.
|
|
|
|
|
|
(print_insn_z80): Don't zero n_fetch and n_used here,..
|
|
|
|
|
|
(print_insn_z80_buf): ..do it here instead.
|
|
|
|
|
|
|
2020-01-04 05:41:43 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-03 05:42:00 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
|
|
|
|
|
|
|
2020-01-03 04:37:17 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-dis.c (match_opcode): Avoid shift left of signed value.
|
|
|
|
|
|
|
2020-01-01 16:16:43 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
|
|
|
|
|
|
|
2020-01-03 17:14:16 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Use
|
|
|
|
|
|
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
|
|
|
|
|
|
|
|
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
|
2020-01-03 17:14:16 +08:00
|
|
|
|
forms of SUDOT and USDOT.
|
|
|
|
|
|
|
2020-01-03 17:13:31 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
|
2020-01-03 17:13:31 +08:00
|
|
|
|
uzip{1,2}.
|
|
|
|
|
|
* opcodes/aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
|
2020-01-03 17:12:49 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
|
2020-01-03 17:12:49 +08:00
|
|
|
|
FMMLA encoding.
|
|
|
|
|
|
* opcodes/aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
|
2020-01-02 22:10:40 +08:00
|
|
|
|
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z80-dis.c: Add support for eZ80 and Z80 instructions.
|
|
|
|
|
|
|
2020-01-01 16:22:19 +08:00
|
|
|
|
2020-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
For older changes see ChangeLog-2019
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
Copyright (C) 2020 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
