2011-03-16 05:01:45 +08:00
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/* Blackfin General Purpose Ports (GPIO) model
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2016-01-01 12:33:14 +08:00
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Copyright (C) 2010-2016 Free Software Foundation, Inc.
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2011-03-16 05:01:45 +08:00
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_gpio.h"
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struct bfin_gpio
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{
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bu32 base;
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2011-04-26 13:46:02 +08:00
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bu16 int_state;
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2011-03-16 05:01:45 +08:00
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(data);
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bu16 BFIN_MMR_16(clear);
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bu16 BFIN_MMR_16(set);
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bu16 BFIN_MMR_16(toggle);
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bu16 BFIN_MMR_16(maska);
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bu16 BFIN_MMR_16(maska_clear);
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bu16 BFIN_MMR_16(maska_set);
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bu16 BFIN_MMR_16(maska_toggle);
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bu16 BFIN_MMR_16(maskb);
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bu16 BFIN_MMR_16(maskb_clear);
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bu16 BFIN_MMR_16(maskb_set);
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bu16 BFIN_MMR_16(maskb_toggle);
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bu16 BFIN_MMR_16(dir);
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bu16 BFIN_MMR_16(polar);
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bu16 BFIN_MMR_16(edge);
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bu16 BFIN_MMR_16(both);
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bu16 BFIN_MMR_16(inen);
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};
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#define mmr_base() offsetof(struct bfin_gpio, data)
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#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
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"PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
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"PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
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"PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
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"PORTIO_BOTH", "PORTIO_INEN",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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2011-04-26 13:46:02 +08:00
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static void
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bfin_gpio_forward_int (struct hw *me, struct bfin_gpio *port, bu32 mask,
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int dst_port)
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{
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HW_TRACE ((me, "resending levels on port %c", 'a' + dst_port));
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hw_port_event (me, dst_port, !!(port->int_state & mask));
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}
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static void
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bfin_gpio_forward_ints (struct hw *me, struct bfin_gpio *port)
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{
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bfin_gpio_forward_int (me, port, port->maska, 0);
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bfin_gpio_forward_int (me, port, port->maskb, 1);
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}
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2011-04-26 13:47:14 +08:00
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static void
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bfin_gpio_forward_ouput (struct hw *me, struct bfin_gpio *port, bu32 odata)
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{
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int pin, value, ovalue, bit;
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for (pin = 0; pin < 16; ++pin)
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{
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bit = 1 << pin;
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/* Make sure this is an output pin. */
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if (!(port->dir & bit))
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continue;
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/* Only signal port if the pin changes value. */
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value = !!(port->data & bit);
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ovalue = !!(odata & bit);
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if (value == ovalue)
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continue;
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HW_TRACE ((me, "outputting gpio %i changed to %i", pin, value));
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hw_port_event (me, pin, value);
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}
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}
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2011-03-16 05:01:45 +08:00
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static unsigned
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bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu16 value;
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bu16 *valuep;
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2011-04-26 13:47:14 +08:00
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bu32 data = port->data;
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2011-03-16 05:01:45 +08:00
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2015-12-27 08:02:07 +08:00
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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2011-03-16 05:01:45 +08:00
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value = dv_load_2 (source);
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mmr_off = addr - port->base;
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(maska):
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case mmr_offset(maskb):
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case mmr_offset(dir):
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case mmr_offset(polar):
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case mmr_offset(edge):
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case mmr_offset(both):
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case mmr_offset(inen):
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*valuep = value;
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break;
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case mmr_offset(clear):
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case mmr_offset(maska_clear):
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case mmr_offset(maskb_clear):
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2011-03-25 08:12:47 +08:00
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/* We want to clear the related data MMR. */
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valuep -= 2;
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2011-03-24 11:17:14 +08:00
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dv_w1c_2 (valuep, value, -1);
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2011-03-16 05:01:45 +08:00
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break;
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case mmr_offset(set):
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case mmr_offset(maska_set):
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case mmr_offset(maskb_set):
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2011-03-25 08:12:47 +08:00
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/* We want to set the related data MMR. */
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valuep -= 4;
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2011-03-16 05:01:45 +08:00
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*valuep |= value;
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break;
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case mmr_offset(toggle):
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case mmr_offset(maska_toggle):
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case mmr_offset(maskb_toggle):
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2011-03-25 08:12:47 +08:00
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/* We want to toggle the related data MMR. */
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valuep -= 6;
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2011-03-16 05:01:45 +08:00
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*valuep ^= value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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2015-12-27 08:02:07 +08:00
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return 0;
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2011-03-16 05:01:45 +08:00
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}
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2011-04-26 13:46:02 +08:00
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/* If updating masks, make sure we send updated port info. */
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switch (mmr_off)
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{
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2011-04-26 13:47:14 +08:00
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case mmr_offset(dir):
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case mmr_offset(data) ... mmr_offset(toggle):
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bfin_gpio_forward_ouput (me, port, data);
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break;
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2011-04-26 13:46:02 +08:00
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case mmr_offset(maska) ... mmr_offset(maska_toggle):
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bfin_gpio_forward_int (me, port, port->maska, 0);
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break;
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case mmr_offset(maskb) ... mmr_offset(maskb_toggle):
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bfin_gpio_forward_int (me, port, port->maskb, 1);
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break;
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}
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2011-03-16 05:01:45 +08:00
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return nr_bytes;
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}
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static unsigned
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bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu16 *valuep;
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2015-12-27 08:02:07 +08:00
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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2011-03-16 05:01:45 +08:00
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mmr_off = addr - port->base;
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(clear):
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case mmr_offset(set):
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case mmr_offset(toggle):
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dv_store_2 (dest, port->data);
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break;
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case mmr_offset(maska):
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case mmr_offset(maska_clear):
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case mmr_offset(maska_set):
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case mmr_offset(maska_toggle):
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dv_store_2 (dest, port->maska);
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break;
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case mmr_offset(maskb):
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case mmr_offset(maskb_clear):
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case mmr_offset(maskb_set):
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case mmr_offset(maskb_toggle):
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dv_store_2 (dest, port->maskb);
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break;
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case mmr_offset(dir):
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case mmr_offset(polar):
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case mmr_offset(edge):
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case mmr_offset(both):
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case mmr_offset(inen):
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dv_store_2 (dest, *valuep);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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2015-12-27 08:02:07 +08:00
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return 0;
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2011-03-16 05:01:45 +08:00
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}
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_gpio_ports[] =
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{
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{ "mask_a", 0, 0, output_port, },
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{ "mask_b", 1, 0, output_port, },
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2011-04-26 13:47:14 +08:00
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{ "p0", 0, 0, bidirect_port, },
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{ "p1", 1, 0, bidirect_port, },
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{ "p2", 2, 0, bidirect_port, },
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{ "p3", 3, 0, bidirect_port, },
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{ "p4", 4, 0, bidirect_port, },
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{ "p5", 5, 0, bidirect_port, },
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{ "p6", 6, 0, bidirect_port, },
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{ "p7", 7, 0, bidirect_port, },
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{ "p8", 8, 0, bidirect_port, },
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{ "p9", 9, 0, bidirect_port, },
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{ "p10", 10, 0, bidirect_port, },
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{ "p11", 11, 0, bidirect_port, },
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{ "p12", 12, 0, bidirect_port, },
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{ "p13", 13, 0, bidirect_port, },
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{ "p14", 14, 0, bidirect_port, },
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{ "p15", 15, 0, bidirect_port, },
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2011-03-16 05:01:45 +08:00
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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struct bfin_gpio *port = hw_data (me);
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bool olvl, nlvl;
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bu32 bit = (1 << my_port);
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2011-03-25 08:13:23 +08:00
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/* Normalize the level value. A simulated device can send any value
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it likes to us, but in reality we only care about 0 and 1. This
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lets us assume only those two values below. */
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level = !!level;
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2011-03-25 08:13:57 +08:00
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HW_TRACE ((me, "pin %i set to %i", my_port, level));
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2011-03-25 08:13:23 +08:00
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/* Only screw with state if this pin is set as an input, and the
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input is actually enabled. */
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if ((port->dir & bit) || !(port->inen & bit))
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2011-03-25 08:13:57 +08:00
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{
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HW_TRACE ((me, "ignoring level/int due to DIR=%i INEN=%i",
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!!(port->dir & bit), !!(port->inen & bit)));
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return;
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}
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2011-03-16 05:01:45 +08:00
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/* Get the old pin state for calculating an interrupt. */
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olvl = !!(port->data & bit);
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/* Update the new pin state. */
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2011-03-25 08:13:23 +08:00
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port->data = (port->data & ~bit) | (level << my_port);
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2011-03-16 05:01:45 +08:00
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/* See if this state transition will generate an interrupt. */
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nlvl = !!(port->data & bit);
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if (port->edge & bit)
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{
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/* Pin is edge triggered. */
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2011-03-25 08:13:23 +08:00
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if (port->both & bit)
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2011-03-16 05:01:45 +08:00
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{
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/* Both edges. */
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if (olvl == nlvl)
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2011-03-25 08:13:57 +08:00
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{
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HW_TRACE ((me, "ignoring int due to EDGE=%i BOTH=%i lvl=%i->%i",
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!!(port->edge & bit), !!(port->both & bit),
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olvl, nlvl));
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return;
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}
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2011-03-16 05:01:45 +08:00
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}
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else
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{
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/* Just one edge. */
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if (!(((port->polar & bit) && olvl > nlvl)
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|| (!(port->polar & bit) && olvl < nlvl)))
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2011-03-25 08:13:57 +08:00
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{
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HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i->%i",
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!!(port->edge & bit), !!(port->polar & bit),
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olvl, nlvl));
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return;
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}
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2011-03-16 05:01:45 +08:00
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}
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2011-04-26 13:46:02 +08:00
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/* Send the signal up, and then fall through to clear it. */
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port->int_state |= bit;
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bfin_gpio_forward_ints (me, port);
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port->int_state &= ~bit;
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2011-03-16 05:01:45 +08:00
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}
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else
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{
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/* Pin is level triggered. */
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if (nlvl == !!(port->polar & bit))
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2011-03-25 08:13:57 +08:00
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{
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HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i",
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!!(port->edge & bit), !!(port->polar & bit), nlvl));
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2011-04-26 13:46:02 +08:00
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/* We still need to signal SIC to clear the int, so don't return. */
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port->int_state &= ~bit;
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2011-03-25 08:13:57 +08:00
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}
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2011-04-26 13:46:02 +08:00
|
|
|
else
|
|
|
|
port->int_state |= bit;
|
2011-03-16 05:01:45 +08:00
|
|
|
}
|
|
|
|
|
2011-04-26 13:46:02 +08:00
|
|
|
bfin_gpio_forward_ints (me, port);
|
2011-03-16 05:01:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port)
|
|
|
|
{
|
|
|
|
address_word attach_address;
|
|
|
|
int attach_space;
|
|
|
|
unsigned attach_size;
|
|
|
|
reg_property_spec reg;
|
|
|
|
|
|
|
|
if (hw_find_property (me, "reg") == NULL)
|
|
|
|
hw_abort (me, "Missing \"reg\" property");
|
|
|
|
|
|
|
|
if (!hw_find_reg_array_property (me, "reg", 0, ®))
|
|
|
|
hw_abort (me, "\"reg\" property must contain three addr/size entries");
|
|
|
|
|
|
|
|
hw_unit_address_to_attach_address (hw_parent (me),
|
|
|
|
®.address,
|
|
|
|
&attach_space, &attach_address, me);
|
|
|
|
hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
|
|
|
|
|
|
|
|
if (attach_size != BFIN_MMR_GPIO_SIZE)
|
|
|
|
hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE);
|
|
|
|
|
|
|
|
hw_attach_address (hw_parent (me),
|
|
|
|
0, attach_space, attach_address, attach_size, me);
|
|
|
|
|
|
|
|
port->base = attach_address;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bfin_gpio_finish (struct hw *me)
|
|
|
|
{
|
|
|
|
struct bfin_gpio *port;
|
|
|
|
|
|
|
|
port = HW_ZALLOC (me, struct bfin_gpio);
|
|
|
|
|
|
|
|
set_hw_data (me, port);
|
|
|
|
set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
|
|
|
|
set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
|
|
|
|
set_hw_ports (me, bfin_gpio_ports);
|
|
|
|
set_hw_port_event (me, bfin_gpio_port_event);
|
|
|
|
|
|
|
|
attach_bfin_gpio_regs (me, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct hw_descriptor dv_bfin_gpio_descriptor[] =
|
|
|
|
{
|
|
|
|
{"bfin_gpio", bfin_gpio_finish,},
|
|
|
|
{NULL, NULL},
|
|
|
|
};
|