2020-06-18 15:13:49 +08:00
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2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Revert the last vmgexit change.
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2020-06-16 22:11:31 +08:00
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2020-06-17 Lili Cui <lili.cui@intel.com>
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* i386-dis.c (prefix_table): Delete the incorrect vmgexit.
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2020-06-14 20:18:35 +08:00
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2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26115
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* i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
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* i386-opc.tbl: Likewise.
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* i386-tbl.h: Regenerated.
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RISC-V: Drop the privileged spec v1.9 support.
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is
0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable,
but may also cause risk of compatibility. Binutils already support the
-mpriv-spec options and ELF priv attributes, which can used to choose what
privileged spec you want, and then give a correponding CSR name and address
to use. But Gdb and other tools don't have the simialr mechanism for now.
However, there are two things can be confirmed,
1. If we don't have a way to control the priv specs, then the changes, like
MISA, will cause risk and hard to maintain.
2. We get the guarantee that the CSR address won't be reused in the future
specs, even if it is dropped.
I'm not sure if Gdb needs to care about the priv spec versions, it is still
discussing. But drop the priv spec v1.9, and make sure that we won't reuse
the CSR address is a useful solution for now. Also, we might drop the v1.9.1
in a year or two. After that, specs above v1.10 should be compatible anyway.
gas/
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
include/
* opcode/riscv-opc.h: Update the defined versions of CSR from
PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the
MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
* opcode/riscv.h (enum riscv_priv_spec_class): Remove
PRIV_SPEC_CLASS_1P9.
opcodes/
* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-10 14:07:54 +08:00
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2020-06-12 Nelson Chu <nelson.chu@sifive.com>
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* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
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2020-06-11 19:34:37 +08:00
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2020-06-11 Alex Coplan <alex.coplan@arm.com>
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* aarch64-opc.c (SYSREG): New macro for describing system registers.
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(SR_CORE): Likewise.
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(SR_FEAT): Likewise.
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(SR_RNG): Likewise.
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(SR_V8_1): Likewise.
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(SR_V8_2): Likewise.
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(SR_V8_3): Likewise.
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(SR_V8_4): Likewise.
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(SR_PAN): Likewise.
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(SR_RAS): Likewise.
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(SR_SSBS): Likewise.
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(SR_SVE): Likewise.
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(SR_ID_PFR2): Likewise.
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(SR_PROFILE): Likewise.
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(SR_MEMTAG): Likewise.
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(SR_SCXTNUM): Likewise.
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(aarch64_sys_regs): Refactor to store feature information in the table.
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(aarch64_sys_reg_supported_p): Collapse logic for system registers
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that now describe their own features.
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(aarch64_pstatefield_supported_p): Likewise.
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2020-06-09 21:29:33 +08:00
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2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Fix a typo in comments.
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2020-06-09 14:59:04 +08:00
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2020-06-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (rex_ignored): Delete.
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(ckprefix): Drop rex_ignored initialization.
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(get_valid_dis386): Drop setting of rex_ignored.
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(print_insn): Drop checking of rex_ignored. Don't record data
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size prefix as used with VEX-and-alike encodings.
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x86: fix {,V}MOV{L,H}PD disassembly
Neither the legacy nor the VEX-encoded forms are permitted with register
operands, just like is already the case for their store forms as well as
{,V}MOV{L,H}PS.
At the same time, besides folding respective vex_len_table[] entries,
adjust adjacent related legacy mod_table[] entries:
- when the prefix was already decoded, PREFIX_OPCODE is pointless,
- limit the amount of string literals by using X consistently on all
{,V}MOV{L,H}P{S,D} forms.
2020-06-09 14:57:55 +08:00
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2020-06-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
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MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
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(VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
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(VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
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(prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
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VEX_0F12, and VEX_0F16.
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(vex_len_table): Use X for vmovlp* and vmovh*s. Drop
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VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
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(mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
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from movlps and movhlps. New MOD_0F12_PREFIX_2,
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MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
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MOD_VEX_0F16_PREFIX_2 entries.
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2020-06-09 14:57:22 +08:00
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2020-06-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
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MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
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(PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
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PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
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PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
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PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
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EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
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EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
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EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
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EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
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EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
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EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
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EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
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EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
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EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
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EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
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EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
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EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
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EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
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EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
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EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
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EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
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EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
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EVEX_W_0FC6_P_2): Delete.
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(print_insn): Add EVEX.W vs embedded prefix consistency check
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to prefix validation.
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* i386-dis-evex.h (evex_table): Don't further descend for
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vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
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and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
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and 0F2B.
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* i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
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* i386-dis-evex-prefix.h: Don't further descend for vmovupX,
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vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
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vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
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2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
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Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
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PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
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PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
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PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
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* i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
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EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
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EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
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EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
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EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
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EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
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EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
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EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
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EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
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EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
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EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
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EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
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EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
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EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
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EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
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EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
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EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
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EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
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2020-06-09 14:56:39 +08:00
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2020-06-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
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vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
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(vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
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vmovmskpX.
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(print_insn): Drop pointless check against bad_opcode. Split
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prefix validation into legacy and VEX-and-alike parts.
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(putop): Re-work 'X' macro handling.
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2020-06-09 14:55:50 +08:00
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|
2020-06-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (MOD_0F51): Rename to ...
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(MOD_0F50): ... this.
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2020-06-08 22:16:29 +08:00
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|
2020-06-08 Alex Coplan <alex.coplan@arm.com>
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* arm-dis.c (arm_opcodes): Add dfb.
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(thumb32_opcodes): Add dfb.
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2020-06-08 14:37:47 +08:00
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|
2020-06-08 Jan Beulich <jbeulich@suse.com>
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* i386-opc.h (reg_entry): Const-qualify reg_name field.
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2020-06-06 12:52:37 +08:00
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|
2020-06-06 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
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2020-06-05 14:48:47 +08:00
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|
2020-06-05 Alan Modra <amodra@gmail.com>
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* cgen-dis.c (hash_insn_array): Increase size of buf. Assert
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size is large enough.
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2020-06-04 22:17:07 +08:00
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2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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* disassemble.c (disassemble_init_for_target): Set endian_code for
|
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bpf targets.
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* bpf-desc.c: Regenerate.
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* bpf-opc.c: Likewise.
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* bpf-dis.c: Likewise.
|
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|
|
opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
2020-06-04 22:15:53 +08:00
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2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
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* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
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(cgen_put_insn_value): Likewise.
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(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
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* cgen-dis.in (print_insn): Likewise.
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* cgen-ibld.in (insert_1): Likewise.
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(insert_1): Likewise.
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(insert_insn_normal): Likewise.
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(extract_1): Likewise.
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* bpf-dis.c: Regenerate.
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* bpf-ibld.c: Likewise.
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* bpf-ibld.c: Likewise.
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* cgen-dis.in: Likewise.
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* cgen-ibld.in: Likewise.
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* cgen-opc.c: Likewise.
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* epiphany-dis.c: Likewise.
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* epiphany-ibld.c: Likewise.
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* fr30-dis.c: Likewise.
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* fr30-ibld.c: Likewise.
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* frv-dis.c: Likewise.
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* frv-ibld.c: Likewise.
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* ip2k-dis.c: Likewise.
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* ip2k-ibld.c: Likewise.
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* iq2000-dis.c: Likewise.
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* iq2000-ibld.c: Likewise.
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* lm32-dis.c: Likewise.
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* lm32-ibld.c: Likewise.
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* m32c-dis.c: Likewise.
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* m32c-ibld.c: Likewise.
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* m32r-dis.c: Likewise.
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* m32r-ibld.c: Likewise.
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* mep-dis.c: Likewise.
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* mep-ibld.c: Likewise.
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* mt-dis.c: Likewise.
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* mt-ibld.c: Likewise.
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* or1k-dis.c: Likewise.
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* or1k-ibld.c: Likewise.
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* xc16x-dis.c: Likewise.
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* xc16x-ibld.c: Likewise.
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* xstormy16-dis.c: Likewise.
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* xstormy16-ibld.c: Likewise.
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2020-06-04 22:14:41 +08:00
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2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
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* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
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(print_insn_): Handle instruction endian.
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* bpf-dis.c: Regenerate.
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* bpf-desc.c: Regenerate.
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* epiphany-dis.c: Likewise.
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* epiphany-desc.c: Likewise.
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* fr30-dis.c: Likewise.
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* fr30-desc.c: Likewise.
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* frv-dis.c: Likewise.
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* frv-desc.c: Likewise.
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* ip2k-dis.c: Likewise.
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* ip2k-desc.c: Likewise.
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* iq2000-dis.c: Likewise.
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* iq2000-desc.c: Likewise.
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* lm32-dis.c: Likewise.
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* lm32-desc.c: Likewise.
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* m32c-dis.c: Likewise.
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* m32c-desc.c: Likewise.
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* m32r-dis.c: Likewise.
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* m32r-desc.c: Likewise.
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* mep-dis.c: Likewise.
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* mep-desc.c: Likewise.
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* mt-dis.c: Likewise.
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* mt-desc.c: Likewise.
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* or1k-dis.c: Likewise.
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* or1k-desc.c: Likewise.
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* xc16x-dis.c: Likewise.
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* xc16x-desc.c: Likewise.
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* xstormy16-dis.c: Likewise.
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* xstormy16-desc.c: Likewise.
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2020-06-03 22:29:09 +08:00
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2020-06-03 Nick Clifton <nickc@redhat.com>
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* po/sr.po: Updated Serbian translation.
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2020-06-02 09:44:13 +08:00
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2020-06-03 Nelson Chu <nelson.chu@sifive.com>
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* riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
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(riscv_get_priv_spec_class): Likewise.
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2020-05-30 10:46:43 +08:00
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2020-06-01 Alan Modra <amodra@gmail.com>
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* bpf-desc.c: Regenerate.
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2020-05-28 22:53:54 +08:00
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2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
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David Faust <david.faust@oracle.com>
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* bpf-desc.c: Regenerate.
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* bpf-opc.h: Likewise.
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* bpf-opc.c: Likewise.
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* bpf-dis.c: Likewise.
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2020-05-28 20:37:11 +08:00
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2020-05-28 Alan Modra <amodra@gmail.com>
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* nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
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values.
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2020-05-28 16:06:31 +08:00
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2020-05-28 Alan Modra <amodra@gmail.com>
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* ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
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immediates.
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(print_insn_ns32k): Revert last change.
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2020-05-28 18:04:27 +08:00
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2020-05-28 Nick Clifton <nickc@redhat.com>
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* ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
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static.
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2020-05-27 14:23:03 +08:00
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2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
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Fix extraction of signed constants in nios2 disassembler (again).
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* nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
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extractions of signed fields.
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2020-05-27 00:34:39 +08:00
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2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
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* s390-opc.txt: Relocate vector load/store instructions with
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additional alignment parameter and change architecture level
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constraint from z14 to z13.
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2020-05-20 21:17:29 +08:00
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2020-05-21 Alan Modra <amodra@gmail.com>
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* arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
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* sparc-dis.c: Likewise.
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* tic4x-dis.c: Likewise.
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* xtensa-dis.c: Likewise.
|
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* bpf-desc.c: Regenerate.
|
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* epiphany-desc.c: Regenerate.
|
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* fr30-desc.c: Regenerate.
|
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* frv-desc.c: Regenerate.
|
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* ip2k-desc.c: Regenerate.
|
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* iq2000-desc.c: Regenerate.
|
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* lm32-desc.c: Regenerate.
|
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* m32c-desc.c: Regenerate.
|
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* m32r-desc.c: Regenerate.
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* mep-asm.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mt-desc.c: Regenerate.
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* or1k-desc.c: Regenerate.
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* xc16x-desc.c: Regenerate.
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* xstormy16-desc.c: Regenerate.
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[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
2020-05-21 00:22:48 +08:00
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2020-05-20 Nelson Chu <nelson.chu@sifive.com>
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* riscv-opc.c (riscv_ext_version_table): The table used to store
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all information about the supported spec and the corresponding ISA
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versions. Currently, only Zicsr is supported to verify the
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correctness of Z sub extension settings. Others will be supported
|
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in the future patches.
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(struct isa_spec_t, isa_specs): List for all supported ISA spec
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classes and the corresponding strings.
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(riscv_get_isa_spec_class): New function. Get the corresponding ISA
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spec class by giving a ISA spec string.
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* riscv-opc.c (struct priv_spec_t): New structure.
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(struct priv_spec_t priv_specs): List for all supported privilege spec
|
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classes and the corresponding strings.
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(riscv_get_priv_spec_class): New function. Get the corresponding
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privilege spec class by giving a spec string.
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(riscv_get_priv_spec_name): New function. Get the corresponding
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privilege spec string by giving a CSR version class.
|
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* riscv-dis.c: Updated since DECLARE_CSR is changed.
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* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
|
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according to the chosen version. Build a hash table riscv_csr_hash to
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store the valid CSR for the chosen pirv verison. Dump the direct
|
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CSR address rather than it's name if it is invalid.
|
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(parse_riscv_dis_option_without_args): New function. Parse the options
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without arguments.
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(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
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parse the options without arguments first, and then handle the options
|
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with arguments. Add the new option -Mpriv-spec, which has argument.
|
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* riscv-dis.c (print_riscv_disassembler_options): Add description
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about the new OBJDUMP option.
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Power10 dcbf, sync, and wait extensions.
opcodes/
* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
WC values on POWER10 sync, dcbf and wait instructions.
(insert_pl, extract_pl): New functions.
(L2OPT, LS, WC): Use insert_ls and extract_ls.
(LS3): New , 3-bit L for sync.
(LS3, L3OPT): New, 3-bit L for sync and dcbf.
(SC2, PL): New, 2-bit SC and PL for sync and wait.
(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
(XOPL3, XWCPL, XSYNCLS): New opcode macros.
(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
<wait>: Enable PL operand on POWER10.
<dcbf>: Enable L3OPT operand on POWER10.
<sync>: Enable SC2 operand on POWER10.
gas/
* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
sync, wait, waitrsv>: Add tests.
* testsuite/gas/ppc/power10.d: Likewise.
2020-05-20 07:09:51 +08:00
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2020-05-19 Peter Bergner <bergner@linux.ibm.com>
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* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
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WC values on POWER10 sync, dcbf and wait instructions.
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(insert_pl, extract_pl): New functions.
|
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(L2OPT, LS, WC): Use insert_ls and extract_ls.
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(LS3): New , 3-bit L for sync.
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(LS3, L3OPT): New, 3-bit L for sync and dcbf.
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(SC2, PL): New, 2-bit SC and PL for sync and wait.
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(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
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(XOPL3, XWCPL, XSYNCLS): New opcode macros.
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(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
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plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
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<wait>: Enable PL operand on POWER10.
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<dcbf>: Enable L3OPT operand on POWER10.
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<sync>: Enable SC2 operand on POWER10.
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2020-05-19 19:40:27 +08:00
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2020-05-19 Stafford Horne <shorne@gmail.com>
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PR 25184
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* or1k-asm.c: Regenerate.
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* or1k-desc.c: Regenerate.
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* or1k-desc.h: Regenerate.
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* or1k-dis.c: Regenerate.
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* or1k-ibld.c: Regenerate.
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* or1k-opc.c: Regenerate.
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* or1k-opc.h: Regenerate.
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* or1k-opinst.c: Regenerate.
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2020-05-11 08:19:29 +08:00
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
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xsmaxcqp, xsmincqp.
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2020-05-11 08:18:29 +08:00
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
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stxvrbx, stxvrhx, stxvrwx, stxvrdx.
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2020-05-11 08:17:38 +08:00
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
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Power10 string operations
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
* testsuite/gas/ppc/stringop.d,
* testsuite/gas/ppc/stringop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:16:45 +08:00
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
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vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
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2020-05-11 08:15:42 +08:00
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2020-05-11 Peter Bergner <bergner@linux.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
|
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mnemonics.
|
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Power10 bit manipulation operations
opcodes/
* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
(prefix_opcodes): Add xxeval.
gas/
* testsuite/gas/ppc/bitmanip.d,
* testsuite/gas/ppc/bitmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:14:25 +08:00
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|
2020-05-11 Alan Modra <amodra@gmail.com>
|
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* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
|
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(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
|
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vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
|
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(prefix_opcodes): Add xxeval.
|
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2020-05-11 08:13:15 +08:00
|
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|
2020-05-11 Alan Modra <amodra@gmail.com>
|
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* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
|
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|
xxgenpcvwm, xxgenpcvdm.
|
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|
Power10 VSX Mask Manipulation Operations
opcodes/
* ppc-opc.c (MP, VXVAM_MASK): Define.
(VXVAPS_MASK): Use VXVA_MASK.
(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
* testsuite/gas/ppc/maskmanip.d,
* testsuite/gas/ppc/maskmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:11:57 +08:00
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|
2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (MP, VXVAM_MASK): Define.
|
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|
(VXVAPS_MASK): Use VXVA_MASK.
|
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(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
|
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|
vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
|
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vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
|
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vcntmbb, vcntmbh, vcntmbw, vcntmbd.
|
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|
Power10 Reduced precision outer product operations
include/
* opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following
PPC_OPERAND defines.
opcodes/
* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
New functions.
(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
YMSK2, XA6a, XA6ap, XB6a entries.
(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
(PPCVSX4): Define.
(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
* config/tc-ppc.c (pre_defined_registers): Add accumulators.
(md_assemble): Check acc specified in correct operand.
* testsuite/gas/ppc/outerprod.d,
* testsuite/gas/ppc/outerprod.s,
* testsuite/gas/ppc/vsx4.d,
* testsuite/gas/ppc/vsx4.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 08:10:42 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
|
|
|
|
|
|
New functions.
|
|
|
|
|
|
(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
|
|
|
|
|
|
YMSK2, XA6a, XA6ap, XB6a entries.
|
|
|
|
|
|
(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
|
|
|
|
|
|
(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
|
|
|
|
|
|
(PPCVSX4): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
|
|
|
|
|
|
xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
|
|
|
|
|
|
xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
|
|
|
|
|
|
xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
|
|
|
|
|
|
xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
|
|
|
|
|
|
xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
|
|
|
|
|
|
xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
|
|
|
|
|
|
(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
|
|
|
|
|
|
pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
|
|
|
|
|
|
pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
|
|
|
|
|
|
pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
|
|
|
|
|
|
pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
|
|
|
|
|
|
pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
|
|
|
|
|
|
pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
|
|
|
|
|
|
|
Power10 SIMD permute class operations
opcodes/
* ppc-opc.c (insert_imm32, extract_imm32): New functions.
(insert_xts, extract_xts): New functions.
(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
(VXRC_MASK, VXSH_MASK): Define.
(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
xxblendvh, xxblendvw, xxblendvd, xxpermx.
gas/
* testsuite/gas/ppc/simd_perm.d,
* testsuite/gas/ppc/simd_perm.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:07:14 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_imm32, extract_imm32): New functions.
|
|
|
|
|
|
(insert_xts, extract_xts): New functions.
|
|
|
|
|
|
(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
|
|
|
|
|
|
(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
|
|
|
|
|
|
(VXRC_MASK, VXSH_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
|
|
|
|
|
|
vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
|
|
|
|
|
|
vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
|
|
|
|
|
|
vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
|
|
|
|
|
|
vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
|
|
|
|
|
|
(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
|
|
|
|
|
|
xxblendvh, xxblendvw, xxblendvd, xxpermx.
|
|
|
|
|
|
|
Power10 128-bit binary integer operations
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
gas/
* testsuite/gas/ppc/int128.d,
* testsuite/gas/ppc/int128.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:06:11 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
|
|
|
|
|
|
vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
|
|
|
|
|
|
vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
|
|
|
|
|
|
vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
|
|
|
|
|
|
xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
|
|
|
|
|
|
|
2020-05-11 08:04:49 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_xtp, extract_xtp): New functions.
|
|
|
|
|
|
(XTP, DQXP, DQXP_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
|
|
|
|
|
|
(prefix_opcodes): Add plxvp and pstxvp.
|
|
|
|
|
|
|
Power10 vector integer multiply, divide, modulo insns
opcodes/
* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
gas/
* testsuite/gas/ppc/vec_mul.s,
* testsuite/gas/ppc/vec_mul.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:02:56 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
|
|
|
|
|
|
vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
|
|
|
|
|
|
vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
|
|
|
|
|
|
|
2020-05-11 08:01:40 +08:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
|
|
|
|
|
|
|
2020-05-11 08:00:19 +08:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
|
|
|
|
|
|
(L1OPT): Define.
|
|
|
|
|
|
(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
|
|
|
|
|
|
|
2020-05-11 07:57:48 +08:00
|
|
|
|
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
|
|
|
|
|
|
|
2020-05-11 07:55:30 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Default to "power10".
|
|
|
|
|
|
|
2020-05-11 07:54:14 +08:00
|
|
|
|
2020-05-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "power10" entry.
|
|
|
|
|
|
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
|
|
|
|
|
|
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
|
|
|
|
|
|
|
2020-05-11 19:02:26 +08:00
|
|
|
|
2020-05-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/fr.po: Updated French translation.
|
|
|
|
|
|
|
2020-04-30 22:47:30 +08:00
|
|
|
|
2020-04-30 Alex Coplan <alex.coplan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add entry for FLD_imm16_2.
|
|
|
|
|
|
(operand_general_constraint_met_p): validate
|
|
|
|
|
|
AARCH64_OPND_UNDEFINED.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
|
|
|
|
|
|
for FLD_imm16_2.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2020-04-29 23:09:38 +08:00
|
|
|
|
2020-04-29 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22699
|
|
|
|
|
|
* sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
|
|
|
|
|
|
and SETRC insns.
|
|
|
|
|
|
|
2020-04-29 20:23:32 +08:00
|
|
|
|
2020-04-29 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2020-04-29 20:13:55 +08:00
|
|
|
|
2020-04-29 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22699
|
|
|
|
|
|
* sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
|
|
|
|
|
|
IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
|
|
|
|
|
|
* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
|
|
|
|
|
|
IMM0_8U case.
|
|
|
|
|
|
|
2020-04-18 20:32:39 +08:00
|
|
|
|
2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25848
|
|
|
|
|
|
* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
|
|
|
|
|
|
cmpi only on m68020up and cpu32.
|
|
|
|
|
|
|
2020-04-20 17:58:16 +08:00
|
|
|
|
2020-04-20 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_none): New.
|
|
|
|
|
|
* aarch64-asm.h (ins_none): New declaration.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_none): New.
|
|
|
|
|
|
* aarch64-dis.h (ext_none): New declaration.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Update case for
|
|
|
|
|
|
AARCH64_OPND_BARRIER_PSB.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
|
|
|
|
|
|
(AARCH64_OPERANDS): Update inserter/extracter for
|
|
|
|
|
|
AARCH64_OPND_BARRIER_PSB to use new dummy functions.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
[AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2020-04-20 17:50:52 +08:00
|
|
|
|
2020-04-20 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
|
|
|
|
|
|
(aarch64_feature_ras, RAS): Likewise.
|
|
|
|
|
|
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
|
|
|
|
|
|
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
|
|
|
|
|
|
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
|
|
|
|
|
|
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2020-04-18 00:25:19 +08:00
|
|
|
|
2020-04-17 Fredrik Strupe <fredrik@strupe.net>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
|
|
|
|
|
|
(print_insn_neon): Support disassembly of conditional
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2020-04-16 15:52:57 +08:00
|
|
|
|
2020-02-16 David Faust <david.faust@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bpf-desc.c: Regenerate.
|
|
|
|
|
|
* bpf-desc.h: Likewise.
|
|
|
|
|
|
* bpf-opc.c: Regenerate.
|
|
|
|
|
|
* bpf-opc.h: Likewise.
|
|
|
|
|
|
|
2020-04-07 13:59:50 +08:00
|
|
|
|
2020-04-07 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
|
|
|
|
|
|
(prefix_table): New instructions (see prefixes above).
|
|
|
|
|
|
(rm_table): Likewise
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
|
|
|
|
|
|
CPU_ANY_TSXLDTRK_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuTSXLDTRK.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuTSXLDTRK.
|
|
|
|
|
|
(i386_cpu_flags): Add cputsxldtrk.
|
|
|
|
|
|
* i386-opc.tbl: Add XSUSPLDTRK insns.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2020-03-06 14:38:15 +08:00
|
|
|
|
2020-04-02 Lili Cui <lili.cui@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): New instructions serialize.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
|
|
|
|
|
|
CPU_ANY_SERIALIZE_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuSERIALIZE.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuSERIALIZE.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuserialize.
|
|
|
|
|
|
* i386-opc.tbl: Add SERIALIZE insns.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2020-03-26 13:56:16 +08:00
|
|
|
|
2020-03-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.h (opcodes_assert): Declare.
|
|
|
|
|
|
(OPCODES_ASSERT): Define.
|
|
|
|
|
|
* disassemble.c: Don't include assert.h. Include opintl.h.
|
|
|
|
|
|
(opcodes_assert): New function.
|
|
|
|
|
|
* h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
|
|
|
|
|
|
(bfd_h8_disassemble): Reduce size of data array. Correctly
|
|
|
|
|
|
calculate maxlen. Omit insn decoding when insn length exceeds
|
|
|
|
|
|
maxlen. Exit from nibble loop when looking for E, before
|
|
|
|
|
|
accessing next data byte. Move processing of E outside loop.
|
|
|
|
|
|
Replace tests of maxlen in loop with assertions.
|
|
|
|
|
|
|
2020-03-26 13:50:47 +08:00
|
|
|
|
2020-03-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
|
|
|
|
|
|
|
2020-03-25 06:20:21 +08:00
|
|
|
|
2020-03-25 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z80-dis.c (suffix): Init mybuf.
|
|
|
|
|
|
|
2020-03-22 17:56:31 +08:00
|
|
|
|
2020-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
|
|
|
|
|
|
successflly read from section.
|
|
|
|
|
|
|
2020-03-22 17:32:55 +08:00
|
|
|
|
2020-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (find_format): Use ISO C string concatenation rather
|
|
|
|
|
|
than line continuation within a string. Don't access needs_limm
|
|
|
|
|
|
before testing opcode != NULL.
|
|
|
|
|
|
|
2020-03-22 15:45:41 +08:00
|
|
|
|
2020-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ns32k-dis.c (print_insn_arg): Update comment.
|
|
|
|
|
|
(print_insn_ns32k): Reduce size of index_offset array, and
|
|
|
|
|
|
initialize, passing -1 to print_insn_arg for args that are not
|
|
|
|
|
|
an index. Don't exit arg loop early. Abort on bad arg number.
|
|
|
|
|
|
|
s12z disassembler tidy
Don't ignore buffer memory read failure, or malloc failure. Lots of
functions get a return status to pass these failures up the chain in
this patch.
opcodes/
* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
* s12z-opc.c: Formatting.
(operands_f): Return an int.
(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
(exg_sex_discrim): Likewise.
(create_immediate_operand, create_bitfield_operand),
(create_register_operand_with_size, create_register_all_operand),
(create_register_all16_operand, create_simple_memory_operand),
(create_memory_operand, create_memory_auto_operand): Don't
segfault on malloc failure.
(z_ext24_decode): Return an int status, negative on fail, zero
on success.
(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
(loop_primitive_decode, shift_decode, psh_pul_decode),
(bit_field_decode): Similarly.
(z_decode_signed_value, decode_signed_value): Similarly. Add arg
to return value, update callers.
(x_opr_decode_with_size): Check all reads, returning NULL on fail.
Don't segfault on NULL operand.
(decode_operation): Return OP_INVALID on first fail.
(decode_s12z): Check all reads, returning -1 on fail.
gas/
* testsuite/gas/s12z/truncated.d: Update expected output.
2020-03-22 12:32:27 +08:00
|
|
|
|
2020-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
|
|
|
|
|
|
* s12z-opc.c: Formatting.
|
|
|
|
|
|
(operands_f): Return an int.
|
|
|
|
|
|
(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
|
|
|
|
|
|
(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
|
|
|
|
|
|
(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
|
|
|
|
|
|
(exg_sex_discrim): Likewise.
|
|
|
|
|
|
(create_immediate_operand, create_bitfield_operand),
|
|
|
|
|
|
(create_register_operand_with_size, create_register_all_operand),
|
|
|
|
|
|
(create_register_all16_operand, create_simple_memory_operand),
|
|
|
|
|
|
(create_memory_operand, create_memory_auto_operand): Don't
|
|
|
|
|
|
segfault on malloc failure.
|
|
|
|
|
|
(z_ext24_decode): Return an int status, negative on fail, zero
|
|
|
|
|
|
on success.
|
|
|
|
|
|
(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
|
|
|
|
|
|
(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
|
|
|
|
|
|
(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
|
|
|
|
|
|
(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
|
|
|
|
|
|
(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
|
|
|
|
|
|
(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
|
|
|
|
|
|
(loop_primitive_decode, shift_decode, psh_pul_decode),
|
|
|
|
|
|
(bit_field_decode): Similarly.
|
|
|
|
|
|
(z_decode_signed_value, decode_signed_value): Similarly. Add arg
|
|
|
|
|
|
to return value, update callers.
|
|
|
|
|
|
(x_opr_decode_with_size): Check all reads, returning NULL on fail.
|
|
|
|
|
|
Don't segfault on NULL operand.
|
|
|
|
|
|
(decode_operation): Return OP_INVALID on first fail.
|
|
|
|
|
|
(decode_s12z): Check all reads, returning -1 on fail.
|
|
|
|
|
|
|
2020-03-20 08:25:58 +08:00
|
|
|
|
2020-03-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c (print_insn_metag): Don't ignore status from
|
|
|
|
|
|
read_memory_func.
|
|
|
|
|
|
|
2020-03-20 08:21:14 +08:00
|
|
|
|
2020-03-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
|
|
|
|
|
|
Initialize parts of buffer not written when handling a possible
|
|
|
|
|
|
2-byte insn at end of section. Don't attempt decoding of such
|
|
|
|
|
|
an insn by the 4-byte machinery.
|
|
|
|
|
|
|
2020-03-20 07:46:28 +08:00
|
|
|
|
2020-03-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
|
|
|
|
|
|
partially filled buffer. Prevent lookup of 4-byte insns when
|
|
|
|
|
|
only VLE 2-byte insns are possible due to section size. Print
|
|
|
|
|
|
".word" rather than ".long" for 2-byte leftovers.
|
|
|
|
|
|
|
2020-03-18 01:02:15 +08:00
|
|
|
|
2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25641
|
|
|
|
|
|
* z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
|
|
|
|
|
|
|
2020-03-13 16:57:10 +08:00
|
|
|
|
2020-03-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (X86_64_0D): Rename to ...
|
|
|
|
|
|
(X86_64_0E): ... this.
|
|
|
|
|
|
|
2020-03-09 23:23:46 +08:00
|
|
|
|
2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
|
2020-03-09 17:14:55 +08:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
|
|
|
|
|
|
3-operand pseudos.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-09 17:14:17 +08:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
|
|
|
|
|
|
vprot*, vpsha*, and vpshl*.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-09 17:13:43 +08:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
|
|
|
|
|
|
vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-09 17:13:04 +08:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (set_bitfield): Ignore zero-length field names.
|
|
|
|
|
|
* i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
|
|
|
|
|
|
cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-09 17:12:14 +08:00
|
|
|
|
2020-03-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (struct template_arg, struct template_instance,
|
|
|
|
|
|
struct template_param, struct template, templates,
|
|
|
|
|
|
parse_template, expand_templates): New.
|
|
|
|
|
|
(process_i386_opcodes): Various local variables moved to
|
|
|
|
|
|
expand_templates. Call parse_template and expand_templates.
|
|
|
|
|
|
* i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:56:47 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
|
|
|
|
|
|
vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
|
|
|
|
|
|
register and memory source templates. Replace VexW= by VexW*
|
|
|
|
|
|
where applicable.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
x86: drop/replace IgnoreSize
Even after commit dc2be329b950 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06 15:55:52 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
|
|
|
|
|
|
VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:53:56 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:53:18 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
|
|
|
|
|
|
(movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
|
|
|
|
|
|
pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
|
|
|
|
|
|
VexW0 on SSE2AVX variants.
|
|
|
|
|
|
(vmovq): Drop NoRex64 from XMM/XMM variants.
|
|
|
|
|
|
(vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
|
|
|
|
|
|
vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
|
|
|
|
|
|
applicable use VexW0.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:52:12 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove Rex64 field.
|
|
|
|
|
|
* i386-opc.h (Rex64): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Remove rex64 field.
|
|
|
|
|
|
* i386-opc.tbl (crc32): Drop Rex64.
|
|
|
|
|
|
Replace Rex64 with Size64 everywhere else.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:50:56 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E_memory): Exclude recording of used address
|
|
|
|
|
|
prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
|
|
|
|
|
|
addressed memory operands for MPX insns.
|
|
|
|
|
|
|
2020-03-06 15:49:45 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
|
|
|
|
|
|
invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
|
|
|
|
|
|
adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
|
|
|
|
|
|
(ptwrite): Split into non-64-bit and 64-bit forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-06 15:48:48 +08:00
|
|
|
|
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
|
|
|
|
|
|
template.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-04 15:58:13 +08:00
|
|
|
|
2020-03-04 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
|
|
|
|
|
|
(prefix_table): Move vmmcall here. Add vmgexit.
|
|
|
|
|
|
(rm_table): Replace vmmcall entry by prefix_table[] escape.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
|
|
|
|
|
|
(cpu_flags): Add CpuSEV_ES entry.
|
|
|
|
|
|
* i386-opc.h (CpuSEV_ES): New.
|
|
|
|
|
|
(union i386_cpu_flags): Add cpusev_es field.
|
|
|
|
|
|
* i386-opc.tbl (vmgexit): New.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-03-04 03:24:16 +08:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
|
|
|
|
|
|
with MnemonicSize.
|
|
|
|
|
|
* i386-opc.h (IGNORESIZE): New.
|
|
|
|
|
|
(DEFAULTSIZE): Likewise.
|
|
|
|
|
|
(IgnoreSize): Removed.
|
|
|
|
|
|
(DefaultSize): Likewise.
|
|
|
|
|
|
(MnemonicSize): New.
|
|
|
|
|
|
(i386_opcode_modifier): Replace ignoresize/defaultsize with
|
|
|
|
|
|
mnemonicsize.
|
|
|
|
|
|
* i386-opc.tbl (IgnoreSize): New.
|
|
|
|
|
|
(DefaultSize): Likewise.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-03-04 00:31:42 +08:00
|
|
|
|
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25627
|
|
|
|
|
|
* z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
x86: Allow integer conversion without suffix in AT&T syntax
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
2020-03-03 23:39:18 +08:00
|
|
|
|
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25622
|
|
|
|
|
|
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
|
|
|
|
|
|
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-02-25 13:04:46 +08:00
|
|
|
|
2020-02-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c: Indent labels correctly.
|
|
|
|
|
|
* aarch64-dis.c: Likewise.
|
|
|
|
|
|
* aarch64-gen.c: Likewise.
|
|
|
|
|
|
* aarch64-opc.c: Likewise.
|
|
|
|
|
|
* alpha-dis.c: Likewise.
|
|
|
|
|
|
* i386-dis.c: Likewise.
|
|
|
|
|
|
* nds32-asm.c: Likewise.
|
|
|
|
|
|
* nfp-dis.c: Likewise.
|
|
|
|
|
|
* visium-dis.c: Likewise.
|
|
|
|
|
|
|
2020-02-25 16:27:07 +08:00
|
|
|
|
2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h (int_vector_base): Make it available for all ARC
|
|
|
|
|
|
CPUs.
|
|
|
|
|
|
|
RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 18:18:49 +08:00
|
|
|
|
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
|
|
|
|
|
|
changed.
|
|
|
|
|
|
|
2020-02-20 06:51:07 +08:00
|
|
|
|
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
|
|
|
|
|
|
c.mv/c.li if rs1 is zero.
|
|
|
|
|
|
|
2020-02-17 23:12:10 +08:00
|
|
|
|
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Replace CpuABM with
|
|
|
|
|
|
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
|
|
|
|
|
|
CPU_POPCNT_FLAGS.
|
|
|
|
|
|
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
|
|
|
|
|
|
* i386-opc.h (CpuABM): Removed.
|
|
|
|
|
|
(CpuPOPCNT): New.
|
|
|
|
|
|
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
|
|
|
|
|
|
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
|
|
|
|
|
|
popcnt. Remove CpuABM from lzcnt.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
x86: fold certain VCVT{,U}SI2S{S,D} templates
There don't really need to be separate Cpu64 and CpuNo64 templates for
these. One small issue with this is that slightly strange code
.intel_syntax noprefix
.code16
.arch i286
.arch .avx
vcvtsi2sd xmm0, xmm0, dword ptr [bx]
vcvtsi2sd xmm0, xmm0, qword ptr [bx]
vcvtsi2sd xmm0, xmm0, ebx
vcvtsi2sd xmm0, xmm0, rbx
now will match in behavior with the AVX512 counterparts in that not
only the 2nd vcvtsi2sd won't assemble, but also the first. The last
two, otoh, will continue to assemble fine (due to the lack of any
memory operand size specifier). As a result, another way to make
things behave more consistently would be to avoid the folding and
add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so
would be to add Cpu386 to any such insn template.
While doing this also make the usual cosmetic adjustments for the
insns touched anyway. Additionally drop the redundant Cpu64 from
the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of
64-bit mode due to there not being anything to match the Reg64
operand.
2020-02-17 15:59:52 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
|
|
|
|
|
|
Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
|
|
|
|
|
|
VexW1 instead of open-coding them.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 15:59:07 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (AddrPrefixOpReg): Define.
|
|
|
|
|
|
(monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
|
|
|
|
|
|
umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
|
|
|
|
|
|
templates. Drop NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 15:56:18 +08:00
|
|
|
|
2020-02-17 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/6518
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
|
|
|
|
|
|
vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
|
|
|
|
|
|
into Intel syntax instance (with Unpsecified) and AT&T one
|
|
|
|
|
|
(without).
|
|
|
|
|
|
(vcvtneps2bf16): Likewise, along with folding the two so far
|
|
|
|
|
|
separate ones.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-17 12:10:20 +08:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
|
|
|
|
|
|
CPU_ANY_SSE4A_FLAGS.
|
|
|
|
|
|
|
2020-02-17 09:07:38 +08:00
|
|
|
|
2020-02-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Correct last change.
|
|
|
|
|
|
|
2020-02-17 00:36:51 +08:00
|
|
|
|
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
|
|
|
|
|
|
CPU_ANY_SSE4_FLAGS.
|
|
|
|
|
|
|
2020-02-14 21:40:19 +08:00
|
|
|
|
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movsx): Remove Intel syntax comments.
|
|
|
|
|
|
(movzx): Likewise.
|
|
|
|
|
|
|
2020-02-14 21:27:28 +08:00
|
|
|
|
2020-02-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25438
|
|
|
|
|
|
* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
|
|
|
|
|
|
destination for Cpu64-only variant.
|
|
|
|
|
|
(movzx): Fold patterns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-13 17:19:28 +08:00
|
|
|
|
2020-02-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
|
|
|
|
|
|
CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
|
|
|
|
|
|
CPU_ANY_SSE4_FLAGS entry.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:20:56 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
|
|
|
|
|
|
with Unspecified, making the present one AT&T syntax only.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:19:52 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-12 23:19:03 +08:00
|
|
|
|
2020-02-12 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/24546
|
|
|
|
|
|
* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
|
|
|
|
|
|
* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
|
|
|
|
|
|
Amd64 and Intel64 templates.
|
|
|
|
|
|
(call, jmp): Likewise for far indirect variants. Dro
|
|
|
|
|
|
Unspecified.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-11 18:20:55 +08:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
|
|
|
|
|
|
* i386-opc.h (ShortForm): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Remove shortform field.
|
|
|
|
|
|
* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
|
|
|
|
|
|
fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
|
|
|
|
|
|
fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
|
|
|
|
|
|
ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
|
|
|
|
|
|
Drop ShortForm.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-02-11 18:20:05 +08:00
|
|
|
|
2020-02-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
|
|
|
|
|
|
fucompi): Drop ShortForm from operand-less templates.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
Ensure *valuep always written by extract_normal return
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2020-02-11 06:41:18 +08:00
|
|
|
|
2020-02-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
|
|
|
|
|
|
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
|
|
|
|
|
|
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
|
|
|
|
|
|
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
|
|
|
|
|
|
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-02-11 00:39:02 +08:00
|
|
|
|
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_cde): Define 'V' parse character.
|
|
|
|
|
|
(cde_opcodes): Add VCX* instructions.
|
|
|
|
|
|
|
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
2020-02-11 00:38:00 +08:00
|
|
|
|
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
|
|
|
|
|
|
Matthew Malcomson <matthew.malcomson@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (struct cdeopcode32): New.
|
|
|
|
|
|
(CDE_OPCODE): New macro.
|
|
|
|
|
|
(cde_opcodes): New disassembly table.
|
|
|
|
|
|
(regnames): New option to table.
|
|
|
|
|
|
(cde_coprocs): New global variable.
|
|
|
|
|
|
(print_insn_cde): New
|
|
|
|
|
|
(print_insn_thumb32): Use print_insn_cde.
|
|
|
|
|
|
(parse_arm_disassembler_options): Parse coprocN args.
|
|
|
|
|
|
|
2020-02-11 00:37:22 +08:00
|
|
|
|
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/25516
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
|
|
|
|
|
|
with ISA64.
|
|
|
|
|
|
* i386-opc.h (AMD64): Removed.
|
|
|
|
|
|
(Intel64): Likewose.
|
|
|
|
|
|
(AMD64): New.
|
|
|
|
|
|
(INTEL64): Likewise.
|
|
|
|
|
|
(INTEL64ONLY): Likewise.
|
|
|
|
|
|
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
|
|
|
|
|
|
* i386-opc.tbl (Amd64): New.
|
|
|
|
|
|
(Intel64): Likewise.
|
|
|
|
|
|
(Intel64Only): Likewise.
|
|
|
|
|
|
Replace AMD64 with Amd64. Update sysenter/sysenter with
|
|
|
|
|
|
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-02-07 22:53:46 +08:00
|
|
|
|
2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25469
|
|
|
|
|
|
* z80-dis.c: Add support for GBZ80 opcodes.
|
|
|
|
|
|
|
2020-02-04 06:00:22 +08:00
|
|
|
|
2020-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
|
|
|
|
|
|
|
2020-02-03 08:56:30 +08:00
|
|
|
|
2020-02-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-02-01 10:38:43 +08:00
|
|
|
|
2020-02-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-31 21:29:18 +08:00
|
|
|
|
2020-01-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
|
|
|
|
|
|
(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
|
|
|
|
|
|
(OP_E_memory): Replace xmm_mdq_mode case label by
|
|
|
|
|
|
vex_scalar_w_dq_mode one.
|
|
|
|
|
|
* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
|
|
|
|
|
|
|
2020-01-31 21:28:43 +08:00
|
|
|
|
2020-01-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
|
|
|
|
|
|
(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
|
|
|
|
|
|
vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
|
|
|
|
|
|
(intel_operand_size): Drop vex_w_dq_mode case label.
|
|
|
|
|
|
|
2020-01-31 16:03:56 +08:00
|
|
|
|
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
|
|
|
|
|
|
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
|
|
|
|
|
|
|
2020-01-30 19:29:20 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 20:59:04 +08:00
|
|
|
|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bpf-opc.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 18:36:33 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
|
|
|
|
|
|
(dis386): Use them to replace C2/C3 table entries.
|
|
|
|
|
|
(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
|
|
|
|
|
|
* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
|
|
|
|
|
|
ones. Use Size64 instead of DefaultSize on Intel64 ones.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 18:33:53 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
|
|
|
|
|
|
forms.
|
|
|
|
|
|
(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
|
|
|
|
|
|
DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 14:36:54 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_dp): Make unsigned.
|
|
|
|
|
|
|
2020-01-27 20:38:10 +08:00
|
|
|
|
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/25445
|
|
|
|
|
|
* i386-dis.c (MOVSXD_Fixup): New function.
|
|
|
|
|
|
(movsxd_mode): New enum.
|
|
|
|
|
|
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
|
|
|
|
|
|
(intel_operand_size): Handle movsxd_mode.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
|
|
|
|
|
|
register on movsxd. Add movsxd with 16-bit destination register
|
|
|
|
|
|
for AMD64 and Intel64 ISAs.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-27 18:40:02 +08:00
|
|
|
|
2020-01-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25403
|
|
|
|
|
|
* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 15:28:25 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (sysret): Drop DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-21 15:25:31 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
|
|
|
|
|
|
Dword.
|
|
|
|
|
|
(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-20 23:10:23 +08:00
|
|
|
|
2020-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2020-01-20 10:02:37 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (fput_const): Remove useless cast.
|
|
|
|
|
|
|
2020-01-20 10:01:58 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Wrap 'T' value.
|
|
|
|
|
|
|
2020-01-18 22:12:07 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2020-01-18 21:50:25 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Binutils 2.34 branch created.
|
|
|
|
|
|
|
2020-01-18 02:34:03 +08:00
|
|
|
|
2020-01-17 Christian Biesinger <cbiesinger@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opintl.h: Fix spelling error (seperate).
|
|
|
|
|
|
|
2020-01-17 23:07:55 +08:00
|
|
|
|
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add {vex} pseudo prefix.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-16 21:50:52 +08:00
|
|
|
|
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25376
|
|
|
|
|
|
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
(select_arm_features): Make sure we enable MVE bits when selecting
|
|
|
|
|
|
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
|
|
|
|
|
|
any architecture.
|
|
|
|
|
|
|
2020-01-16 17:07:05 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop stale comment from XOP section.
|
|
|
|
|
|
|
2020-01-16 17:06:21 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
|
|
|
|
|
|
(extractps): Add VexWIG to SSE2AVX forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-16 17:05:35 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
|
|
|
|
|
|
Size64 from and use VexW1 on SSE2AVX forms.
|
|
|
|
|
|
(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
|
|
|
|
|
|
VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-15 13:37:16 +08:00
|
|
|
|
2020-01-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_version): Make unsigned long.
|
|
|
|
|
|
(optab, optab_special, registernames): New file scope vars.
|
|
|
|
|
|
(tic4x_print_register): Set up registernames rather than
|
|
|
|
|
|
malloc'd registertable.
|
|
|
|
|
|
(tic4x_disassemble): Delete optable and optable_special. Use
|
|
|
|
|
|
optab and optab_special instead. Throw away old optab,
|
|
|
|
|
|
optab_special and registernames when info->mach changes.
|
|
|
|
|
|
|
2020-01-14 21:13:57 +08:00
|
|
|
|
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25377
|
|
|
|
|
|
* z80-dis.c (suffix): Use .db instruction to generate double
|
|
|
|
|
|
prefix.
|
|
|
|
|
|
|
2020-01-14 06:47:09 +08:00
|
|
|
|
2020-01-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
|
|
|
|
|
|
values to unsigned before shifting.
|
|
|
|
|
|
|
Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
(detected_jumps): New variables.
(usage): Add the new jump visualization options.
(option_values): Add new option value.
(long_options): Add the new option.
(jump_info_new, jump_info_free): New functions.
(jump_info_min_address, jump_info_max_address): Likewise.
(jump_info_end_address, jump_info_is_start_address): Likewise.
(jump_info_is_end_address, jump_info_size): Likewise.
(jump_info_unlink, jump_info_insert): Likewise.
(jump_info_add_front, jump_info_move_linked): Likewise.
(jump_info_intersect, jump_info_merge): Likewise.
(jump_info_sort, jump_info_visualize_address): Likewise.
(disassemble_jumps): New function - used to locate jumps.
(disassemble_bytes): Add ascii art generation.
(disassemble_section): Add scan to locate jumps.
(main): Parse the new visualization option.
* doc/binutils.texi: Document the new feature.
* NEWS: Mention the new feature.
opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control
flow instructions.
(print_insn_thumb16, print_insn_thumb32): Likewise.
(print_insn): Initialize the insn info.
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
2020-01-13 20:36:55 +08:00
|
|
|
|
2020-01-13 Thomas Troeger <tstroege@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Fill in insn info fields for control
|
|
|
|
|
|
flow instructions.
|
|
|
|
|
|
(print_insn_thumb16, print_insn_thumb32): Likewise.
|
|
|
|
|
|
(print_insn): Initialize the insn info.
|
|
|
|
|
|
* i386-dis.c (print_insn): Initialize the insn info fields, and
|
|
|
|
|
|
detect jumps.
|
|
|
|
|
|
|
2020-01-13 17:16:47 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (C_NE): Make it required.
|
|
|
|
|
|
|
2020-01-13 16:21:30 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
|
|
|
|
|
|
reserved register name.
|
|
|
|
|
|
|
2020-01-13 15:28:02 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
|
|
|
|
|
|
(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
|
|
|
|
|
|
|
2020-01-13 11:57:19 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
|
|
|
|
|
|
result of wasm_read_leb128 in a uint64_t and check that bits
|
|
|
|
|
|
are not lost when copying to other locals. Use uint32_t for
|
|
|
|
|
|
most locals. Use PRId64 when printing int64_t.
|
|
|
|
|
|
|
2020-01-13 08:48:36 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c: Formatting.
|
|
|
|
|
|
* score7-dis.c: Formatting.
|
|
|
|
|
|
|
2020-01-13 08:16:55 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c (print_insn_score48): Use unsigned variables for
|
|
|
|
|
|
unsigned values. Don't left shift negative values.
|
|
|
|
|
|
(print_insn_score32): Likewise.
|
|
|
|
|
|
* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
|
|
|
|
|
|
|
2020-01-12 17:46:22 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_print_register): Remove dead code.
|
|
|
|
|
|
|
2020-01-11 10:02:11 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-11 09:53:47 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* xgate-dis.c (print_insn): Don't left shift signed value.
|
|
|
|
|
|
(ripBits): Formatting, use 1u.
|
|
|
|
|
|
|
2020-01-10 05:57:33 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
|
|
|
|
|
|
* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
|
|
|
|
|
|
|
2020-01-09 04:29:42 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
|
|
|
|
|
|
and XRREG value earlier to avoid a shift with negative exponent.
|
|
|
|
|
|
* m10200-dis.c (disassemble): Similarly.
|
|
|
|
|
|
|
2020-01-09 22:32:49 +08:00
|
|
|
|
2020-01-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25224
|
|
|
|
|
|
* z80-dis.c (ld_ii_ii): Use correct cast.
|
|
|
|
|
|
|
2020-01-09 19:47:44 +08:00
|
|
|
|
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25224
|
|
|
|
|
|
* z80-dis.c (ld_ii_ii): Use character constant when checking
|
|
|
|
|
|
opcode byte value.
|
|
|
|
|
|
|
2020-01-09 18:38:01 +08:00
|
|
|
|
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (SEP_Fixup): New.
|
|
|
|
|
|
(SEP): Define.
|
|
|
|
|
|
(dis386_twobyte): Use it for sysenter/sysexit.
|
|
|
|
|
|
(enum x86_64_isa): Change amd64 enumerator to value 1.
|
|
|
|
|
|
(OP_J): Compare isa64 against intel64 instead of amd64.
|
|
|
|
|
|
* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
|
|
|
|
|
|
forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-08 09:12:36 +08:00
|
|
|
|
2020-01-08 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z8k-dis.c: Include libiberty.h
|
|
|
|
|
|
(instr_data_s): Make max_fetched unsigned.
|
|
|
|
|
|
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
|
|
|
|
|
|
Don't exceed byte_info bounds.
|
|
|
|
|
|
(output_instr): Make num_bytes unsigned.
|
|
|
|
|
|
(unpack_instr): Likewise for nibl_count and loop.
|
|
|
|
|
|
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
|
|
|
|
|
|
idx unsigned.
|
|
|
|
|
|
* z8k-opc.h: Regenerate.
|
|
|
|
|
|
|
2020-01-07 21:25:15 +08:00
|
|
|
|
2020-01-07 Shahab Vahedi <shahab@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h (llock): Use 'LLOCK' as class.
|
|
|
|
|
|
(llockd): Likewise.
|
|
|
|
|
|
(scond): Use 'SCOND' as class.
|
|
|
|
|
|
(scondd): Likewise.
|
|
|
|
|
|
(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
|
|
|
|
|
|
(scondd): Likewise.
|
|
|
|
|
|
|
2020-01-04 17:23:19 +08:00
|
|
|
|
2020-01-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-06 06:22:39 +08:00
|
|
|
|
2020-01-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25344
|
|
|
|
|
|
* z80-dis.c (suffix): Don't use a local struct buffer copy.
|
|
|
|
|
|
Peek at next byte to prevent recursion on repeated prefix bytes.
|
|
|
|
|
|
Ensure uninitialised "mybuf" is not accessed.
|
|
|
|
|
|
(print_insn_z80): Don't zero n_fetch and n_used here,..
|
|
|
|
|
|
(print_insn_z80_buf): ..do it here instead.
|
|
|
|
|
|
|
2020-01-04 05:41:43 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-03 05:42:00 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
|
|
|
|
|
|
|
2020-01-03 04:37:17 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx-dis.c (match_opcode): Avoid shift left of signed value.
|
|
|
|
|
|
|
2020-01-01 16:16:43 +08:00
|
|
|
|
2020-01-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
|
|
|
|
|
|
|
2020-01-03 17:14:16 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Use
|
|
|
|
|
|
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
|
|
|
|
|
|
|
|
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
|
2020-01-03 17:14:16 +08:00
|
|
|
|
forms of SUDOT and USDOT.
|
|
|
|
|
|
|
2020-01-03 17:13:31 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
|
2020-01-03 17:13:31 +08:00
|
|
|
|
uzip{1,2}.
|
|
|
|
|
|
* opcodes/aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
|
2020-01-03 17:12:49 +08:00
|
|
|
|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
2020-01-03 17:16:44 +08:00
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
|
2020-01-03 17:12:49 +08:00
|
|
|
|
FMMLA encoding.
|
|
|
|
|
|
* opcodes/aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
|
2020-01-02 22:10:40 +08:00
|
|
|
|
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z80-dis.c: Add support for eZ80 and Z80 instructions.
|
|
|
|
|
|
|
2020-01-01 16:22:19 +08:00
|
|
|
|
2020-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
For older changes see ChangeLog-2019
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
Copyright (C) 2020 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
