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x86: Don't disable SSE4a when disabling SSE4 commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also adds .sse4a and nosse4a. gas/ * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore nosse4. * doc/c-i386.texi: Document sse4a and nosse4a. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove CPU_ANY_SSE4_FLAGS.
2020-02-17 00:36:51 +08:00
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
Remove Intel syntax comments on movsx and movzx Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel syntax comments on movsx and movzx to avoid confusing other readers. * i386-opc.tbl (movsx): Remove Intel syntax comments. (movzx): Likewise.
2020-02-14 21:40:19 +08:00
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl (movsx): Remove Intel syntax comments.
(movzx): Likewise.
x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
2020-02-14 21:27:28 +08:00
2020-02-14 Jan Beulich <jbeulich@suse.com>
PR gas/25438
* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
destination for Cpu64-only variant.
(movzx): Fold patterns.
* i386-tbl.h: Re-generate.
x86: fix SSE4a dependencies of ".arch .nosse*" Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
2020-02-13 17:19:28 +08:00
2020-02-13 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
CPU_ANY_SSE4_FLAGS entry.
* i386-init.h: Re-generate.
x86: correct VFPCLASSP{S,D} operand size handling With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
2020-02-12 23:20:56 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
with Unspecified, making the present one AT&T syntax only.
* i386-tbl.h: Re-generate.
x86: fold two JMP templates Now that the AMD64 check in match_template() applies to 64-bit code only, the non-64-bit and the Amd64 template can be folded, as being otherwise compatible with one another. (Oddly enough the same doesn't apply to CALL, due to the suffixes it permits, while JMP doesn't allow for any.)
2020-02-12 23:19:52 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
* i386-tbl.h: Re-generate.
x86-64: Intel64 adjustments for insns dealing with far pointers AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-02-12 23:19:03 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
PR gas/24546
* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
Amd64 and Intel64 templates.
(call, jmp): Likewise for far indirect variants. Dro
Unspecified.
* i386-tbl.h: Re-generate.
x86: drop ShortForm attribute It is very simple to derive from other template properties, and hence there's little point wasting storage for it.
2020-02-11 18:20:55 +08:00
2020-02-11 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
* i386-opc.h (ShortForm): Delete.
(struct i386_opcode_modifier): Remove shortform field.
* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
Drop ShortForm.
* i386-tbl.h: Re-generate.
x86: drop stray ShortForm attributes This attribute is meaningless when there are no operands to encode.
2020-02-11 18:20:05 +08:00
2020-02-11 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
fucompi): Drop ShortForm from operand-less templates.
* i386-tbl.h: Re-generate.
Ensure *valuep always written by extract_normal return * cgen-ibld.in (extract_normal): Set *valuep on all return paths. * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2020-02-11 06:41:18 +08:00
2020-02-11 Alan Modra <amodra@gmail.com>
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
[binutils][arm] Implement Custom Datapath Extensions for MVE Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
2020-02-11 00:39:02 +08:00
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (print_insn_cde): Define 'V' parse character.
(cde_opcodes): Add VCX* instructions.
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-11 00:38:00 +08:00
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
x86: Accept Intel64 only instruction by default Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by default. By default, assembler should accept common, Intel64 only and AMD64 ISAs since there are no conflicts. gas/ PR gas/25516 * config/tc-i386.c (intel64): Renamed to ... (isa64): This. (match_template): Accept Intel64 only instruction by default. (i386_displacement): Updated. (md_parse_option): Updated. * c-i386.texi: Update -mamd64/-mintel64 documentation. * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass -mamd64 to x86-64-sysenter-amd. * testsuite/gas/i386/x86-64-sysenter.d: New file. opcodes/ PR gas/25516 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 with ISA64. * i386-opc.h (AMD64): Removed. (Intel64): Likewose. (AMD64): New. (INTEL64): Likewise. (INTEL64ONLY): Likewise. (i386_opcode_modifier): Replace amd64 and intel64 with isa64. * i386-opc.tbl (Amd64): New. (Intel64): Likewise. (Intel64Only): Likewise. Replace AMD64 with Amd64. Update sysenter/sysenter with Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. * i386-tbl.h: Regenerated.
2020-02-11 00:37:22 +08:00
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-07 22:53:46 +08:00
2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25469
* z80-dis.c: Add support for GBZ80 opcodes.
ubsan: d30v: negation of -2147483648 include/ * opcode/d30v.h (struct pd_reg): Make value field unsigned. opcodes/ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-02-04 06:00:22 +08:00
2020-02-04 Alan Modra <amodra@gmail.com>
* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
ubsan: m32c: left shift of negative value cpu/ * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value. opcodes/ * m32c-ibld.c: Regenerate.
2020-02-03 08:56:30 +08:00
2020-02-03 Alan Modra <amodra@gmail.com>
* m32c-ibld.c: Regenerate.
ubsan: frv: left shift of negative value More non-bugs flagged by ubsan, unless you happen to be compiling for a 1's complement host. cpu/ * frv.cpu (f-u12): Multiply rather than left shift signed values. (f-label16, f-label24): Likewise. opcodes/ * frv-ibld.c: Regenerate.
2020-02-01 10:38:43 +08:00
2020-02-01 Alan Modra <amodra@gmail.com>
* frv-ibld.c: Regenerate.
x86: replace EXxmm_mdq by EXVexWdqScalar There's no need to have two operand specifiers / enumerators for the same purpose. This then renders xmm_mdq_mode unused.
2020-01-31 21:29:18 +08:00
2020-01-31 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
(OP_E_memory): Replace xmm_mdq_mode case label by
vex_scalar_w_dq_mode one.
* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
x86: drop unused EXVexWdq / vex_w_dq_mode
2020-01-31 21:28:43 +08:00
2020-01-31 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
(intel_operand_size): Drop vex_w_dq_mode case label.
aarch64: Fix MOVPRFX markup for bf16 conversions bfcvt converts a .S input to a .H output, so any predicated movprfx needs to operate on .S rather than .H. In common with SVE2 narrowing top operations, bfcvtnt doesn't accept movprfx. 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. Remove C_SCAN_MOVPRFX for SVE bfcvtnt. gas/ * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than .s for the movprfx. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_28.d, * testsuite/gas/aarch64/sve-movprfx_28.l, * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-31 16:03:56 +08:00
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
ubsan: m32c: left shift of negative value More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate.
2020-01-30 19:29:20 +08:00
2020-01-30 Alan Modra <amodra@gmail.com>
* m32c-ibld.c: Regenerate.
cpu,opcodes,gas: fix neg and neg32 instructions in BPF This patch fixes the neg/neg32 BPF instructions, which have K (=0) instead of X (=1) in their header source bit, despite operating on registes. cpu/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-alu-insn-un): The unary BPF instructions (neg and neg32) use OP_SRC_K even if they operate only in registers. opcodes/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c: Regenerate. gas/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. * testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 20:59:04 +08:00
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c: Regenerate.
x86-64: honor vendor specifics for near RET While vendors agree about default operand size (64 bits) and hence unavilability of a 32-bit form, AMD honors a 16-bit operand size override (0x66) while Intel doesn't.
2020-01-30 18:36:33 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
(dis386): Use them to replace C2/C3 table entries.
(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
ones. Use Size64 instead of DefaultSize on Intel64 ones.
* i386-tbl.h: Re-generate.
x86: drop further pointless/bogus DefaultSize - 64-bit CALL permitting just a single operand size doesn't need it. - FLDENV et al should never have had it. It remains suspicious that a number of 64-bit only insns continue to have the attribute, despite this being intended for .code16gcc handling only.
2020-01-30 18:33:53 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
forms.
(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
DefaultSize.
* i386-tbl.h: Re-generate.
ubsan: tic4x: left shift cannot be represented in type 'int' The patch also fixes a case where libopcodes built for a 64-bit bfd_vma may print different results to libopcodes built for a 32-bit bfd_vma. * tic4x-dis.c (tic4x_dp): Make unsigned.
2020-01-30 14:36:54 +08:00
2020-01-30 Alan Modra <amodra@gmail.com>
* tic4x-dis.c (tic4x_dp): Make unsigned.
x86-64: Properly encode and decode movsxd movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit destination registers. Its AT&T mnemonic is movslq which only supports 64-bit destination register. There is also a discrepancy between AMD64 and Intel64 on movsxd with 16-bit destination register. AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit destination registers. It also handles movsxd with 16-bit destination register for AMD64 and Intel 64. gas/ PR binutils/25445 * config/tc-i386.c (check_long_reg): Also convert to QWORD for movsxd. * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA differences. Document movslq and movsxd. * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd.d: Likewise. * testsuite/gas/i386/x86-64-movsxd.s: Likewise. opcodes/ PR binutils/25445 * i386-dis.c (MOVSXD_Fixup): New function. (movsxd_mode): New enum. (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. (intel_operand_size): Handle movsxd_mode. (OP_E_register): Likewise. (OP_G): Likewise. * i386-opc.tbl: Remove Rex64 and allow 32-bit destination register on movsxd. Add movsxd with 16-bit destination register for AMD64 and Intel64 ISAs. * i386-tbl.h: Regenerated.
2020-01-27 20:38:10 +08:00
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
Jan Beulich <jbeulich@suse.com>
PR binutils/25445
* i386-dis.c (MOVSXD_Fixup): New function.
(movsxd_mode): New enum.
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
(intel_operand_size): Handle movsxd_mode.
(OP_E_register): Likewise.
(OP_G): Likewise.
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
register on movsxd. Add movsxd with 16-bit destination register
for AMD64 and Intel64 ISAs.
* i386-tbl.h: Regenerated.
AArch64: Fix cfinv disassembly issues This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2020-01-27 18:40:02 +08:00
2020-01-27 Tamar Christina <tamar.christina@arm.com>
PR 25403
* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
* aarch64-asm-2.c: Regenerate
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
x86: improve handling of insns with ambiguous operand sizes Commit b76bc5d54e ("x86: don't default variable shift count insns to 8-bit operand size") pointed out a very bad case, but the underlying problem is, as mentioned on various occasions, much larger: Silently selecting a (nowhere documented afaict) certain default operand size when there's no "sizing" suffix and no suitable register operand(s) is simply dangerous (for the programmer to make mistakes). While in Intel syntax mode such mistakes already lead to an error (which is going to remain that way), AT&T syntax mode now gains warnings in such cases by default, which can be suppressed or promoted to an error if so desired by the programmer. Furthermore at least general purpose insns now consistently have a default applied (alongside the warning emission), rather than accepting some and refusing others. No warnings are (as before) to be generated for "DefaultSize" insns as well as ones acting on selector and other fixed-width values. For SYSRET, however, the DefaultSize needs to be dropped - it had been wrongly put there in the first place, as it's unrelated to .code16gcc (no stack accesses involved). As set forth as a prereq when I first mentioned this intended change a few years back, Linux as well as gcc have meanwhile been patched to avoid (emission of) ambiguous operands (and hence triggering of the new warning). Note that I think that in 64-bit mode IRET and far RET would better get a diagnostic too, as it's reasonably likely that a suffix-less instance really is meant to be a 64-bit one. But I guess I better make this a separate follow-on patch. Note further that floating point operations with integer operands are an exception for now: They continue to use short (16-bit) operands by default even in 32- and 64-bit modes. Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also need to be diagnosed, with their 64-bit forms not being very useful I think it is better to continue to avoid warning about them (by way of them carrying IgnoreSize attributes).
2020-01-21 15:28:25 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (sysret): Drop DefaultSize.
* i386-tbl.h: Re-generate.
x86: VCVTNEPS2BF16{X,Y} should permit broadcasting Just like other VCVT*{X,Y} templates do, and to allow the programmer flexibility (might be relevant in particular when heavily macro-izing code), the two templates should also have Broadcast set, just like their X/Y-suffix-less counterparts. This in turn requires them to also have * Dword set on their memory operands, to cover the logic added to i386gen by 4a1b91eabbe7 ("x86: Expand Broadcast to 3 bits"), * RegXMM/RegYMM set on their source operands, to satisfy broadcast sizing logic in gas itself. Otherwise ATTSyntax templates wouldn't need such operand size attributes. While extending the test cases, also add Intel syntax broadcast forms without explicit size specifiers.
2020-01-21 15:25:31 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
Dword.
(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
* i386-tbl.h: Re-generate.
Updated translations for various binutils sub-directories
2020-01-20 23:10:23 +08:00
2020-01-20 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/pt_BR.po: Updated Brazilian Portuguese translation.
* po/uk.po: Updated Ukranian translation.
ubsan: hppa: negation of -2147483648 * hppa-dis.c (fput_const): Remove useless cast.
2020-01-20 10:02:37 +08:00
2020-01-20 Alan Modra <amodra@gmail.com>
* hppa-dis.c (fput_const): Remove useless cast.
ubsan: arm: out of bounds array access .inst 0x81bdfe9f disassembles as 0: 81bdfe9f ldaexdhi pc, reg-names-std, [sp] I'm quite sure "reg-names-std" isn't an ARM register. * arm-dis.c (print_insn_arm): Wrap 'T' value.
2020-01-20 10:01:58 +08:00
2020-01-20 Alan Modra <amodra@gmail.com>
* arm-dis.c (print_insn_arm): Wrap 'T' value.
Update version to 2.34.50. Regenerate configure and .pot files.
2020-01-18 22:12:07 +08:00
2020-01-18 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
Add markers for 2.34 branch to the NEWS files and ChangeLogs.
2020-01-18 21:50:25 +08:00
2020-01-18 Nick Clifton <nickc@redhat.com>
Binutils 2.34 branch created.
Fix spelling errors seperate -> separate bfd/ChangeLog: 2020-01-17 Christian Biesinger <cbiesinger@google.com> * coff-arm.c: Fix spelling error (seperate). * elfxx-riscv.c (riscv_parse_sv_or_non_std_ext): Fix spelling error (seperate). * sysdep.h (strnlen): Fix spelling error (seperate). opcodes/ChangeLog: 2020-01-17 Christian Biesinger <cbiesinger@google.com> * opintl.h: Fix spelling error (seperate). sim/arm/ChangeLog: 2020-01-17 Christian Biesinger <cbiesinger@google.com> * iwmmxt.c: Fix spelling error (seperate). Change-Id: I55e5f47bcf3cf3533d2acb7ad338f1be0d5f30f9
2020-01-18 02:34:03 +08:00
2020-01-17 Christian Biesinger <cbiesinger@google.com>
* opintl.h: Fix spelling error (seperate).
x86: Add {vex} pseudo prefix There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix can't encode all operands. By default, assembler tries 2-byte VEX prefix first. {vex3} can be used to force 3-byte VEX prefix. This patch adds {vex} pseudo prefix and keeps {vex2} for backward compatibility. gas/ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 with vex_encoding_vex. (parse_insn): Likewise. * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} and {vex3} documentation. * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with {vex}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-opc.tbl: Add {vex} pseudo prefix. * i386-tbl.h: Regenerated.
2020-01-17 23:07:55 +08:00
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add {vex} pseudo prefix.
* i386-tbl.h: Regenerated.
[binutils][arm] PR25376 Change MVE into a CORE_HIGH feature This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-16 21:50:52 +08:00
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
any architecture.
x86: drop stale Vec_Imm4 related comment I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably because of the mis-spelling.
2020-01-16 17:07:05 +08:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Drop stale comment from XOP section.
x86: add a few more missing VexWIG Alternatively it could also be VexW0 (to match other SSE2AVX), but the VexW attribute shouldn't be left unset.
2020-01-16 17:06:21 +08:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
(extractps): Add VexWIG to SSE2AVX forms.
* i386-tbl.h: Re-generate.
x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
2020-01-16 17:05:35 +08:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
Size64 from and use VexW1 on SSE2AVX forms.
(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
* i386-tbl.h: Re-generate.
tic4x disassembly static variables tic4x uses a number of static variables for tables that are generated depending on the current machine (tic4x vs. tic3x). However, it is possible to change the machine from one invocation of print_insn_tic4x to the next. This patch throws away the old state if that happens, and uses a relatively small known size array of register names rather than a malloc'd table. * tic4x-dis.c (tic4x_version): Make unsigned long. (optab, optab_special, registernames): New file scope vars. (tic4x_print_register): Set up registernames rather than malloc'd registertable. (tic4x_disassemble): Delete optable and optable_special. Use optab and optab_special instead. Throw away old optab, optab_special and registernames when info->mach changes.
2020-01-15 13:37:16 +08:00
2020-01-15 Alan Modra <amodra@gmail.com>
* tic4x-dis.c (tic4x_version): Make unsigned long.
(optab, optab_special, registernames): New file scope vars.
(tic4x_print_register): Set up registernames rather than
malloc'd registertable.
(tic4x_disassemble): Delete optable and optable_special. Use
optab and optab_special instead. Throw away old optab,
optab_special and registernames when info->mach changes.
Fix various assembler testsuite failures for the Z80 target. PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
2020-01-14 21:13:57 +08:00
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25377
* z80-dis.c (suffix): Use .db instruction to generate double
prefix.
ubsan: z8k: left shift cannot be represented in type 'int' * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short values to unsigned before shifting.
2020-01-14 06:47:09 +08:00
2020-01-14 Alan Modra <amodra@gmail.com>
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
values to unsigned before shifting.
Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions. binutils* objdump.c (visualize_jumps, color_output, extended_color_output) (detected_jumps): New variables. (usage): Add the new jump visualization options. (option_values): Add new option value. (long_options): Add the new option. (jump_info_new, jump_info_free): New functions. (jump_info_min_address, jump_info_max_address): Likewise. (jump_info_end_address, jump_info_is_start_address): Likewise. (jump_info_is_end_address, jump_info_size): Likewise. (jump_info_unlink, jump_info_insert): Likewise. (jump_info_add_front, jump_info_move_linked): Likewise. (jump_info_intersect, jump_info_merge): Likewise. (jump_info_sort, jump_info_visualize_address): Likewise. (disassemble_jumps): New function - used to locate jumps. (disassemble_bytes): Add ascii art generation. (disassemble_section): Add scan to locate jumps. (main): Parse the new visualization option. * doc/binutils.texi: Document the new feature. * NEWS: Mention the new feature. opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control flow instructions. (print_insn_thumb16, print_insn_thumb32): Likewise. (print_insn): Initialize the insn info. * i386-dis.c (print_insn): Initialize the insn info fields, and detect jumps.
2020-01-13 20:36:55 +08:00
2020-01-13 Thomas Troeger <tstroege@gmx.de>
* arm-dis.c (print_insn_arm): Fill in insn info fields for control
flow instructions.
(print_insn_thumb16, print_insn_thumb32): Likewise.
(print_insn): Initialize the insn info.
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
[ARC][committed] Code cleanup and improvements. Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
2020-01-13 17:16:47 +08:00
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
* arc-opc.c (C_NE): Make it required.
[ARC] [COMMITTED] Change ACCL/ACCH reg name to generic. ACCL/ACCH register names are only available for ARCv2 architecture, leading to a confusion when disassembling for any other ARC variants. This patch is changing the default names for ACCL/ACCH to generic r58/r59. 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo reserved register name.
2020-01-13 16:21:30 +08:00
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
reserved register name.
asan: ns32k: wild memory write index_offset isn't set up for "sfsr", resulting in a random offset being used when trying to disassemble the following. .byte 0x3e, 0xf7, 0x07, 0x00 * ns32k-dis.c (Is_gen): Use strchr, add 'f'. (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2020-01-13 15:28:02 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
ubsan: wasm32: signed integer overflow The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
2020-01-13 11:57:19 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
result of wasm_read_leb128 in a uint64_t and check that bits
are not lost when copying to other locals. Use uint32_t for
most locals. Use PRId64 when printing int64_t.
score formatting * score-dis.c: Formatting. * score7-dis.c: Formatting.
2020-01-13 08:48:36 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* score-dis.c: Formatting.
* score7-dis.c: Formatting.
ubsan: score: left shift of negative value * score-dis.c (print_insn_score48): Use unsigned variables for unsigned values. Don't left shift negative values. (print_insn_score32): Likewise. * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2020-01-13 08:16:55 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* score-dis.c (print_insn_score48): Use unsigned variables for
unsigned values. Don't left shift negative values.
(print_insn_score32): Likewise.
* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
tic4x: sign extension using shifts Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-12 17:46:22 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* tic4x-dis.c (tic4x_print_register): Remove dead code.
ubsan: fr30: left shift of negative value cpu/ * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't left shift signed values. opcodes/ * fr30-ibld.c: Regenerate.
2020-01-11 10:02:11 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* fr30-ibld.c: Regenerate.
ubsan: xgate: left shift of negative value * xgate-dis.c (print_insn): Don't left shift signed value. (ripBits): Formatting, use 1u.
2020-01-11 09:53:47 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* xgate-dis.c (print_insn): Don't left shift signed value.
(ripBits): Formatting, use 1u.
ubsan: tilepro: signed integer overflow * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2020-01-10 05:57:33 +08:00
2020-01-10 Alan Modra <amodra@gmail.com>
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
ubsan: m10300: shift exponent -4 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, and XRREG value earlier to avoid a shift with negative exponent. * m10200-dis.c (disassemble): Similarly.
2020-01-09 04:29:42 +08:00
2020-01-10 Alan Modra <amodra@gmail.com>
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
and XRREG value earlier to avoid a shift with negative exponent.
* m10200-dis.c (disassemble): Similarly.
Fix the cast used to prevent compile time warning about an always false test. PR 25224 * z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09 22:32:49 +08:00
2020-01-09 Nick Clifton <nickc@redhat.com>
PR 25224
* z80-dis.c (ld_ii_ii): Use correct cast.
Fix compile time warnings about comparisons always being false. PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09 19:47:44 +08:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25224
* z80-dis.c (ld_ii_ii): Use character constant when checking
opcode byte value.
x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-09 18:38:01 +08:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (SEP_Fixup): New.
(SEP): Define.
(dis386_twobyte): Use it for sysenter/sysexit.
(enum x86_64_isa): Change amd64 enumerator to value 1.
(OP_J): Compare isa64 against intel64 instead of amd64.
* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
forms.
* i386-tbl.h: Re-generate.
ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]' The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-08 09:12:36 +08:00
2020-01-08 Alan Modra <amodra@gmail.com>
* z8k-dis.c: Include libiberty.h
(instr_data_s): Make max_fetched unsigned.
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
Don't exceed byte_info bounds.
(output_instr): Make num_bytes unsigned.
(unpack_instr): Likewise for nibl_count and loop.
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
idx unsigned.
* z8k-opc.h: Regenerate.
[ARC] Add finer details for LLOCK and SCOND This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-07 21:25:15 +08:00
2020-01-07 Shahab Vahedi <shahab@synopsys.com>
* arc-tbl.h (llock): Use 'LLOCK' as class.
(llockd): Likewise.
(scond): Use 'SCOND' as class.
(scondd): Likewise.
(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
(scondd): Likewise.
ubsan: m32c: left shift of negative value There are probably a lot more of these still here. cpu/ * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign bits before shifting rather than masking after shifting. (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise. (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise. (f-dsp-64-u16, f-dsp-8-s24): Likewise. (f-bitbase32-16-s19-unprefixed): Avoid signed left shift. opcodes/ * m32c-ibld.c: Regenerate.
2020-01-04 17:23:19 +08:00
2020-01-06 Alan Modra <amodra@gmail.com>
* m32c-ibld.c: Regenerate.
PR25344, z80 disassembler recursion PR 25344 * z80-dis.c (suffix): Don't use a local struct buffer copy. Peek at next byte to prevent recursion on repeated prefix bytes. Ensure uninitialised "mybuf" is not accessed. (print_insn_z80): Don't zero n_fetch and n_used here,.. (print_insn_z80_buf): ..do it here instead.
2020-01-06 06:22:39 +08:00
2020-01-06 Alan Modra <amodra@gmail.com>
PR 25344
* z80-dis.c (suffix): Don't use a local struct buffer copy.
Peek at next byte to prevent recursion on repeated prefix bytes.
Ensure uninitialised "mybuf" is not accessed.
(print_insn_z80): Don't zero n_fetch and n_used here,..
(print_insn_z80_buf): ..do it here instead.
ubsan: m32r: left shift of negative value cpu/ * m32r.cpu (f-disp8): Avoid left shift of negative values. (f-disp16, f-disp24): Likewise. opcodes/ * m32r-ibld.c: Regenerate.
2020-01-04 05:41:43 +08:00
2020-01-04 Alan Modra <amodra@gmail.com>
* m32r-ibld.c: Regenerate.
ubsan: cr16: left shift cannot be represented in type 'int' * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-03 05:42:00 +08:00
2020-01-04 Alan Modra <amodra@gmail.com>
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
ubsan: crx: left shift cannot be represented in type 'int' * crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-03 04:37:17 +08:00
2020-01-04 Alan Modra <amodra@gmail.com>
* crx-dis.c (match_opcode): Avoid shift left of signed value.
ubsan: d30v: left shift cannot be represented in type 'int' * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-01 16:16:43 +08:00
2020-01-04 Alan Modra <amodra@gmail.com>
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 17:14:16 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 17:16:44 +08:00
* aarch64-tbl.h (aarch64_opcode_table): Use
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 17:14:16 +08:00
forms of SUDOT and USDOT.
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 17:13:31 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 17:16:44 +08:00
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 17:13:31 +08:00
uzip{1,2}.
* opcodes/aarch64-dis-2.c: Re-generate.
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 17:12:49 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 17:16:44 +08:00
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 17:12:49 +08:00
FMMLA encoding.
* opcodes/aarch64-dis-2.c: Re-generate.
Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 22:10:40 +08:00
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* z80-dis.c: Add support for eZ80 and Z80 instructions.
Re: Update year range in copyright notice of binutils files Add the ChangeLog entry.
2020-01-01 16:22:19 +08:00
2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2020-01-01 15:37:11 +08:00
For older changes see ChangeLog-2019
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2020-01-01 15:37:11 +08:00
Copyright (C) 2020 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
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