[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-09-26 18:02:28 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for
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scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
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(aarch64_sys_reg_supported_p): New checks for above.
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[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
2018-09-26 18:00:49 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
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(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
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with the hint immediate.
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* aarch64-opc.c (aarch64_hint_options): New entries for
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c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
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(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
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while checking for HINT_OPD_F_NOPRINT flag.
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* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
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extract value.
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* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
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(aarch64_opcode_table): Add entry for BTI.
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(AARCH64_OPERANDS): Add new description for BTI targets.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-09-26 17:57:16 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for
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rndr and rndrrs.
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(aarch64_sys_reg_supported_p): New check for above.
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2018-09-26 17:54:07 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
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(aarch64_sys_ins_reg_supported_p): New check for above.
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2018-09-26 17:52:51 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
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AARCH64_OPND_SYSREG_SR.
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* aarch64-opc.c (aarch64_print_operand): Likewise.
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(aarch64_sys_regs_sr): Define table.
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(aarch64_sys_ins_reg_supported_p): Check for RCTX with
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AARCH64_FEATURE_PREDRES.
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* aarch64-tbl.h (aarch64_feature_predres): New.
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(PREDRES, PREDRES_INSN): New.
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(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
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(AARCH64_OPERANDS): Add new description for SYSREG_SR.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-09-26 17:47:40 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_sb): New.
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(SB, SB_INSN): New.
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(aarch64_opcode_table): Add entry for sb.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
2018-09-26 17:45:35 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_flagmanip): New.
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(aarch64_feature_frintts): New.
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(FLAGMANIP, FRINTTS): New.
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(aarch64_opcode_table): Add entries for xaflag, axflag
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and frint[32,64][x,z] instructions.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-09-26 17:38:59 +08:00
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
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(ARMV8_5, V8_5_INSN): New.
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2018-10-08 20:33:42 +08:00
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2018-10-08 Tamar Christina <tamar.christina@arm.com>
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* aarch64-opc.c (verify_constraints): Use memset instead of {0}.
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2018-10-06 02:56:42 +08:00
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2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (rm_table): Add enclv.
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* i386-opc.tbl: Add enclv.
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* i386-tbl.h: Regenerated.
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2018-10-05 17:49:53 +08:00
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2018-10-05 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (arm_opcodes): Add sb.
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(thumb32_opcodes): Likewise.
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or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 10:41:41 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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Stafford Horne <shorne@gmail.com>
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* or1k-desc.c: Regenerate.
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* or1k-desc.h: Regenerate.
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* or1k-opc.c: Regenerate.
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* or1k-opc.h: Regenerate.
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* or1k-opinst.c: Regenerate.
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or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
2018-10-05 10:41:41 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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* or1k-asm.c: Regenerated.
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* or1k-desc.c: Regenerated.
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* or1k-desc.h: Regenerated.
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* or1k-dis.c: Regenerated.
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* or1k-ibld.c: Regenerated.
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* or1k-opc.c: Regenerated.
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* or1k-opc.h: Regenerated.
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* or1k-opinst.c: Regenerated.
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or1k: Add relocations for high-signed and low-stores
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
2018-10-05 10:41:40 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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* or1k-asm.c: Regenerate.
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2018-10-04 01:51:11 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
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* aarch64-dis.c (print_operands): Refactor to take notes.
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(print_verifier_notes): New.
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(print_aarch64_insn): Apply constraint verifier.
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(print_insn_aarch64_word): Update call to print_aarch64_insn.
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* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
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2018-10-04 01:38:42 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-opc.c (init_insn_block): New.
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(verify_constraints, aarch64_is_destructive_by_operands): New.
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* aarch64-opc.h (verify_constraints): New.
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2018-10-04 01:37:07 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
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* aarch64-opc.c (verify_ldpsw): Update arguments.
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2018-10-04 01:35:15 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
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(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
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2018-10-04 01:27:52 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
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* aarch64-dis.c (insn_sequence): New.
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AArch64: Mark sve instructions that require MOVPRFX constraints
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
2018-10-04 01:22:15 +08:00
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
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_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
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_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
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V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
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constraints.
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(_SVE_INSNC): New.
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(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
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constraints.
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(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
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F_SCAN flags.
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(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
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sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
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sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
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sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
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uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
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uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
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C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
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2018-10-02 23:26:32 +08:00
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2018-10-02 Palmer Dabbelt <palmer@sifive.com>
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* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
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2018-09-24 03:31:23 +08:00
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2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
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* nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
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are used when extracting signed fields and converting them to
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potentially 64-bit types.
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2018-09-21 22:27:48 +08:00
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2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
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* Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
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* Makefile.in: Re-generate.
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* aclocal.m4: Re-generate.
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* configure: Re-generate.
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* configure.ac: Remove check for -Wno-missing-field-initializers.
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* csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
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(csky_v2_opcodes): Likewise.
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2018-09-20 22:49:00 +08:00
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2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
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* arc-nps400-tbl.h: Append `ull' to large constants throughout.
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Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream!
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
2018-09-20 20:27:31 +08:00
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2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
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* nds32-asm.c (operand_fields): Remove the unused fields.
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(nds32_opcodes): Remove the unused instructions.
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* nds32-dis.c (nds32_ex9_info): Removed.
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(nds32_parse_opcode): Updated.
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(print_insn_nds32): Likewise.
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* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
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(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
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(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
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build_opcode_hash_table): New functions.
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(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
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nds32_opcode_table): New.
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(hw_ktabs): Declare it to a pointer rather than an array.
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(build_hash_table): Removed.
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* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
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SYN_ROPT and upadte HW_GPR and HW_INT.
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* nds32-dis.c (keywords): Remove const.
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(match_field): New function.
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(nds32_parse_opcode): Updated.
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* disassemble.c (disassemble_init_for_target):
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Add disassemble_init_nds32.
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* nds32-dis.c (eum map_type): New.
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(nds32_private_data): Likewise.
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(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
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nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
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(print_insn_nds32): Updated.
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* nds32-asm.c (parse_aext_reg): Add new parameter.
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(parse_re, parse_re2, parse_aext_reg): Only reduced registers
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are allowed to use.
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All callers changed.
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* nds32-asm.c (keyword_usr, keyword_sr): Updated.
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(operand_fields): Add new fields.
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(nds32_opcodes): Add new instructions.
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(keyword_aridxi_mx): New keyword.
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* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
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and NASM_ATTR_ZOL.
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(ALU2_1, ALU2_2, ALU2_3): New macros.
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* nds32-dis.c (nds32_filter_unknown_insn): Updated.
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2018-09-18 02:43:08 +08:00
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2018-09-17 Kito Cheng <kito@andestech.com>
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* riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
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x86: Set EVex=2 on EVEX.128 only vmovd and vmovq
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64",
"VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2"
can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and
vmovq.
gas/
PR gas/23670
* testsuite/gas/i386/evex-lig-2.d: New file.
* testsuite/gas/i386/evex-lig-2.s: Likewise.
* testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise.
* testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise.
* testsuite/gas/i386/i386.exp: Run evex-lig-2 and
x86-64-evex-lig-2.
opcodes/
PR gas/23670
* i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
(EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
(EVEX_LEN_0F7E_P_1): Likewise.
(EVEX_LEN_0F7E_P_2): Likewise.
(EVEX_LEN_0FD6_P_2): Likewise.
* i386-dis.c (USE_EVEX_LEN_TABLE): New.
(EVEX_LEN_TABLE): Likewise.
(EVEX_LEN_0F6E_P_2): New enum.
(EVEX_LEN_0F7E_P_1): Likewise.
(EVEX_LEN_0F7E_P_2): Likewise.
(EVEX_LEN_0FD6_P_2): Likewise.
(evex_len_table): New.
(get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
* i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
* i386-tbl.h: Regenerated.
2018-09-18 00:33:20 +08:00
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2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/23670
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* i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
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EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
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(EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
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(EVEX_LEN_0F7E_P_1): Likewise.
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(EVEX_LEN_0F7E_P_2): Likewise.
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(EVEX_LEN_0FD6_P_2): Likewise.
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* i386-dis.c (USE_EVEX_LEN_TABLE): New.
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(EVEX_LEN_TABLE): Likewise.
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(EVEX_LEN_0F6E_P_2): New enum.
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(EVEX_LEN_0F7E_P_1): Likewise.
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(EVEX_LEN_0F7E_P_2): Likewise.
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(EVEX_LEN_0FD6_P_2): Likewise.
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(evex_len_table): New.
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(get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
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* i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
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* i386-tbl.h: Regenerated.
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2018-09-18 00:31:07 +08:00
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2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/23665
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* i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
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VEX_LEN_0F7E_P_2 entries.
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* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
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* i386-tbl.h: Regenerated.
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x86: Update disassembler for VexWIG
The VEX.W bit is ignored by some VEX instructions, aka WIG instructions.
Update x86 disassembler to handle VEX WIG instructions.
* i386-dis.c (VZERO_Fixup): Removed.
(VZERO): Likewise.
(VEX_LEN_0F10_P_1): Likewise.
(VEX_LEN_0F10_P_3): Likewise.
(VEX_LEN_0F11_P_1): Likewise.
(VEX_LEN_0F11_P_3): Likewise.
(VEX_LEN_0F2E_P_0): Likewise.
(VEX_LEN_0F2E_P_2): Likewise.
(VEX_LEN_0F2F_P_0): Likewise.
(VEX_LEN_0F2F_P_2): Likewise.
(VEX_LEN_0F51_P_1): Likewise.
(VEX_LEN_0F51_P_3): Likewise.
(VEX_LEN_0F52_P_1): Likewise.
(VEX_LEN_0F53_P_1): Likewise.
(VEX_LEN_0F58_P_1): Likewise.
(VEX_LEN_0F58_P_3): Likewise.
(VEX_LEN_0F59_P_1): Likewise.
(VEX_LEN_0F59_P_3): Likewise.
(VEX_LEN_0F5A_P_1): Likewise.
(VEX_LEN_0F5A_P_3): Likewise.
(VEX_LEN_0F5C_P_1): Likewise.
(VEX_LEN_0F5C_P_3): Likewise.
(VEX_LEN_0F5D_P_1): Likewise.
(VEX_LEN_0F5D_P_3): Likewise.
(VEX_LEN_0F5E_P_1): Likewise.
(VEX_LEN_0F5E_P_3): Likewise.
(VEX_LEN_0F5F_P_1): Likewise.
(VEX_LEN_0F5F_P_3): Likewise.
(VEX_LEN_0FC2_P_1): Likewise.
(VEX_LEN_0FC2_P_3): Likewise.
(VEX_LEN_0F3A0A_P_2): Likewise.
(VEX_LEN_0F3A0B_P_2): Likewise.
(VEX_W_0F10_P_0): Likewise.
(VEX_W_0F10_P_1): Likewise.
(VEX_W_0F10_P_2): Likewise.
(VEX_W_0F10_P_3): Likewise.
(VEX_W_0F11_P_0): Likewise.
(VEX_W_0F11_P_1): Likewise.
(VEX_W_0F11_P_2): Likewise.
(VEX_W_0F11_P_3): Likewise.
(VEX_W_0F12_P_0_M_0): Likewise.
(VEX_W_0F12_P_0_M_1): Likewise.
(VEX_W_0F12_P_1): Likewise.
(VEX_W_0F12_P_2): Likewise.
(VEX_W_0F12_P_3): Likewise.
(VEX_W_0F13_M_0): Likewise.
(VEX_W_0F14): Likewise.
(VEX_W_0F15): Likewise.
(VEX_W_0F16_P_0_M_0): Likewise.
(VEX_W_0F16_P_0_M_1): Likewise.
(VEX_W_0F16_P_1): Likewise.
(VEX_W_0F16_P_2): Likewise.
(VEX_W_0F17_M_0): Likewise.
(VEX_W_0F28): Likewise.
(VEX_W_0F29): Likewise.
(VEX_W_0F2B_M_0): Likewise.
(VEX_W_0F2E_P_0): Likewise.
(VEX_W_0F2E_P_2): Likewise.
(VEX_W_0F2F_P_0): Likewise.
(VEX_W_0F2F_P_2): Likewise.
(VEX_W_0F50_M_0): Likewise.
(VEX_W_0F51_P_0): Likewise.
(VEX_W_0F51_P_1): Likewise.
(VEX_W_0F51_P_2): Likewise.
(VEX_W_0F51_P_3): Likewise.
(VEX_W_0F52_P_0): Likewise.
(VEX_W_0F52_P_1): Likewise.
(VEX_W_0F53_P_0): Likewise.
(VEX_W_0F53_P_1): Likewise.
(VEX_W_0F58_P_0): Likewise.
(VEX_W_0F58_P_1): Likewise.
(VEX_W_0F58_P_2): Likewise.
(VEX_W_0F58_P_3): Likewise.
(VEX_W_0F59_P_0): Likewise.
(VEX_W_0F59_P_1): Likewise.
(VEX_W_0F59_P_2): Likewise.
(VEX_W_0F59_P_3): Likewise.
(VEX_W_0F5A_P_0): Likewise.
(VEX_W_0F5A_P_1): Likewise.
(VEX_W_0F5A_P_3): Likewise.
(VEX_W_0F5B_P_0): Likewise.
(VEX_W_0F5B_P_1): Likewise.
(VEX_W_0F5B_P_2): Likewise.
(VEX_W_0F5C_P_0): Likewise.
(VEX_W_0F5C_P_1): Likewise.
(VEX_W_0F5C_P_2): Likewise.
(VEX_W_0F5C_P_3): Likewise.
(VEX_W_0F5D_P_0): Likewise.
(VEX_W_0F5D_P_1): Likewise.
(VEX_W_0F5D_P_2): Likewise.
(VEX_W_0F5D_P_3): Likewise.
(VEX_W_0F5E_P_0): Likewise.
(VEX_W_0F5E_P_1): Likewise.
(VEX_W_0F5E_P_2): Likewise.
(VEX_W_0F5E_P_3): Likewise.
(VEX_W_0F5F_P_0): Likewise.
(VEX_W_0F5F_P_1): Likewise.
(VEX_W_0F5F_P_2): Likewise.
(VEX_W_0F5F_P_3): Likewise.
(VEX_W_0F60_P_2): Likewise.
(VEX_W_0F61_P_2): Likewise.
(VEX_W_0F62_P_2): Likewise.
(VEX_W_0F63_P_2): Likewise.
(VEX_W_0F64_P_2): Likewise.
(VEX_W_0F65_P_2): Likewise.
(VEX_W_0F66_P_2): Likewise.
(VEX_W_0F67_P_2): Likewise.
(VEX_W_0F68_P_2): Likewise.
(VEX_W_0F69_P_2): Likewise.
(VEX_W_0F6A_P_2): Likewise.
(VEX_W_0F6B_P_2): Likewise.
(VEX_W_0F6C_P_2): Likewise.
(VEX_W_0F6D_P_2): Likewise.
(VEX_W_0F6F_P_1): Likewise.
(VEX_W_0F6F_P_2): Likewise.
(VEX_W_0F70_P_1): Likewise.
(VEX_W_0F70_P_2): Likewise.
(VEX_W_0F70_P_3): Likewise.
(VEX_W_0F71_R_2_P_2): Likewise.
(VEX_W_0F71_R_4_P_2): Likewise.
(VEX_W_0F71_R_6_P_2): Likewise.
(VEX_W_0F72_R_2_P_2): Likewise.
(VEX_W_0F72_R_4_P_2): Likewise.
(VEX_W_0F72_R_6_P_2): Likewise.
(VEX_W_0F73_R_2_P_2): Likewise.
(VEX_W_0F73_R_3_P_2): Likewise.
(VEX_W_0F73_R_6_P_2): Likewise.
(VEX_W_0F73_R_7_P_2): Likewise.
(VEX_W_0F74_P_2): Likewise.
(VEX_W_0F75_P_2): Likewise.
(VEX_W_0F76_P_2): Likewise.
(VEX_W_0F77_P_0): Likewise.
(VEX_W_0F7C_P_2): Likewise.
(VEX_W_0F7C_P_3): Likewise.
(VEX_W_0F7D_P_2): Likewise.
(VEX_W_0F7D_P_3): Likewise.
(VEX_W_0F7E_P_1): Likewise.
(VEX_W_0F7F_P_1): Likewise.
(VEX_W_0F7F_P_2): Likewise.
(VEX_W_0FAE_R_2_M_0): Likewise.
(VEX_W_0FAE_R_3_M_0): Likewise.
(VEX_W_0FC2_P_0): Likewise.
(VEX_W_0FC2_P_1): Likewise.
(VEX_W_0FC2_P_2): Likewise.
(VEX_W_0FC2_P_3): Likewise.
(VEX_W_0FD0_P_2): Likewise.
(VEX_W_0FD0_P_3): Likewise.
(VEX_W_0FD1_P_2): Likewise.
(VEX_W_0FD2_P_2): Likewise.
(VEX_W_0FD3_P_2): Likewise.
(VEX_W_0FD4_P_2): Likewise.
(VEX_W_0FD5_P_2): Likewise.
(VEX_W_0FD6_P_2): Likewise.
(VEX_W_0FD7_P_2_M_1): Likewise.
(VEX_W_0FD8_P_2): Likewise.
(VEX_W_0FD9_P_2): Likewise.
(VEX_W_0FDA_P_2): Likewise.
(VEX_W_0FDB_P_2): Likewise.
(VEX_W_0FDC_P_2): Likewise.
(VEX_W_0FDD_P_2): Likewise.
(VEX_W_0FDE_P_2): Likewise.
(VEX_W_0FDF_P_2): Likewise.
(VEX_W_0FE0_P_2): Likewise.
(VEX_W_0FE1_P_2): Likewise.
(VEX_W_0FE2_P_2): Likewise.
(VEX_W_0FE3_P_2): Likewise.
(VEX_W_0FE4_P_2): Likewise.
(VEX_W_0FE5_P_2): Likewise.
(VEX_W_0FE6_P_1): Likewise.
(VEX_W_0FE6_P_2): Likewise.
(VEX_W_0FE6_P_3): Likewise.
(VEX_W_0FE7_P_2_M_0): Likewise.
(VEX_W_0FE8_P_2): Likewise.
(VEX_W_0FE9_P_2): Likewise.
(VEX_W_0FEA_P_2): Likewise.
(VEX_W_0FEB_P_2): Likewise.
(VEX_W_0FEC_P_2): Likewise.
(VEX_W_0FED_P_2): Likewise.
(VEX_W_0FEE_P_2): Likewise.
(VEX_W_0FEF_P_2): Likewise.
(VEX_W_0FF0_P_3_M_0): Likewise.
(VEX_W_0FF1_P_2): Likewise.
(VEX_W_0FF2_P_2): Likewise.
(VEX_W_0FF3_P_2): Likewise.
(VEX_W_0FF4_P_2): Likewise.
(VEX_W_0FF5_P_2): Likewise.
(VEX_W_0FF6_P_2): Likewise.
(VEX_W_0FF7_P_2): Likewise.
(VEX_W_0FF8_P_2): Likewise.
(VEX_W_0FF9_P_2): Likewise.
(VEX_W_0FFA_P_2): Likewise.
(VEX_W_0FFB_P_2): Likewise.
(VEX_W_0FFC_P_2): Likewise.
(VEX_W_0FFD_P_2): Likewise.
(VEX_W_0FFE_P_2): Likewise.
(VEX_W_0F3800_P_2): Likewise.
(VEX_W_0F3801_P_2): Likewise.
(VEX_W_0F3802_P_2): Likewise.
(VEX_W_0F3803_P_2): Likewise.
(VEX_W_0F3804_P_2): Likewise.
(VEX_W_0F3805_P_2): Likewise.
(VEX_W_0F3806_P_2): Likewise.
(VEX_W_0F3807_P_2): Likewise.
(VEX_W_0F3808_P_2): Likewise.
(VEX_W_0F3809_P_2): Likewise.
(VEX_W_0F380A_P_2): Likewise.
(VEX_W_0F380B_P_2): Likewise.
(VEX_W_0F3817_P_2): Likewise.
(VEX_W_0F381C_P_2): Likewise.
(VEX_W_0F381D_P_2): Likewise.
(VEX_W_0F381E_P_2): Likewise.
(VEX_W_0F3820_P_2): Likewise.
(VEX_W_0F3821_P_2): Likewise.
(VEX_W_0F3822_P_2): Likewise.
(VEX_W_0F3823_P_2): Likewise.
(VEX_W_0F3824_P_2): Likewise.
(VEX_W_0F3825_P_2): Likewise.
(VEX_W_0F3828_P_2): Likewise.
(VEX_W_0F3829_P_2): Likewise.
(VEX_W_0F382A_P_2_M_0): Likewise.
(VEX_W_0F382B_P_2): Likewise.
(VEX_W_0F3830_P_2): Likewise.
(VEX_W_0F3831_P_2): Likewise.
(VEX_W_0F3832_P_2): Likewise.
(VEX_W_0F3833_P_2): Likewise.
(VEX_W_0F3834_P_2): Likewise.
(VEX_W_0F3835_P_2): Likewise.
(VEX_W_0F3837_P_2): Likewise.
(VEX_W_0F3838_P_2): Likewise.
(VEX_W_0F3839_P_2): Likewise.
(VEX_W_0F383A_P_2): Likewise.
(VEX_W_0F383B_P_2): Likewise.
(VEX_W_0F383C_P_2): Likewise.
(VEX_W_0F383D_P_2): Likewise.
(VEX_W_0F383E_P_2): Likewise.
(VEX_W_0F383F_P_2): Likewise.
(VEX_W_0F3840_P_2): Likewise.
(VEX_W_0F3841_P_2): Likewise.
(VEX_W_0F38DB_P_2): Likewise.
(VEX_W_0F3A08_P_2): Likewise.
(VEX_W_0F3A09_P_2): Likewise.
(VEX_W_0F3A0A_P_2): Likewise.
(VEX_W_0F3A0B_P_2): Likewise.
(VEX_W_0F3A0C_P_2): Likewise.
(VEX_W_0F3A0D_P_2): Likewise.
(VEX_W_0F3A0E_P_2): Likewise.
(VEX_W_0F3A0F_P_2): Likewise.
(VEX_W_0F3A21_P_2): Likewise.
(VEX_W_0F3A40_P_2): Likewise.
(VEX_W_0F3A41_P_2): Likewise.
(VEX_W_0F3A42_P_2): Likewise.
(VEX_W_0F3A62_P_2): Likewise.
(VEX_W_0F3A63_P_2): Likewise.
(VEX_W_0F3ADF_P_2): Likewise.
(VEX_LEN_0F77_P_0): New.
(prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
(vex_table): Update VEX 0F28 and 0F29 entries.
(vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
VEX_LEN_0F3A0B_P_2 entries.
(vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
VEX_W_0F3ADF_P_2 entries.
(mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
2018-09-18 00:23:03 +08:00
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2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (VZERO_Fixup): Removed.
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(VZERO): Likewise.
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(VEX_LEN_0F10_P_1): Likewise.
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(VEX_LEN_0F10_P_3): Likewise.
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(VEX_LEN_0F11_P_1): Likewise.
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(VEX_LEN_0F11_P_3): Likewise.
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(VEX_LEN_0F2E_P_0): Likewise.
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(VEX_LEN_0F2E_P_2): Likewise.
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(VEX_LEN_0F2F_P_0): Likewise.
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(VEX_LEN_0F2F_P_2): Likewise.
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(VEX_LEN_0F51_P_1): Likewise.
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(VEX_LEN_0F51_P_3): Likewise.
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(VEX_LEN_0F52_P_1): Likewise.
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(VEX_LEN_0F53_P_1): Likewise.
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(VEX_LEN_0F58_P_1): Likewise.
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(VEX_LEN_0F58_P_3): Likewise.
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(VEX_LEN_0F59_P_1): Likewise.
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(VEX_LEN_0F59_P_3): Likewise.
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(VEX_LEN_0F5A_P_1): Likewise.
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(VEX_LEN_0F5A_P_3): Likewise.
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(VEX_LEN_0F5C_P_1): Likewise.
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(VEX_LEN_0F5C_P_3): Likewise.
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(VEX_LEN_0F5D_P_1): Likewise.
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(VEX_LEN_0F5D_P_3): Likewise.
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(VEX_LEN_0F5E_P_1): Likewise.
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(VEX_LEN_0F5E_P_3): Likewise.
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(VEX_LEN_0F5F_P_1): Likewise.
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(VEX_LEN_0F5F_P_3): Likewise.
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(VEX_LEN_0FC2_P_1): Likewise.
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(VEX_LEN_0FC2_P_3): Likewise.
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(VEX_LEN_0F3A0A_P_2): Likewise.
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(VEX_LEN_0F3A0B_P_2): Likewise.
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(VEX_W_0F10_P_0): Likewise.
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(VEX_W_0F10_P_1): Likewise.
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(VEX_W_0F10_P_2): Likewise.
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(VEX_W_0F10_P_3): Likewise.
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(VEX_W_0F11_P_0): Likewise.
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(VEX_W_0F11_P_1): Likewise.
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(VEX_W_0F11_P_2): Likewise.
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(VEX_W_0F11_P_3): Likewise.
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(VEX_W_0F12_P_0_M_0): Likewise.
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(VEX_W_0F12_P_0_M_1): Likewise.
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(VEX_W_0F12_P_1): Likewise.
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(VEX_W_0F12_P_2): Likewise.
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(VEX_W_0F12_P_3): Likewise.
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(VEX_W_0F13_M_0): Likewise.
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(VEX_W_0F14): Likewise.
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(VEX_W_0F15): Likewise.
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(VEX_W_0F16_P_0_M_0): Likewise.
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(VEX_W_0F16_P_0_M_1): Likewise.
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(VEX_W_0F16_P_1): Likewise.
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(VEX_W_0F16_P_2): Likewise.
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(VEX_W_0F17_M_0): Likewise.
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(VEX_W_0F28): Likewise.
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(VEX_W_0F29): Likewise.
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(VEX_W_0F2B_M_0): Likewise.
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(VEX_W_0F2E_P_0): Likewise.
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(VEX_W_0F2E_P_2): Likewise.
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(VEX_W_0F2F_P_0): Likewise.
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(VEX_W_0F2F_P_2): Likewise.
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(VEX_W_0F50_M_0): Likewise.
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(VEX_W_0F51_P_0): Likewise.
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(VEX_W_0F51_P_1): Likewise.
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(VEX_W_0F51_P_2): Likewise.
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(VEX_W_0F51_P_3): Likewise.
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(VEX_W_0F52_P_0): Likewise.
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(VEX_W_0F52_P_1): Likewise.
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(VEX_W_0F53_P_0): Likewise.
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(VEX_W_0F53_P_1): Likewise.
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(VEX_W_0F58_P_0): Likewise.
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(VEX_W_0F58_P_1): Likewise.
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(VEX_W_0F58_P_2): Likewise.
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(VEX_W_0F58_P_3): Likewise.
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(VEX_W_0F59_P_0): Likewise.
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(VEX_W_0F59_P_1): Likewise.
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(VEX_W_0F59_P_2): Likewise.
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(VEX_W_0F59_P_3): Likewise.
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(VEX_W_0F5A_P_0): Likewise.
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(VEX_W_0F5A_P_1): Likewise.
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(VEX_W_0F5A_P_3): Likewise.
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(VEX_W_0F5B_P_0): Likewise.
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(VEX_W_0F5B_P_1): Likewise.
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(VEX_W_0F5B_P_2): Likewise.
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(VEX_W_0F5C_P_0): Likewise.
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(VEX_W_0F5C_P_1): Likewise.
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(VEX_W_0F5C_P_2): Likewise.
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(VEX_W_0F5C_P_3): Likewise.
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(VEX_W_0F5D_P_0): Likewise.
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(VEX_W_0F5D_P_1): Likewise.
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(VEX_W_0F5D_P_2): Likewise.
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(VEX_W_0F5D_P_3): Likewise.
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(VEX_W_0F5E_P_0): Likewise.
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(VEX_W_0F5E_P_1): Likewise.
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(VEX_W_0F5E_P_2): Likewise.
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(VEX_W_0F5E_P_3): Likewise.
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(VEX_W_0F5F_P_0): Likewise.
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(VEX_W_0F5F_P_1): Likewise.
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(VEX_W_0F5F_P_2): Likewise.
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(VEX_W_0F5F_P_3): Likewise.
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(VEX_W_0F60_P_2): Likewise.
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(VEX_W_0F61_P_2): Likewise.
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(VEX_W_0F62_P_2): Likewise.
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(VEX_W_0F63_P_2): Likewise.
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(VEX_W_0F64_P_2): Likewise.
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(VEX_W_0F65_P_2): Likewise.
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(VEX_W_0F66_P_2): Likewise.
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(VEX_W_0F67_P_2): Likewise.
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(VEX_W_0F68_P_2): Likewise.
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(VEX_W_0F69_P_2): Likewise.
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(VEX_W_0F6A_P_2): Likewise.
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(VEX_W_0F6B_P_2): Likewise.
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(VEX_W_0F6C_P_2): Likewise.
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(VEX_W_0F6D_P_2): Likewise.
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(VEX_W_0F6F_P_1): Likewise.
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(VEX_W_0F6F_P_2): Likewise.
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(VEX_W_0F70_P_1): Likewise.
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(VEX_W_0F70_P_2): Likewise.
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(VEX_W_0F70_P_3): Likewise.
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(VEX_W_0F71_R_2_P_2): Likewise.
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(VEX_W_0F71_R_4_P_2): Likewise.
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(VEX_W_0F71_R_6_P_2): Likewise.
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(VEX_W_0F72_R_2_P_2): Likewise.
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(VEX_W_0F72_R_4_P_2): Likewise.
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(VEX_W_0F72_R_6_P_2): Likewise.
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(VEX_W_0F73_R_2_P_2): Likewise.
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(VEX_W_0F73_R_3_P_2): Likewise.
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(VEX_W_0F73_R_6_P_2): Likewise.
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(VEX_W_0F73_R_7_P_2): Likewise.
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(VEX_W_0F74_P_2): Likewise.
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(VEX_W_0F75_P_2): Likewise.
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(VEX_W_0F76_P_2): Likewise.
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(VEX_W_0F77_P_0): Likewise.
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(VEX_W_0F7C_P_2): Likewise.
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(VEX_W_0F7C_P_3): Likewise.
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(VEX_W_0F7D_P_2): Likewise.
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(VEX_W_0F7D_P_3): Likewise.
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(VEX_W_0F7E_P_1): Likewise.
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(VEX_W_0F7F_P_1): Likewise.
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(VEX_W_0F7F_P_2): Likewise.
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(VEX_W_0FAE_R_2_M_0): Likewise.
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(VEX_W_0FAE_R_3_M_0): Likewise.
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(VEX_W_0FC2_P_0): Likewise.
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(VEX_W_0FC2_P_1): Likewise.
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(VEX_W_0FC2_P_2): Likewise.
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(VEX_W_0FC2_P_3): Likewise.
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(VEX_W_0FD0_P_2): Likewise.
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(VEX_W_0FD0_P_3): Likewise.
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(VEX_W_0FD1_P_2): Likewise.
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(VEX_W_0FD2_P_2): Likewise.
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(VEX_W_0FD3_P_2): Likewise.
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(VEX_W_0FD4_P_2): Likewise.
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(VEX_W_0FD5_P_2): Likewise.
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(VEX_W_0FD6_P_2): Likewise.
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(VEX_W_0FD7_P_2_M_1): Likewise.
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(VEX_W_0FD8_P_2): Likewise.
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(VEX_W_0FD9_P_2): Likewise.
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(VEX_W_0FDA_P_2): Likewise.
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(VEX_W_0FDB_P_2): Likewise.
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(VEX_W_0FDC_P_2): Likewise.
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(VEX_W_0FDD_P_2): Likewise.
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(VEX_W_0FDE_P_2): Likewise.
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(VEX_W_0FDF_P_2): Likewise.
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(VEX_W_0FE0_P_2): Likewise.
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(VEX_W_0FE1_P_2): Likewise.
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(VEX_W_0FE2_P_2): Likewise.
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(VEX_W_0FE3_P_2): Likewise.
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(VEX_W_0FE4_P_2): Likewise.
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(VEX_W_0FE5_P_2): Likewise.
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(VEX_W_0FE6_P_1): Likewise.
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(VEX_W_0FE6_P_2): Likewise.
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(VEX_W_0FE6_P_3): Likewise.
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(VEX_W_0FE7_P_2_M_0): Likewise.
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(VEX_W_0FE8_P_2): Likewise.
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(VEX_W_0FE9_P_2): Likewise.
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(VEX_W_0FEA_P_2): Likewise.
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(VEX_W_0FEB_P_2): Likewise.
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(VEX_W_0FEC_P_2): Likewise.
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(VEX_W_0FED_P_2): Likewise.
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(VEX_W_0FEE_P_2): Likewise.
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(VEX_W_0FEF_P_2): Likewise.
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(VEX_W_0FF0_P_3_M_0): Likewise.
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(VEX_W_0FF1_P_2): Likewise.
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(VEX_W_0FF2_P_2): Likewise.
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(VEX_W_0FF3_P_2): Likewise.
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(VEX_W_0FF4_P_2): Likewise.
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(VEX_W_0FF5_P_2): Likewise.
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(VEX_W_0FF6_P_2): Likewise.
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(VEX_W_0FF7_P_2): Likewise.
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(VEX_W_0FF8_P_2): Likewise.
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(VEX_W_0FF9_P_2): Likewise.
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(VEX_W_0FFA_P_2): Likewise.
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(VEX_W_0FFB_P_2): Likewise.
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(VEX_W_0FFC_P_2): Likewise.
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(VEX_W_0FFD_P_2): Likewise.
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(VEX_W_0FFE_P_2): Likewise.
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(VEX_W_0F3800_P_2): Likewise.
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(VEX_W_0F3801_P_2): Likewise.
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(VEX_W_0F3802_P_2): Likewise.
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(VEX_W_0F3803_P_2): Likewise.
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(VEX_W_0F3804_P_2): Likewise.
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(VEX_W_0F3805_P_2): Likewise.
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(VEX_W_0F3806_P_2): Likewise.
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(VEX_W_0F3807_P_2): Likewise.
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(VEX_W_0F3808_P_2): Likewise.
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(VEX_W_0F3809_P_2): Likewise.
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(VEX_W_0F380A_P_2): Likewise.
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(VEX_W_0F380B_P_2): Likewise.
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(VEX_W_0F3817_P_2): Likewise.
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(VEX_W_0F381C_P_2): Likewise.
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(VEX_W_0F381D_P_2): Likewise.
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(VEX_W_0F381E_P_2): Likewise.
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(VEX_W_0F3820_P_2): Likewise.
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|
|
|
(VEX_W_0F3821_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3822_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3823_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3824_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3825_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3828_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3829_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F382A_P_2_M_0): Likewise.
|
|
|
|
|
|
(VEX_W_0F382B_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3830_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3831_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3832_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3833_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3834_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3835_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3837_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3838_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3839_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383A_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383B_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383C_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383D_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383E_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F383F_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3840_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3841_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F38DB_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A08_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A09_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0A_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0B_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0C_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0D_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0E_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A0F_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A21_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A40_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A41_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A42_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A62_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3A63_P_2): Likewise.
|
|
|
|
|
|
(VEX_W_0F3ADF_P_2): Likewise.
|
|
|
|
|
|
(VEX_LEN_0F77_P_0): New.
|
|
|
|
|
|
(prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
|
|
|
|
|
|
PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
|
|
|
|
|
|
PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
|
|
|
|
|
|
PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
|
|
|
|
|
|
PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
|
|
|
|
|
|
PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
|
|
|
|
|
|
PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
|
|
|
|
|
|
PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
|
|
|
|
|
|
PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
|
|
|
|
|
|
PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
|
|
|
|
|
|
PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
|
|
|
|
|
|
PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
|
|
|
|
|
|
PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
|
|
|
|
|
|
PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
|
|
|
|
|
|
PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
|
|
|
|
|
|
PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
|
|
|
|
|
|
PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
|
|
|
|
|
|
PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
|
|
|
|
|
|
PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
|
|
|
|
|
|
PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
|
|
|
|
|
|
PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
|
|
|
|
|
|
PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
|
|
|
|
|
|
PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
|
|
|
|
|
|
PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
|
|
|
|
|
|
PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
|
|
|
|
|
|
PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
|
|
|
|
|
|
PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
|
|
|
|
|
|
PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
|
|
|
|
|
|
PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
|
|
|
|
|
|
PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
|
|
|
|
|
|
PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
|
|
|
|
|
|
PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
|
|
|
|
|
|
PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
|
|
|
|
|
|
PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
|
|
|
|
|
|
PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
|
|
|
|
|
|
PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
|
|
|
|
|
|
PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
|
|
|
|
|
|
PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
|
|
|
|
|
|
PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
|
|
|
|
|
|
PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
|
|
|
|
|
|
PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
|
|
|
|
|
|
PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
|
|
|
|
|
|
PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
|
|
|
|
|
|
PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
|
|
|
|
|
|
PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
|
|
|
|
|
|
PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
|
|
|
|
|
|
PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
|
|
|
|
|
|
PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
|
|
|
|
|
|
PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
|
|
|
|
|
|
(vex_table): Update VEX 0F28 and 0F29 entries.
|
|
|
|
|
|
(vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
|
|
|
|
|
|
VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
|
|
|
|
|
|
VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
|
|
|
|
|
|
VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
|
|
|
|
|
|
VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
|
|
|
|
|
|
VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
|
|
|
|
|
|
VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
|
|
|
|
|
|
VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
|
|
|
|
|
|
VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
|
|
|
|
|
|
VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
|
|
|
|
|
|
VEX_LEN_0F3A0B_P_2 entries.
|
|
|
|
|
|
(vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
|
|
|
|
|
|
VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
|
|
|
|
|
|
VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
|
|
|
|
|
|
VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
|
|
|
|
|
|
VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
|
|
|
|
|
|
VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
|
|
|
|
|
|
VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
|
|
|
|
|
|
VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
|
|
|
|
|
|
VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
|
|
|
|
|
|
VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
|
|
|
|
|
|
VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
|
|
|
|
|
|
VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
|
|
|
|
|
|
VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
|
|
|
|
|
|
VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
|
|
|
|
|
|
VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
|
|
|
|
|
|
VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
|
|
|
|
|
|
VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
|
|
|
|
|
|
VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
|
|
|
|
|
|
VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
|
|
|
|
|
|
VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
|
|
|
|
|
|
VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
|
|
|
|
|
|
VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
|
|
|
|
|
|
VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
|
|
|
|
|
|
VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
|
|
|
|
|
|
VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
|
|
|
|
|
|
VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
|
|
|
|
|
|
VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
|
|
|
|
|
|
VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
|
|
|
|
|
|
VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
|
|
|
|
|
|
VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
|
|
|
|
|
|
VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
|
|
|
|
|
|
VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
|
|
|
|
|
|
VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
|
|
|
|
|
|
VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
|
|
|
|
|
|
VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
|
|
|
|
|
|
VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
|
|
|
|
|
|
VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
|
|
|
|
|
|
VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
|
|
|
|
|
|
VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
|
|
|
|
|
|
VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
|
|
|
|
|
|
VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
|
|
|
|
|
|
VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
|
|
|
|
|
|
VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
|
|
|
|
|
|
VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
|
|
|
|
|
|
VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
|
|
|
|
|
|
VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
|
|
|
|
|
|
VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
|
|
|
|
|
|
VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
|
|
|
|
|
|
VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
|
|
|
|
|
|
VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
|
|
|
|
|
|
VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
|
|
|
|
|
|
VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
|
|
|
|
|
|
VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
|
|
|
|
|
|
VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
|
|
|
|
|
|
VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
|
|
|
|
|
|
VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
|
|
|
|
|
|
VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
|
|
|
|
|
|
VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
|
|
|
|
|
|
VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
|
|
|
|
|
|
VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
|
|
|
|
|
|
VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
|
|
|
|
|
|
VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
|
|
|
|
|
|
VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
|
|
|
|
|
|
VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
|
|
|
|
|
|
VEX_W_0F3ADF_P_2 entries.
|
|
|
|
|
|
(mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
|
|
|
|
|
|
MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
|
|
|
|
|
|
MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
|
|
|
|
|
|
|
2018-09-17 21:11:54 +08:00
|
|
|
|
2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (VexWIG): New.
|
|
|
|
|
|
Replace VexW=3 with VexWIG.
|
|
|
|
|
|
|
2018-09-16 08:09:08 +08:00
|
|
|
|
2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-09-16 05:50:40 +08:00
|
|
|
|
2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/23665
|
|
|
|
|
|
* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
|
|
|
|
|
|
VEX_LEN_0FD6_P_2 entries.
|
|
|
|
|
|
* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-09-15 03:19:58 +08:00
|
|
|
|
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/23642
|
|
|
|
|
|
* i386-opc.h (VEXWIG): New.
|
|
|
|
|
|
* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-09-15 02:25:01 +08:00
|
|
|
|
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23655
|
|
|
|
|
|
* i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
|
|
|
|
|
|
vcvtsi2sd%LQ and vcvtusi2sd%LQ.
|
|
|
|
|
|
* i386-dis.c (EXxEVexR64): New.
|
|
|
|
|
|
(evex_rounding_64_mode): Likewise.
|
|
|
|
|
|
(OP_Rounding): Handle evex_rounding_64_mode.
|
|
|
|
|
|
|
2018-09-15 01:49:43 +08:00
|
|
|
|
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23655
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Replace Eq with Edqa for
|
|
|
|
|
|
vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
|
|
|
|
|
|
* i386-dis.c (Edqa): New.
|
|
|
|
|
|
(dqa_mode): Likewise.
|
|
|
|
|
|
(intel_operand_size): Handle dqa_mode as m_mode.
|
|
|
|
|
|
(OP_E_register): Handle dqa_mode as dq_mode.
|
|
|
|
|
|
(OP_E_memory): Set shift for dqa_mode based on address_mode.
|
|
|
|
|
|
|
2018-09-14 21:51:29 +08:00
|
|
|
|
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E_memory): Reformat.
|
|
|
|
|
|
|
2018-09-14 17:21:15 +08:00
|
|
|
|
2018-09-14 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (crc32): Fold byte and word forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
i386: Update VexW field for VEX instructions
1. Mark VEX.W0 VEX instructions with VexW=1.
2. Mark VEX.W1 VEX instructions with VexW=2.
3. Remove VexW=1 from WIG VEX instructions.
* i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
Add VexW=2 to VEX.W1 VEX movd, movq, pextrq, pinsrq, vmod, vmovq,
vpextrq and vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
* i386-tbl.h: Regenerated.
2018-09-13 06:12:59 +08:00
|
|
|
|
2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
|
|
|
|
|
|
pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
|
|
|
|
|
|
Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
|
|
|
|
|
|
vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-09-13 17:26:06 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
(invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
|
|
|
|
|
|
xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
|
|
|
|
|
|
rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:25:30 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
|
|
|
|
|
|
AVX512_4VNNIW insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:24:53 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:24:23 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:23:50 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:23:17 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:22:49 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:22:03 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SHA insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:21:36 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:19:21 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:18:52 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AVX insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:16:49 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from GNFI insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:16:19 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:15:38 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:15:01 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:14:32 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:12:51 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
|
|
|
|
|
|
meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:12:23 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:11:55 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:11:26 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:08:37 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
|
|
|
|
|
|
(vpbroadcastw, rdpid): Drop NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:07:55 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vmovsd, vmovss): Fold register form load and
|
|
|
|
|
|
store templates, adding D.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:07:07 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
|
|
|
|
|
|
movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
|
|
|
|
|
|
movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
|
|
|
|
|
|
vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
|
|
|
|
|
|
vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
|
|
|
|
|
|
Fold load and store templates where possible, adding D. Drop
|
|
|
|
|
|
IgnoreSize where it was pointlessly present. Drop redundant
|
|
|
|
|
|
*word.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-09-13 17:03:35 +08:00
|
|
|
|
2018-09-13 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Mv_bnd, v_bndmk_mode): New.
|
|
|
|
|
|
(mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
|
|
|
|
|
|
(intel_operand_size): Handle v_bndmk_mode.
|
|
|
|
|
|
(OP_E_memory): Likewise. Produce (bad) when also riprel.
|
|
|
|
|
|
|
2018-09-08 12:59:09 +08:00
|
|
|
|
2018-09-08 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (ARCH_s12z): Define if ARCH_all.
|
|
|
|
|
|
|
2018-09-01 03:23:05 +08:00
|
|
|
|
2018-08-31 Kito Cheng <kito@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
|
|
|
|
|
|
compressed floating point instructions.
|
|
|
|
|
|
|
2018-08-31 04:23:12 +08:00
|
|
|
|
2018-08-30 Kito Cheng <kito@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
|
|
|
|
|
|
riscv_opcode.xlen_requirement.
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Update for struct change.
|
|
|
|
|
|
|
2018-08-30 02:52:28 +08:00
|
|
|
|
2018-08-29 Martin Aberg <maberg@gaisler.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes): Add Leon specific partial write
|
|
|
|
|
|
psr (PWRPSR) instruction.
|
|
|
|
|
|
|
2018-08-29 20:55:25 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
|
|
|
|
|
|
|
2018-08-29 20:36:23 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
|
|
|
|
|
|
|
2018-08-29 20:13:00 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
|
|
|
|
|
|
loongson3a as an alias of gs464 for compatibility.
|
|
|
|
|
|
* mips-opc.c (mips_opcodes): Change Comments.
|
|
|
|
|
|
|
2018-08-29 20:08:58 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
|
|
|
|
|
|
option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -M loongson-ext.
|
|
|
|
|
|
* mips-opc.c (LEXT2): New macro.
|
|
|
|
|
|
(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
|
|
|
|
|
|
|
2018-08-29 19:57:39 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add EXT to loongson3a
|
|
|
|
|
|
descriptors.
|
|
|
|
|
|
(parse_mips_ase_option): Handle -M loongson-ext option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -M loongson-ext.
|
|
|
|
|
|
* mips-opc.c (IL3A): Delete.
|
|
|
|
|
|
* mips-opc.c (LEXT): New macro.
|
|
|
|
|
|
(mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2018-08-29 17:39:33 +08:00
|
|
|
|
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
|
|
|
|
|
|
descriptors.
|
|
|
|
|
|
(parse_mips_ase_option): Handle -M loongson-cam option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -M loongson-cam.
|
|
|
|
|
|
* mips-opc.c (LCAM): New macro.
|
|
|
|
|
|
(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
Use operand->extract to provide defaults for optional PowerPC operands
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
2018-08-16 14:44:12 +08:00
|
|
|
|
2018-08-21 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (operand_value_powerpc): Init "invalid".
|
|
|
|
|
|
(skip_optional_operands): Count optional operands, and update
|
|
|
|
|
|
ppc_optional_operand_value call.
|
|
|
|
|
|
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
|
|
|
|
|
|
(extract_vlensi): Likewise.
|
|
|
|
|
|
(extract_fxm): Return default value for missing optional operand.
|
|
|
|
|
|
(extract_ls, extract_raq, extract_tbr): Likewise.
|
|
|
|
|
|
(insert_sxl, extract_sxl): New functions.
|
|
|
|
|
|
(insert_esync, extract_esync): Remove Power9 handling and simplify.
|
|
|
|
|
|
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
|
|
|
|
|
|
flag and extra entry.
|
|
|
|
|
|
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
|
|
|
|
|
|
extract_sxl.
|
|
|
|
|
|
|
2018-08-20 07:52:28 +08:00
|
|
|
|
2018-08-20 Alan Modra <amodra@gmail.com>
|
2018-07-24 19:40:21 +08:00
|
|
|
|
|
2018-08-20 07:52:28 +08:00
|
|
|
|
* sh-opc.h (MASK): Simplify.
|
2018-07-24 19:40:21 +08:00
|
|
|
|
|
2018-08-20 16:46:34 +08:00
|
|
|
|
2018-08-18 John Darrington <john@darrington.wattle.id.au>
|
2018-07-11 16:42:01 +08:00
|
|
|
|
|
2018-08-20 07:52:28 +08:00
|
|
|
|
* s12z-dis.c (bm_decode): Deal with cases where the mode is
|
|
|
|
|
|
BM_RESERVED0 or BM_RESERVED1
|
2018-08-20 16:46:34 +08:00
|
|
|
|
(bm_rel_decode, bm_n_bytes): Ditto.
|
2018-08-20 07:52:28 +08:00
|
|
|
|
|
2018-08-20 16:46:34 +08:00
|
|
|
|
2018-08-18 John Darrington <john@darrington.wattle.id.au>
|
2018-08-20 07:52:28 +08:00
|
|
|
|
|
|
|
|
|
|
* s12z.h: Delete.
|
2018-07-11 16:42:01 +08:00
|
|
|
|
|
2018-08-15 00:55:43 +08:00
|
|
|
|
2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
|
|
|
|
|
|
address with the addr32 prefix and without base nor index
|
|
|
|
|
|
registers.
|
|
|
|
|
|
|
2018-08-12 05:37:14 +08:00
|
|
|
|
2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
|
|
|
|
|
|
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
|
|
|
|
|
|
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuCMOV and CpuFXSR.
|
|
|
|
|
|
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
|
|
|
|
|
|
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-08-06 21:41:32 +08:00
|
|
|
|
2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h: Update auxiliary registers.
|
|
|
|
|
|
|
2018-08-06 14:34:36 +08:00
|
|
|
|
2018-08-06 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
|
|
|
|
|
|
(RegIP, RegIZ): Define.
|
|
|
|
|
|
* i386-reg.tbl: Adjust comments.
|
|
|
|
|
|
(rip): Use Qword instead of BaseIndex. Use RegIP.
|
|
|
|
|
|
(eip): Use Dword instead of BaseIndex. Use RegIP.
|
|
|
|
|
|
(riz): Add Qword. Use RegIZ.
|
|
|
|
|
|
(eiz): Add Dword. Use RegIZ.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-03 15:30:58 +08:00
|
|
|
|
2018-08-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
|
|
|
|
|
|
pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
|
|
|
|
|
|
vpmovzxdq, vpmovzxwd): Remove NoRex64.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-03 15:30:02 +08:00
|
|
|
|
2018-08-03 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_types): Remove Mem field.
|
|
|
|
|
|
* i386-opc.h (union i386_operand_type): Remove mem field.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-08-01 09:02:56 +08:00
|
|
|
|
2018-08-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-08-01 00:49:53 +08:00
|
|
|
|
2018-07-31 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2018-07-31 16:58:05 +08:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-31 16:57:09 +08:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (ZEROING_MASKING) Rename to ...
|
|
|
|
|
|
(DYNAMIC_MASKING): ... this. Adjust comment.
|
|
|
|
|
|
* i386-opc.tbl (MaskingMorZ): Define.
|
|
|
|
|
|
(vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
|
|
|
|
|
|
vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
|
|
|
|
|
|
vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
|
|
|
|
|
|
vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
|
|
|
|
|
|
vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
|
|
|
|
|
|
vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
|
|
|
|
|
|
vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
|
|
|
|
|
|
vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
|
|
|
|
|
|
|
2018-07-31 16:55:17 +08:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Use element rather than vector size for AVX512*
|
|
|
|
|
|
scatter/gather insns.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-31 16:52:37 +08:00
|
|
|
|
2018-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
|
|
|
|
|
|
(cpu_flags): Drop CpuVREX.
|
|
|
|
|
|
* i386-opc.h (CpuVREX): Delete.
|
|
|
|
|
|
(union i386_cpu_flags): Remove cpuvrex.
|
|
|
|
|
|
* i386-init.h, i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-31 04:55:41 +08:00
|
|
|
|
2018-07-30 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
|
|
|
|
|
|
fields.
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
|
|
|
|
|
|
|
Add support for the C_SKY series of processors.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
2018-07-30 19:24:14 +08:00
|
|
|
|
2018-07-30 Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.ac: Add C-SKY.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* csky-dis.c: New file.
|
|
|
|
|
|
* csky-opc.h: New file.
|
|
|
|
|
|
* disassemble.c (ARCH_csky): Define.
|
|
|
|
|
|
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
|
|
|
|
|
|
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
|
|
|
|
|
|
|
2018-07-27 06:49:45 +08:00
|
|
|
|
2018-07-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (insert_sprbat): Correct function parameter and
|
|
|
|
|
|
return type.
|
|
|
|
|
|
(extract_sprbat): Likewise, variable too.
|
|
|
|
|
|
|
2018-07-24 07:51:44 +08:00
|
|
|
|
2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
|
|
|
|
|
|
Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
|
|
|
|
|
|
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
|
|
|
|
|
|
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
|
|
|
|
|
|
support disjointed BAT.
|
|
|
|
|
|
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
|
|
|
|
|
|
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
|
|
|
|
|
|
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
|
|
|
|
|
|
|
2018-07-26 06:28:07 +08:00
|
|
|
|
2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (adjust_broadcast_modifier): New function.
|
|
|
|
|
|
(process_i386_opcode_modifier): Add an argument for operands.
|
|
|
|
|
|
Adjust the Broadcast value based on operands.
|
|
|
|
|
|
(output_i386_opcode): Pass operand_types to
|
|
|
|
|
|
process_i386_opcode_modifier.
|
|
|
|
|
|
(process_i386_opcodes): Pass NULL as operands to
|
|
|
|
|
|
process_i386_opcode_modifier.
|
|
|
|
|
|
* i386-opc.h (BYTE_BROADCAST): New.
|
|
|
|
|
|
(WORD_BROADCAST): Likewise.
|
|
|
|
|
|
(DWORD_BROADCAST): Likewise.
|
|
|
|
|
|
(QWORD_BROADCAST): Likewise.
|
|
|
|
|
|
(i386_opcode_modifier): Expand broadcast to 3 bits.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-07-24 15:05:52 +08:00
|
|
|
|
2018-07-24 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 23430
|
|
|
|
|
|
* or1k-desc.h: Regenerate.
|
|
|
|
|
|
|
2018-07-24 15:46:27 +08:00
|
|
|
|
2018-07-24 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
|
|
|
|
|
|
vcvtusi2ss, and vcvtusi2sd.
|
|
|
|
|
|
* i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
|
|
|
|
|
|
Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-23 17:09:43 +08:00
|
|
|
|
2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (extract_w6): Fix extending the sign.
|
|
|
|
|
|
|
2018-07-23 17:09:43 +08:00
|
|
|
|
2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-tbl.h (vewt): Allow it for ARC EM family.
|
|
|
|
|
|
|
2018-07-23 11:29:23 +08:00
|
|
|
|
2018-07-23 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 23419
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
|
|
|
|
|
|
opcode variants for mtspr/mfspr encodings.
|
|
|
|
|
|
|
2018-07-20 20:21:33 +08:00
|
|
|
|
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
|
|
|
|
|
|
loongson3a descriptors.
|
|
|
|
|
|
(parse_mips_ase_option): Handle -M loongson-mmi option.
|
|
|
|
|
|
(print_mips_disassembler_options): Document -M loongson-mmi.
|
|
|
|
|
|
* mips-opc.c (LMMI): New macro.
|
|
|
|
|
|
(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2018-07-19 14:36:19 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
|
|
|
|
|
|
vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
|
|
|
|
|
|
IgnoreSize and [XYZ]MMword where applicable.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:35:38 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
|
|
|
|
|
|
(vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
|
|
|
|
|
|
(vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
|
|
|
|
|
|
(vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:34:45 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
|
|
|
|
|
|
AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
|
|
|
|
|
|
VPCLMULQDQ templates into their respective AVX512VL counterparts
|
|
|
|
|
|
where possible, using Disp8ShiftVL and CheckRegSize instead of
|
|
|
|
|
|
Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:34:01 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512DQ templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:32:17 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512BW templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:31:24 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold AVX512CD templates into their respective
|
|
|
|
|
|
AVX512VL counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:29:35 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (DISP8_SHIFT_VL): New.
|
|
|
|
|
|
* i386-opc.tbl (Disp8ShiftVL): Define.
|
|
|
|
|
|
(various): Fold AVX512VL templates into their respective
|
|
|
|
|
|
AVX512F counterparts where possible, using Disp8ShiftVL and
|
|
|
|
|
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
|
|
|
|
|
IgnoreSize) as appropriate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-19 14:28:29 +08:00
|
|
|
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Change dependencies and rule for
|
|
|
|
|
|
$(srcdir)/i386-init.h.
|
|
|
|
|
|
* Makefile.in: Re-generate.
|
|
|
|
|
|
* i386-gen.c (process_i386_opcodes): New local variable
|
|
|
|
|
|
"marker". Drop opening of input file. Recognize marker and line
|
|
|
|
|
|
number directives.
|
|
|
|
|
|
* i386-opc.tbl (OPCODE_I386_H): Define.
|
|
|
|
|
|
(i386-opc.h): Include it.
|
|
|
|
|
|
(None): Undefine.
|
|
|
|
|
|
|
x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
After
commit 1b54b8d7e4fc8055f9220a5287e8a94d8a65a88d
Author: Jan Beulich <jbeulich@novell.com>
Date: Mon Dec 18 09:36:14 2017 +0100
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these
RegXMM|...|Xmmword|...
and
RegXMM|...
The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.
gas/
PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.
opcodes/
PR gas/23418
* i386-opc.h (Byte): Update comments.
(Word): Likewise.
(Dword): Likewise.
(Fword): Likewise.
(Qword): Likewise.
(Tbyte): Likewise.
(Xmmword): Likewise.
(Ymmword): Likewise.
(Zmmword): Likewise.
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
vcvttps2uqq.
* i386-tbl.h: Regenerated.
2018-07-18 20:33:36 +08:00
|
|
|
|
2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/23418
|
|
|
|
|
|
* i386-opc.h (Byte): Update comments.
|
|
|
|
|
|
(Word): Likewise.
|
|
|
|
|
|
(Dword): Likewise.
|
|
|
|
|
|
(Fword): Likewise.
|
|
|
|
|
|
(Qword): Likewise.
|
|
|
|
|
|
(Tbyte): Likewise.
|
|
|
|
|
|
(Xmmword): Likewise.
|
|
|
|
|
|
(Ymmword): Likewise.
|
|
|
|
|
|
(Zmmword): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
|
|
|
|
|
|
vcvttps2uqq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-07-12 22:46:17 +08:00
|
|
|
|
2018-07-12 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add entry for
|
|
|
|
|
|
ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
Add remainder of Em16 restrictions for AArch64 gas.
This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.
The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.
The list has been cross checked (by hand) through the Arm ARM version Ca.
opcodes/
PR binutils/23192
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
sqdmulh, sqrdmulh): Use Em16.
gas/
PR binutils/23192
* testsuite/gas/aarch64/illegal-by-element.s: New.
* testsuite/gas/aarch64/illegal-by-element.d: New.
* testsuite/gas/aarch64/illegal-by-element.l: New.
2018-07-12 17:28:46 +08:00
|
|
|
|
2018-07-12 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23192
|
|
|
|
|
|
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
|
|
|
|
|
|
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
|
|
|
|
|
|
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
|
|
|
|
|
|
sqdmulh, sqrdmulh): Use Em16.
|
|
|
|
|
|
|
2018-07-12 01:05:34 +08:00
|
|
|
|
2018-07-11 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
|
|
|
|
|
|
csdb together with them.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2018-07-11 16:30:00 +08:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (monitor, monitorx): Add 64-bit template
|
|
|
|
|
|
requiring 32-bit registers as operands 2 and 3. Improve
|
|
|
|
|
|
comments.
|
|
|
|
|
|
(mwait, mwaitx): Fold templates. Improve comments.
|
|
|
|
|
|
OPERAND_TYPE_INOUTPORTREG.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-07-11 16:28:56 +08:00
|
|
|
|
2018-07-11 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Remove
|
|
|
|
|
|
OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
|
|
|
|
|
|
OPERAND_TYPE_INOUTPORTREG.
|
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|
|
* i386-init.h: Re-generate.
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2018-07-11 16:25:40 +08:00
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2018-07-11 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (wrssd, wrussd): Add Dword.
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(wrssq, wrussq): Add Qword.
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* i386-tbl.h: Re-generate.
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2018-07-11 16:24:44 +08:00
|
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|
2018-07-11 Jan Beulich <jbeulich@suse.com>
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* i386-opc.h: Rename OTMax to OTNum.
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(OTNumOfUints): Adjust calculation.
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(OTUnused): Directly alias to OTNum.
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2018-07-09 22:50:57 +08:00
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2018-07-09 Maciej W. Rozycki <macro@mips.com>
|
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* s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
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`reg_xys'.
|
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(lea_reg_xys): Likewise.
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(print_insn_loop_primitive): Rename `reg' local variable to
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`reg_dxy'.
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2018-07-06 23:18:19 +08:00
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|
2018-07-06 Tamar Christina <tamar.christina@arm.com>
|
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|
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PR binutils/23242
|
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* aarch64-tbl.h (ldarh): Fix disassembly mask.
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|
2018-07-06 23:15:41 +08:00
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|
2018-07-06 Tamar Christina <tamar.christina@arm.com>
|
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PR binutils/23369
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* aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
|
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|
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
|
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GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 06:57:21 +08:00
|
|
|
|
2018-07-02 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR tdep/8282
|
|
|
|
|
|
* mips-dis.c (mips_option_arg_t): New enumeration.
|
|
|
|
|
|
(mips_options): New variable.
|
|
|
|
|
|
(disassembler_options_mips): New function.
|
|
|
|
|
|
(print_mips_disassembler_options): Reimplement in terms of
|
|
|
|
|
|
`disassembler_options_mips'.
|
|
|
|
|
|
* arm-dis.c (disassembler_options_arm): Adapt to using the
|
|
|
|
|
|
`disasm_options_and_args_t' structure.
|
|
|
|
|
|
* ppc-dis.c (disassembler_options_powerpc): Likewise.
|
|
|
|
|
|
* s390-dis.c (disassembler_options_s390): Likewise.
|
|
|
|
|
|
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 18:22:20 +08:00
|
|
|
|
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
|
|
|
|
|
|
expected result.
|
|
|
|
|
|
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
|
|
|
|
|
|
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
|
|
|
|
|
|
* testsuite/ld-arm/tls-longplt.d: Likewise.
|
|
|
|
|
|
|
Fix AArch64 encodings for by element instructions.
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.
e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.
Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.
This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
Also the patch updates all instructions that should be affected by this.
opcodes/
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
gas/
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
include/
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-29 19:12:27 +08:00
|
|
|
|
2018-06-29 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23192
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p,
|
|
|
|
|
|
aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
|
|
|
|
|
|
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
|
|
|
|
|
|
fmlal2, fmlsl2.
|
|
|
|
|
|
(AARCH64_OPERANDS): Add Em2.
|
|
|
|
|
|
|
2018-06-26 21:03:16 +08:00
|
|
|
|
2018-06-26 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-06-26 19:56:23 +08:00
|
|
|
|
2018-06-26 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nfp-dis.c: Fix spelling mistake.
|
|
|
|
|
|
|
2018-06-25 02:13:01 +08:00
|
|
|
|
2018-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2018-06-25 01:36:15 +08:00
|
|
|
|
2018-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.31 branch created.
|
|
|
|
|
|
|
2018-06-22 19:27:53 +08:00
|
|
|
|
2018-06-19 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
|
2018-06-22 05:45:47 +08:00
|
|
|
|
2018-06-21 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (print_mips_disassembler_options): Fix a typo in
|
|
|
|
|
|
`-M ginv' option description.
|
|
|
|
|
|
|
2018-06-19 13:12:48 +08:00
|
|
|
|
2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/23305
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
|
|
|
|
|
|
la and lla.
|
|
|
|
|
|
|
Bump to autoconf 2.69 and automake 1.15.1
When trying to run the update-gnulib.sh script in gdb, I get this:
Error: Wrong automake version (Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\${ <-- HERE ([^ =:+{}]+)}/ at /opt/automake/1.11.1/bin/automake line 4113.), we need 1.11.1.
Aborting.
Apparently, it's an issue with a regex in automake that triggers a
warning starting with Perl 5.22. It has been fixed in automake 1.15.1.
So I think it's a good excuse to bump the versions of autoconf and
automake used in the gnulib import. And to avoid requiring multiple
builds of autoconf/automake, it was suggested that we bump the required
version of those tools for all binutils-gdb.
For autoconf, the 2.69 version is universally available, so it's an easy
choice. For automake, different distros and distro versions have
different automake versions. But 1.15.1 seems to be the most readily
available as a package. In any case, it's easy to build it from source.
I removed the version checks from AUTOMAKE_OPTIONS and AC_PREREQ,
because I don't think they are useful in our case. They only specify a
lower bound for the acceptable version of automake/autoconf. That's
useful if you let the user choose the version of the tool they want to
use, but want to set a minimum version (because you use a feature that
was introduced in that version). In our case, we force people to use a
specific version anyway. For the autoconf version, we have the check in
config/override.m4 that enforces the version we want. It will be one
less thing to update next time we change autotools version.
I hit a few categories of problems that required some changes. They are
described below along with the chosen solutions.
Problem 1:
configure.ac:17: warning: AM_INIT_AUTOMAKE: two- and three-arguments forms are deprecated. For more info, see:
configure.ac:17: http://www.gnu.org/software/automake/manual/automake.html#Modernize-AM_005fINIT_005fAUTOMAKE-invocation
Solution 1:
Adjust the code based on the example at that URL.
Problem 2 (in zlib/):
Makefile.am: error: required file './INSTALL' not found
Makefile.am: 'automake --add-missing' can install 'INSTALL'
Makefile.am: error: required file './NEWS' not found
Makefile.am: error: required file './AUTHORS' not found
Makefile.am: error: required file './COPYING' not found
Makefile.am: 'automake --add-missing' can install 'COPYING'
Solution 2:
Add the foreign option to AUTOMAKE_OPTIONS.
Problem 3:
doc/Makefile.am:20: error: support for Cygnus-style trees has been removed
Solution 3:
Remove the cygnus options.
Problem 4:
Makefile.am:656: warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Solution 4:
Rename "INCLUDES = " to "AM_CPPFLAGS += " (because AM_CPPFLAGS is
already defined earlier).
Problem 5:
doc/Makefile.am:71: warning: suffix '.texinfo' for Texinfo files is discouraged; use '.texi' instead
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 5:
Rename .texinfo files to .texi.
Problem 6:
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 6:
Remove the hack at the bottom of doc/Makefile.am and use
the info-in-builddir automake option.
Problem 7:
doc/Makefile.am:35: error: required file '../texinfo.tex' not found
doc/Makefile.am:35: 'automake --add-missing' can install 'texinfo.tex'
Solution 7:
Use the no-texinfo.tex automake option. We also have one in
texinfo/texinfo.tex, not sure if we should point to that, or move it
(or a newer version of it added with automake --add-missing) to
top-level.
Problem 8:
Makefile.am:131: warning: source file 'config/tc-aarch64.c' is in a subdirectory,
Makefile.am:131: but option 'subdir-objects' is disabled
automake: warning: possible forward-incompatibility.
automake: At least a source file is in a subdirectory, but the 'subdir-objects'
automake: automake option hasn't been enabled. For now, the corresponding output
automake: object file(s) will be placed in the top-level directory. However,
automake: this behaviour will change in future Automake versions: they will
automake: unconditionally cause object files to be placed in the same subdirectory
automake: of the corresponding sources.
automake: You are advised to start using 'subdir-objects' option throughout your
automake: project, to avoid future incompatibilities.
Solution 8:
Use subdir-objects, that means adjusting references to some .o that will now
be in config/.
Problem 9:
configure.ac:375: warning: AC_LANG_CONFTEST: no AC_LANG_SOURCE call detected in body
../../lib/autoconf/lang.m4:193: AC_LANG_CONFTEST is expanded from...
../../lib/autoconf/general.m4:2601: _AC_COMPILE_IFELSE is expanded from...
../../lib/autoconf/general.m4:2617: AC_COMPILE_IFELSE is expanded from...
../../lib/m4sugar/m4sh.m4:639: AS_IF is expanded from...
../../lib/autoconf/general.m4:2042: AC_CACHE_VAL is expanded from...
../../lib/autoconf/general.m4:2063: AC_CACHE_CHECK is expanded from...
configure.ac:375: the top level
Solution 9:
Use AC_LANG_SOURCE, or use proper quoting.
Problem 10 (in intl/):
configure.ac:7: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS
/usr/share/aclocal/threadlib.m4:36: gl_THREADLIB_EARLY_BODY is expanded from...
/usr/share/aclocal/threadlib.m4:29: gl_THREADLIB_EARLY is expanded from...
/usr/share/aclocal/threadlib.m4:318: gl_THREADLIB is expanded from...
/usr/share/aclocal/lock.m4:9: gl_LOCK is expanded from...
/usr/share/aclocal/intl.m4:211: gt_INTL_SUBDIR_CORE is expanded from...
/usr/share/aclocal/intl.m4:25: AM_INTL_SUBDIR is expanded from...
/usr/share/aclocal/gettext.m4:57: AM_GNU_GETTEXT is expanded from...
configure.ac:7: the top level
Solution 10:
Add AC_USE_SYSTEM_EXTENSIONS in configure.ac.
ChangeLog:
* libtool.m4: Use AC_LANG_SOURCE.
* configure.ac: Remove AC_PREREQ, use AC_LANG_SOURCE.
* README-maintainer-mode: Update version requirements.
* ar-lib: New file.
* test-driver: New file.
* configure: Re-generate.
bfd/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
(INCLUDES): Rename to ...
(AM_CPPFLAGS): ... this.
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9, cygnus, add
info-in-builddir no-texinfo.tex.
(info_TEXINFOS): Rename bfd.texinfo to bfd.texi.
* doc/bfd.texinfo: Rename to ...
* doc/bfd.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove cygnus, add
info-in-builddir no-texinfo.tex.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
config/ChangeLog:
* override.m4 (_GCC_AUTOCONF_VERSION): Bump from 2.64 to 2.69.
etc/ChangeLog:
* configure.in: Remove AC_PREREQ.
* configure: Re-generate.
gas/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
(TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix.
* configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles,
extra_objects): Add config/ prefix.
* doc/as.texinfo: Rename to...
* doc/as.texi: ... this.
* doc/Makefile.am: Rename as.texinfo to as.texi throughout.
Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and
info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gdb/ChangeLog:
* common/common-defs.h (PACKAGE_NAME, PACKAGE_VERSION,
PACKAGE_STRING, PACKAGE_TARNAME): Undefine.
* configure.ac: Remove AC_PREREQ, add missing quoting.
* gnulib/configure.ac: Modernize usage of
AC_INIT/AM_INIT_AUTOMAKE. Remove AC_PREREQ.
* gnulib/update-gnulib.sh (AUTOCONF_VERSION): Bump to 2.69.
(AUTOMAKE_VERSION): Bump to 1.15.1.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
* gnulib/aclocal.m4: Re-generate.
* gnulib/config.in: Re-generate.
* gnulib/configure: Re-generate.
* gnulib/import/Makefile.in: Re-generate.
gdb/gdbserver/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
gdb/testsuite/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
gold/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting and usage
of AC_LANG_SOURCE.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.11, add info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* gconfig.in: Re-generate.
intl/ChangeLog:
* configure.ac: Add AC_USE_SYSTEM_EXTENSIONS, remove AC_PREREQ.
* configure: Re-generate.
* config.h.in: Re-generate.
* aclocal.m4: Re-generate.
ld/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack, rename ld.texinfo to
ld.texi, ldint.texinfo to ldint.texi throughout.
(AUTOMAKE_OPTIONS): Add info-in-builddir.
* README: Rename ld.texinfo to ld.texi, ldint.texinfo to
ldint.texi throughout.
* gen-doc.texi: Likewise.
* h8-doc.texi: Likewise.
* ld.texinfo: Rename to ...
* ld.texi: ... this.
* ldint.texinfo: Rename to ...
* ldint.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
libdecnumber/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* aclocal.m4.
libiberty/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* config.in: Re-generate.
opcodes/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
* configure.ac: Remove AC_PREREQ.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
readline/ChangeLog.gdb:
* configure: Re-generate.
* examples/rlfe/configure: Re-generate.
sim/ChangeLog:
* All configure.ac: Remove AC_PREREQ.
* All configure: Re-generate.
zlib/ChangeLog.bin-gdb:
* configure.ac: Modernize AC_INIT call, remove AC_PREREQ.
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add
foreign.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
2018-06-20 04:54:48 +08:00
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|
2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
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|
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
|
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|
|
|
|
* configure.ac: Remove AC_PREREQ.
|
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|
|
|
* Makefile.in: Re-generate.
|
|
|
|
|
|
* aclocal.m4: Re-generate.
|
|
|
|
|
|
* configure: Re-generate.
|
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|
|
|
|
MIPS: Add Global INValidate ASE support
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
2018-06-15 04:34:49 +08:00
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2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
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* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
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mips64r6 descriptors.
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(parse_mips_ase_option): Handle -Mginv option.
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(print_mips_disassembler_options): Document -Mginv.
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* mips-opc.c (decode_mips_operand) <+\>: New operand format.
|
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(GINV): New macro.
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(mips_opcodes): Define ginvi and ginvt.
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MIPS: Add CRC ASE support
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
2018-06-13 22:39:05 +08:00
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2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
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Faraz Shahbazker <Faraz.Shahbazker@mips.com>
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* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
|
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* mips-opc.c (CRC, CRC64): New macros.
|
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(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
|
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crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
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crc32cd for CRC64.
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2018-06-08 21:02:52 +08:00
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2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
|
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PR 20319
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* aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
|
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(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
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2018-06-06 14:00:35 +08:00
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2018-06-06 Alan Modra <amodra@gmail.com>
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* xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
|
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setjmp. Move init for some other vars later too.
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2018-05-25 02:22:14 +08:00
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2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
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* xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
|
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(dis_private): Add new fields for property section tracking.
|
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(xtensa_coalesce_insn_tables, xtensa_find_table_entry)
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(xtensa_instruction_fits): New functions.
|
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(fetch_data): Bump minimal fetch size to 4.
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(print_insn_xtensa): Make struct dis_private static.
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Load and prepare property table on section change.
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Don't disassemble literals. Don't disassemble instructions that
|
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cross property table boundaries.
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2018-06-02 00:34:04 +08:00
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2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
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* configure: Regenerated.
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2018-06-01 14:41:16 +08:00
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2018-06-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
|
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* i386-tbl.h: Re-generate.
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2018-06-01 14:40:38 +08:00
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|
2018-06-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (sldt, str): Add NoRex64.
|
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* i386-tbl.h: Re-generate.
|
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2018-06-01 14:37:24 +08:00
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|
2018-06-01 Jan Beulich <jbeulich@suse.com>
|
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* i386-opc.tbl (invpcid): Add Oword.
|
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* i386-tbl.h: Re-generate.
|
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2018-06-01 09:30:46 +08:00
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|
2018-06-01 Alan Modra <amodra@gmail.com>
|
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* sysdep.h (_bfd_error_handler): Don't declare.
|
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* msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
|
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* rl78-decode.opc: Likewise.
|
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* msp430-decode.c: Regenerate.
|
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* rl78-decode.c: Regenerate.
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2018-05-30 14:57:35 +08:00
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2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
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* i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
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* i386-init.h : Regenerated.
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2018-05-25 14:35:30 +08:00
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2018-05-25 Alan Modra <amodra@gmail.com>
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* Makefile.in: Regenerate.
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* po/POTFILES.in: Regenerate.
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|
Remove fake operand handling for extended mnemonics.
opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-22 06:31:07 +08:00
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2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
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* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
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insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
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(insert_bab, extract_bab, insert_btab, extract_btab,
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insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
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(BAT, BBA VBA RBS XB6S): Delete macros.
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(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
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(BB, BD, RBX, XC6): Update for new macros.
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(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
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crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
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e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
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* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
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2018-05-18 22:26:18 +08:00
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* Makefile.am: Add support for s12z architecture.
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* configure.ac: Likewise.
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* disassemble.c: Likewise.
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* disassemble.h: Likewise.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* s12z-dis.c: New file.
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* s12z.h: New file.
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2018-05-18 07:01:13 +08:00
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2018-05-18 Alan Modra <amodra@gmail.com>
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* nfp-dis.c: Don't #include libbfd.h.
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(init_nfp3200_priv): Use bfd_get_section_contents.
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(nit_nfp6000_mecsr_sec): Likewise.
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2018-05-17 23:24:42 +08:00
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2018-05-17 Nick Clifton <nickc@redhat.com>
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* po/zh_CN.po: Updated simplified Chinese translation.
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2018-05-16 19:13:42 +08:00
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2018-05-16 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23109
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* aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
|
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* aarch64-dis-2.c: Regenerate.
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|
Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 23:37:20 +08:00
|
|
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|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
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PR binutils/21446
|
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|
|
* aarch64-asm.c (opintl.h): Include.
|
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|
|
(aarch64_ins_sysreg): Enforce read/write constraints.
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|
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
|
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|
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
|
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(F_REG_READ, F_REG_WRITE): New.
|
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|
|
* aarch64-opc.c (aarch64_print_operand): Generate notes for
|
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AARCH64_OPND_SYSREG.
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|
|
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
|
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|
|
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
|
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|
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
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|
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
|
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|
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
|
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|
|
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
|
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|
|
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
|
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|
|
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
|
|
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|
|
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
|
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|
|
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
|
|
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|
|
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
|
|
|
|
|
|
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
|
|
|
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|
|
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
|
|
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|
|
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
|
|
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|
|
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
|
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|
|
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
|
|
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|
|
msr (F_SYS_WRITE), mrs (F_SYS_READ).
|
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|
2018-05-15 23:34:54 +08:00
|
|
|
|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
|
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|
|
PR binutils/21446
|
|
|
|
|
|
* aarch64-dis.c (no_notes: New.
|
|
|
|
|
|
(parse_aarch64_dis_option): Support notes.
|
|
|
|
|
|
(aarch64_decode_insn, print_operands): Likewise.
|
|
|
|
|
|
(print_aarch64_disassembler_options): Document notes.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Support notes.
|
|
|
|
|
|
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 23:11:42 +08:00
|
|
|
|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21446
|
|
|
|
|
|
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
|
|
|
|
|
|
and take error struct.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
|
|
|
|
|
|
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
|
|
|
|
|
|
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
|
|
|
|
|
|
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
|
|
|
|
|
|
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
|
|
|
|
|
|
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
|
|
|
|
|
|
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
|
|
|
|
|
|
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
|
|
|
|
|
|
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
|
|
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|
|
|
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
|
|
|
|
|
|
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
|
|
|
|
|
|
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
|
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|
|
|
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
|
|
|
|
|
|
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
|
|
|
|
|
|
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
|
|
|
|
|
|
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
|
|
|
|
|
|
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
|
|
|
|
|
|
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
|
|
|
|
|
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
|
|
|
|
|
|
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
|
|
|
|
|
|
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
|
|
|
|
|
|
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
|
|
|
|
|
|
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
|
|
|
|
|
|
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
|
|
|
|
|
|
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
|
|
|
|
|
|
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
|
|
|
|
|
|
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
|
|
|
|
|
|
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
|
|
|
|
|
|
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
|
|
|
|
|
|
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
|
|
|
|
|
|
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
|
|
|
|
|
|
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
|
|
|
|
|
|
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
|
|
|
|
|
|
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
|
|
|
|
|
|
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
|
|
|
|
|
|
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
|
|
|
|
|
|
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
|
|
|
|
|
|
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
|
|
|
|
|
|
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
|
|
|
|
|
|
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
|
|
|
|
|
|
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
|
|
|
|
|
|
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
|
|
|
|
|
|
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
|
|
|
|
|
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
|
|
|
|
|
|
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
|
|
|
|
|
|
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
|
|
|
|
|
|
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
|
|
|
|
|
|
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
|
|
|
|
|
|
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
|
|
|
|
|
|
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
|
|
|
|
|
|
(determine_disassembling_preference, aarch64_decode_insn,
|
|
|
|
|
|
print_insn_aarch64_word, print_insn_data): Take errors struct.
|
|
|
|
|
|
(print_insn_aarch64): Use errors.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
|
|
|
|
|
|
boolean in aarch64_insert_operan.
|
|
|
|
|
|
(print_operand_extractor): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
|
|
|
|
|
|
|
2018-05-15 20:28:06 +08:00
|
|
|
|
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
|
|
|
|
|
|
|
2018-05-10 02:17:26 +08:00
|
|
|
|
2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
|
|
|
|
|
|
|
2018-05-09 14:20:29 +08:00
|
|
|
|
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-opc.c (cr16_instruction): Comment typo fix.
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Likewise.
|
|
|
|
|
|
|
RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-09 06:46:19 +08:00
|
|
|
|
2018-05-08 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
|
|
|
|
|
|
(match_c_slli64, match_srxi_as_c_srxi): New.
|
|
|
|
|
|
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
|
|
|
|
|
|
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
|
|
|
|
|
|
<c.slli, c.srli, c.srai>: Use match_s_slli.
|
|
|
|
|
|
<c.slli64, c.srli64, c.srai64>: New.
|
|
|
|
|
|
|
2018-05-07 10:05:22 +08:00
|
|
|
|
2018-05-08 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
|
|
|
|
|
|
(VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
|
|
|
|
|
|
partition opcode space for index lookup.
|
|
|
|
|
|
|
2018-05-08 09:47:54 +08:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
|
|
|
|
|
|
<insn_length>: ...with this. Update usage.
|
|
|
|
|
|
Remove duplicate call to *info->memory_error_func.
|
|
|
|
|
|
|
Enable Intel MOVDIRI, MOVDIR64B instructions
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-08 00:30:02 +08:00
|
|
|
|
2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Gva): New.
|
|
|
|
|
|
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
|
|
|
|
|
|
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
|
|
|
|
|
|
(prefix_table): New instructions (see prefix above).
|
|
|
|
|
|
(mod_table): New instructions (see prefix above).
|
|
|
|
|
|
(OP_G): Handle va_mode.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
|
|
|
|
|
|
CPU_MOVDIR64B_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
|
|
|
|
|
|
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
|
|
|
|
|
|
* i386-opc.tbl: Add movidir{i,64b}.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-05-08 00:57:06 +08:00
|
|
|
|
2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
|
|
|
|
|
|
AddrPrefixOpReg.
|
|
|
|
|
|
* i386-opc.h (AddrPrefixOp0): Renamed to ...
|
|
|
|
|
|
(AddrPrefixOpReg): This.
|
|
|
|
|
|
(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
|
|
|
|
|
|
* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
|
|
|
|
|
|
|
2018-05-07 22:40:59 +08:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
|
|
|
|
|
|
(vle_num_opcodes): Likewise.
|
|
|
|
|
|
(spe2_num_opcodes): Likewise.
|
|
|
|
|
|
* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
|
|
|
|
|
|
initialization loop.
|
|
|
|
|
|
(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
|
|
|
|
|
|
(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
|
|
|
|
|
|
only once.
|
|
|
|
|
|
|
2018-05-02 00:11:11 +08:00
|
|
|
|
2018-05-01 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
|
|
|
|
|
|
|
2018-05-01 00:02:59 +08:00
|
|
|
|
2018-04-30 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
Makefile.am: Added nfp-dis.c.
|
|
|
|
|
|
configure.ac: Added bfd_nfp_arch.
|
|
|
|
|
|
disassemble.h: Added print_insn_nfp prototype.
|
|
|
|
|
|
disassemble.c: Added ARCH_nfp and call to print_insn_nfp
|
|
|
|
|
|
nfp-dis.c: New, for NFP support.
|
|
|
|
|
|
po/POTFILES.in: Added nfp-dis.c to the list.
|
|
|
|
|
|
Makefile.in: Regenerate.
|
|
|
|
|
|
configure: Regenerate.
|
|
|
|
|
|
|
2018-04-26 14:55:02 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold various non-memory operand AVX512VL
|
|
|
|
|
|
templates into their base ones.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:48:56 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
|
|
|
|
|
|
CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
|
|
|
|
|
|
CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
|
|
|
|
|
|
CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:48:01 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
|
|
|
|
|
|
CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
|
|
|
|
|
|
CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
|
|
|
|
|
|
Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
|
|
|
|
|
|
comment.
|
|
|
|
|
|
(cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
and CpuRegMask.
|
|
|
|
|
|
* i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
CpuRegMask: Delete.
|
|
|
|
|
|
(union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
|
|
|
|
|
|
cpuregzmm, and cpuregmask.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:45:35 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
|
|
|
|
|
|
CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:30:06 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (VexImmExt): Delete.
|
|
|
|
|
|
* i386-opc.h (VexImmExt, veximmext): Delete.
|
|
|
|
|
|
* i386-opc.tbl: Drop all VexImmExt uses.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-25 22:26:10 +08:00
|
|
|
|
2018-04-25 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
|
|
|
|
|
|
register-only forms.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-25 20:37:30 +08:00
|
|
|
|
2018-04-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
|
|
|
|
|
|
|
2018-04-17 05:09:01 +08:00
|
|
|
|
2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
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|
|
|
|
|
|
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
|
|
|
|
|
|
PREFIX_0F1C.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
|
|
|
|
|
|
(cpu_flags): Add CpuCLDEMOTE.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuCLDEMOTE,
|
|
|
|
|
|
(i386_cpu_flags): Add cpucldemote.
|
|
|
|
|
|
* i386-opc.tbl: Add cldemote.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:59:39 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
* Makefile.am: Remove sh5 and sh64 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* sh-dis.c: Likewise.
|
|
|
|
|
|
* sh64-dis.c: Delete.
|
|
|
|
|
|
* sh64-opc.c: Delete.
|
|
|
|
|
|
* sh64-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
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|
|
2018-04-16 13:56:05 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
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|
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|
|
* Makefile.am: Remove w65 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* w65-dis.c: Delete.
|
|
|
|
|
|
* w65-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
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|
|
|
|
2018-04-16 13:54:43 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Remove we32k support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:53:38 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
|
* Makefile.am: Remove m88k support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* m88k-dis.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:51:56 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove i370 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* i370-dis.c: Delete.
|
|
|
|
|
|
* i370-opc.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:49:41 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove h8500 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* h8500-dis.c: Delete.
|
|
|
|
|
|
* h8500-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:38:40 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Remove tahoe support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-04-15 23:38:23 +08:00
|
|
|
|
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
|
|
|
|
|
|
umwait.
|
|
|
|
|
|
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
|
|
|
|
|
|
64-bit mode.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-04-09 18:58:50 +08:00
|
|
|
|
2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
|
|
|
|
|
|
PREFIX_MOD_1_0FAE_REG_6.
|
|
|
|
|
|
(va_mode): New.
|
|
|
|
|
|
(OP_E_register): Use va_mode.
|
|
|
|
|
|
* i386-dis-evex.h (prefix_table):
|
|
|
|
|
|
New instructions (see prefixes above).
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add WAITPKG.
|
|
|
|
|
|
(cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.h (enum): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Add umonitor, umwait, tpause.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
Remove i860, i960, bout and aout-adobe targets
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 17:16:05 +08:00
|
|
|
|
2018-04-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/i860-dis.c: Delete.
|
|
|
|
|
|
* opcodes/i960-dis.c: Delete.
|
|
|
|
|
|
* Makefile.am: Remove i860 and i960 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-04 19:36:44 +08:00
|
|
|
|
2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23025
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
|
|
|
|
|
|
to 0.
|
|
|
|
|
|
(print_insn): Clear vex instead of vex.evex.
|
|
|
|
|
|
|
2018-04-04 16:00:18 +08:00
|
|
|
|
2018-04-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
|
2018-03-28 20:25:07 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete VecESize.
|
|
|
|
|
|
* i386-opc.h (VecESize): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete vecesize.
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:24:05 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
|
|
|
|
|
|
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
|
|
|
|
|
|
* i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:22:56 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
|
|
|
|
|
|
Fold AVX512 forms
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:22:00 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Drop Y for cvt*2si.
|
|
|
|
|
|
(vex_len_table): Drop Y for vcvt*2si.
|
|
|
|
|
|
(putop): Replace plain 'Y' handling by abort().
|
|
|
|
|
|
|
2018-03-28 16:44:45 +08:00
|
|
|
|
2018-03-28 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22988
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
|
|
|
|
|
|
instructions with only a base address register.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
|
|
|
|
|
|
handle AARHC64_OPND_SVE_ADDR_R.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64_dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2018-03-22 15:46:25 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize from register only insn forms and
|
|
|
|
|
|
memory forms not allowing broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:34:24 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
|
|
|
|
|
|
vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
|
|
|
|
|
|
sha256*): Drop Disp<N>.
|
|
|
|
|
|
|
2018-03-22 15:32:50 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EbndS, bnd_swap_mode): New.
|
|
|
|
|
|
(prefix_table): Use EbndS.
|
|
|
|
|
|
(OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
|
|
|
|
|
|
* i386-opc.tbl (bndmov): Move misplaced Load.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:31:43 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
|
|
|
|
|
|
templates allowing memory operands and folded ones for register
|
|
|
|
|
|
only flavors.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:29:45 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
|
|
|
|
|
|
256-bit templates. Drop redundant leftover Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-15 07:04:03 +08:00
|
|
|
|
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_insn_types): New.
|
|
|
|
|
|
|
2018-03-14 00:57:29 +08:00
|
|
|
|
2018-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-03-08 22:41:34 +08:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add Optimize to clr.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 22:31:32 +08:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove OldGcc.
|
|
|
|
|
|
* i386-opc.h (OldGcc): Removed.
|
|
|
|
|
|
(i386_opcode_modifier): Remove oldgcc.
|
|
|
|
|
|
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
|
|
|
|
|
|
instructions for old (<= 2.8.1) versions of gcc.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 15:58:55 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (EVEXDYN): New.
|
|
|
|
|
|
* i386-opc.tbl: Fold various AVX512VL templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:58:05 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
|
|
|
|
|
vpexpandd, vpexpandq): Fold AFX512VF templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:57:19 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
|
|
|
|
|
|
Fold 128- and 256-bit VEX-encoded templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:56:47 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
|
|
|
|
|
vpexpandd, vpexpandq): Fold AVX512F templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:56:08 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
|
|
|
|
|
|
64-bit templates. Drop Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:55:37 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
|
|
|
|
|
|
and 256-bit templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:52:27 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg8b): Add NoRex64.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:36:41 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
|
|
|
|
|
|
Drop NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:35:48 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:34:09 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete FloatD.
|
|
|
|
|
|
* i386-opc.h (FloatD): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete floatd.
|
|
|
|
|
|
* i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
|
|
|
|
|
|
FloatD by D.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:33:06 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
|
|
|
|
|
|
|
2018-03-08 15:26:35 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:25:31 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
|
|
|
|
|
|
forms.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-07 08:36:15 +08:00
|
|
|
|
2018-03-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
|
|
|
|
|
|
bfd_arch_rs6000.
|
|
|
|
|
|
* disassemble.h (print_insn_rs6000): Delete.
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
|
|
|
|
|
|
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
|
|
|
|
|
|
(print_insn_rs6000): Delete.
|
|
|
|
|
|
|
opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-02 05:53:50 +08:00
|
|
|
|
2018-03-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sysdep.h (opcodes_error_handler): Define.
|
|
|
|
|
|
(_bfd_error_handler): Declare.
|
|
|
|
|
|
* Makefile.am: Remove stray #.
|
|
|
|
|
|
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
|
|
|
|
|
|
EDIT" comment.
|
|
|
|
|
|
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
|
|
|
|
|
|
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
|
|
|
|
|
|
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
|
|
|
|
|
|
opcodes_error_handler to print errors. Standardize error messages.
|
|
|
|
|
|
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
|
|
|
|
|
|
and include opintl.h.
|
|
|
|
|
|
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
|
|
|
|
|
|
* i386-gen.c: Standardize error messages.
|
|
|
|
|
|
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
|
|
|
|
|
|
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
|
|
|
|
|
|
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
|
|
|
|
|
|
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
|
|
|
|
|
|
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
|
|
|
|
|
|
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
|
|
|
|
|
|
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
|
|
|
|
|
|
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
|
|
|
|
|
|
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
|
|
|
|
|
|
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
|
|
|
|
|
|
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
|
|
|
|
|
|
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2018-03-01 22:08:04 +08:00
|
|
|
|
2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
|
|
|
|
|
|
vpsub[bwdq] instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-01 05:56:51 +08:00
|
|
|
|
2018-03-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac (ALL_LINGUAS): Sort.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-02-28 00:40:45 +08:00
|
|
|
|
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
|
|
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|
|
|
macro by assignements.
|
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|
|
x86: Add -O[2|s] assembler command-line options
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
2018-02-27 23:36:33 +08:00
|
|
|
|
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
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|
|
|
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|
|
PR gas/22871
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add Optimize.
|
|
|
|
|
|
* i386-opc.h (Optimize): New enum.
|
|
|
|
|
|
(i386_opcode_modifier): Add optimize.
|
|
|
|
|
|
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
|
|
|
|
|
|
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
|
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|
|
|
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
|
|
|
|
|
|
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
|
|
|
|
|
|
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
|
|
|
|
|
|
vpxord and vpxorq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-02-24 08:03:33 +08:00
|
|
|
|
2018-02-26 Alan Modra <amodra@gmail.com>
|
|
|
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|
|
|
|
|
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|
|
* crx-dis.c (getregliststring): Allocate a large enough buffer
|
|
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|
|
to silence false positive gcc8 warning.
|
|
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|
|
2018-02-23 03:28:51 +08:00
|
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|
|
2018-02-22 Shea Levy <shea@shealevy.com>
|
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|
|
* disassemble.c (ARCH_riscv): Define if ARCH_all.
|
|
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|
|
2018-02-22 22:18:27 +08:00
|
|
|
|
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add {rex},
|
|
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|
|
|
* i386-tbl.h: Regenerated.
|
|
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|
|
2018-02-21 04:51:36 +08:00
|
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|
|
2018-02-20 Maciej W. Rozycki <macro@mips.com>
|
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|
|
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
|
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|
|
|
|
(mips16_opcodes): Replace `M' with `m' for "restore".
|
|
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|
|
2018-02-19 20:05:18 +08:00
|
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|
|
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
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|
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|
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|
|
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
|
|
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|
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|
|
2018-02-13 20:56:29 +08:00
|
|
|
|
2018-02-13 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
|
|
|
|
|
|
variable to `function_index'.
|
|
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|
|
2018-02-13 21:14:47 +08:00
|
|
|
|
2018-02-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22823
|
|
|
|
|
|
* metag-dis.c (print_fmmov): Double buffer size to avoid warning
|
|
|
|
|
|
about truncation of printing.
|
|
|
|
|
|
|
MIPS: Fix encoding for MIPSr6 sigrie instruction.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12 22:50:42 +08:00
|
|
|
|
2018-02-12 Henry Wong <henry@stuffedcow.net>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
|
|
|
|
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|
|
2018-02-05 21:09:15 +08:00
|
|
|
|
2018-02-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
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|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-01-24 00:56:30 +08:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add pconfig.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuPCONFIG.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuPCONFIG.
|
|
|
|
|
|
(i386_cpu_flags): Add cpupconfig.
|
|
|
|
|
|
* i386-opc.tbl: Add PCONFIG instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-24 00:39:05 +08:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_0F09.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuWBNOINVD.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuWBNOINVD.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuwbnoinvd.
|
|
|
|
|
|
* i386-opc.tbl: Add WBNOINVD instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-18 06:04:16 +08:00
|
|
|
|
2018-01-17 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
|
|
|
|
|
|
|
Replace CET bit with IBT and SHSTK bits.
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-18 00:45:52 +08:00
|
|
|
|
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
|
|
|
|
|
|
Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
|
|
|
|
|
|
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(cpu_flags): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuibt, cpushstk.
|
|
|
|
|
|
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-16 20:45:44 +08:00
|
|
|
|
2018-01-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portugese translation.
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
|
2018-01-16 06:53:44 +08:00
|
|
|
|
2018-01-15 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_nop): New.
|
|
|
|
|
|
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
|
|
|
|
|
|
|
2018-01-15 20:09:11 +08:00
|
|
|
|
2018-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2018-01-13 21:56:48 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Regenerated.
|
|
|
|
|
|
|
2018-01-13 21:31:12 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-01-13 21:26:38 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.30 branch created.
|
|
|
|
|
|
|
2018-01-11 07:56:45 +08:00
|
|
|
|
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2018-01-10 21:53:43 +08:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 21:53:05 +08:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
|
|
|
|
|
|
vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
|
|
|
|
|
|
vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
|
|
|
|
|
|
vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
|
|
|
|
|
|
vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
|
|
|
|
|
|
Disp8MemShift of AVX512VL forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 08:40:06 +08:00
|
|
|
|
2018-01-09 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (maybe_print_address): If base_reg is zero,
|
|
|
|
|
|
then the hi_addr value is zero.
|
|
|
|
|
|
|
2018-01-09 22:15:00 +08:00
|
|
|
|
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add csdb.
|
|
|
|
|
|
(thumb32_opcodes): Add csdb.
|
|
|
|
|
|
|
2018-01-09 19:28:04 +08:00
|
|
|
|
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-01-08 20:36:59 +08:00
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2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22681
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* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
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Remove AVX512 vmovd with 64-bit operands.
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* i386-tbl.h: Regenerated.
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2018-01-06 09:51:23 +08:00
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2018-01-05 Jim Wilson <jimw@sifive.com>
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* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
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jalr.
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2018-01-03 13:17:27 +08:00
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2018-01-03 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2018-01-02 18:44:04 +08:00
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2018-01-02 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
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and OPERAND_TYPE_REGZMM entries.
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2018-01-03 13:15:17 +08:00
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For older changes see ChangeLog-2017
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2016-01-01 18:44:31 +08:00
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2018-01-03 13:15:17 +08:00
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Copyright (C) 2018 Free Software Foundation, Inc.
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2016-01-01 18:44:31 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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