2020-01-31 21:28:43 +08:00
|
|
|
|
2020-01-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
|
|
|
|
|
|
(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
|
|
|
|
|
|
vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
|
|
|
|
|
|
(intel_operand_size): Drop vex_w_dq_mode case label.
|
|
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|
|
|
|
2020-01-31 16:03:56 +08:00
|
|
|
|
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
|
|
|
|
|
|
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
|
|
|
|
|
|
|
2020-01-30 19:29:20 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
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|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 20:59:04 +08:00
|
|
|
|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
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|
|
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|
|
|
|
* bpf-opc.c: Regenerate.
|
|
|
|
|
|
|
2020-01-30 18:36:33 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
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|
|
|
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|
|
|
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
|
|
|
|
|
|
(dis386): Use them to replace C2/C3 table entries.
|
|
|
|
|
|
(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
|
|
|
|
|
|
* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
|
|
|
|
|
|
ones. Use Size64 instead of DefaultSize on Intel64 ones.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 18:33:53 +08:00
|
|
|
|
2020-01-30 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
|
|
|
|
|
|
forms.
|
|
|
|
|
|
(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
|
|
|
|
|
|
DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-30 14:36:54 +08:00
|
|
|
|
2020-01-30 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_dp): Make unsigned.
|
|
|
|
|
|
|
2020-01-27 20:38:10 +08:00
|
|
|
|
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/25445
|
|
|
|
|
|
* i386-dis.c (MOVSXD_Fixup): New function.
|
|
|
|
|
|
(movsxd_mode): New enum.
|
|
|
|
|
|
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
|
|
|
|
|
|
(intel_operand_size): Handle movsxd_mode.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
|
|
|
|
|
|
register on movsxd. Add movsxd with 16-bit destination register
|
|
|
|
|
|
for AMD64 and Intel64 ISAs.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-27 18:40:02 +08:00
|
|
|
|
2020-01-27 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25403
|
|
|
|
|
|
* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 15:28:25 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (sysret): Drop DefaultSize.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-21 15:25:31 +08:00
|
|
|
|
2020-01-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
|
|
|
|
|
|
Dword.
|
|
|
|
|
|
(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-20 23:10:23 +08:00
|
|
|
|
2020-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2020-01-20 10:02:37 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa-dis.c (fput_const): Remove useless cast.
|
|
|
|
|
|
|
2020-01-20 10:01:58 +08:00
|
|
|
|
2020-01-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Wrap 'T' value.
|
|
|
|
|
|
|
2020-01-18 22:12:07 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2020-01-18 21:50:25 +08:00
|
|
|
|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Binutils 2.34 branch created.
|
|
|
|
|
|
|
2020-01-18 02:34:03 +08:00
|
|
|
|
2020-01-17 Christian Biesinger <cbiesinger@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opintl.h: Fix spelling error (seperate).
|
|
|
|
|
|
|
2020-01-17 23:07:55 +08:00
|
|
|
|
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add {vex} pseudo prefix.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2020-01-16 21:50:52 +08:00
|
|
|
|
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25376
|
|
|
|
|
|
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
(select_arm_features): Make sure we enable MVE bits when selecting
|
|
|
|
|
|
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
|
|
|
|
|
|
any architecture.
|
|
|
|
|
|
|
2020-01-16 17:07:05 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop stale comment from XOP section.
|
|
|
|
|
|
|
2020-01-16 17:06:21 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
|
|
|
|
|
|
(extractps): Add VexWIG to SSE2AVX forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-16 17:05:35 +08:00
|
|
|
|
2020-01-16 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
|
|
|
|
|
|
Size64 from and use VexW1 on SSE2AVX forms.
|
|
|
|
|
|
(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
|
|
|
|
|
|
VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2020-01-15 13:37:16 +08:00
|
|
|
|
2020-01-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_version): Make unsigned long.
|
|
|
|
|
|
(optab, optab_special, registernames): New file scope vars.
|
|
|
|
|
|
(tic4x_print_register): Set up registernames rather than
|
|
|
|
|
|
malloc'd registertable.
|
|
|
|
|
|
(tic4x_disassemble): Delete optable and optable_special. Use
|
|
|
|
|
|
optab and optab_special instead. Throw away old optab,
|
|
|
|
|
|
optab_special and registernames when info->mach changes.
|
|
|
|
|
|
|
2020-01-14 21:13:57 +08:00
|
|
|
|
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 25377
|
|
|
|
|
|
* z80-dis.c (suffix): Use .db instruction to generate double
|
|
|
|
|
|
prefix.
|
|
|
|
|
|
|
2020-01-14 06:47:09 +08:00
|
|
|
|
2020-01-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
|
|
|
|
|
|
values to unsigned before shifting.
|
|
|
|
|
|
|
Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
(detected_jumps): New variables.
(usage): Add the new jump visualization options.
(option_values): Add new option value.
(long_options): Add the new option.
(jump_info_new, jump_info_free): New functions.
(jump_info_min_address, jump_info_max_address): Likewise.
(jump_info_end_address, jump_info_is_start_address): Likewise.
(jump_info_is_end_address, jump_info_size): Likewise.
(jump_info_unlink, jump_info_insert): Likewise.
(jump_info_add_front, jump_info_move_linked): Likewise.
(jump_info_intersect, jump_info_merge): Likewise.
(jump_info_sort, jump_info_visualize_address): Likewise.
(disassemble_jumps): New function - used to locate jumps.
(disassemble_bytes): Add ascii art generation.
(disassemble_section): Add scan to locate jumps.
(main): Parse the new visualization option.
* doc/binutils.texi: Document the new feature.
* NEWS: Mention the new feature.
opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control
flow instructions.
(print_insn_thumb16, print_insn_thumb32): Likewise.
(print_insn): Initialize the insn info.
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
2020-01-13 20:36:55 +08:00
|
|
|
|
2020-01-13 Thomas Troeger <tstroege@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Fill in insn info fields for control
|
|
|
|
|
|
flow instructions.
|
|
|
|
|
|
(print_insn_thumb16, print_insn_thumb32): Likewise.
|
|
|
|
|
|
(print_insn): Initialize the insn info.
|
|
|
|
|
|
* i386-dis.c (print_insn): Initialize the insn info fields, and
|
|
|
|
|
|
detect jumps.
|
|
|
|
|
|
|
2020-01-13 17:16:47 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (C_NE): Make it required.
|
|
|
|
|
|
|
2020-01-13 16:21:30 +08:00
|
|
|
|
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
|
|
|
|
|
|
reserved register name.
|
|
|
|
|
|
|
2020-01-13 15:28:02 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
|
|
|
|
|
|
(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
|
|
|
|
|
|
|
2020-01-13 11:57:19 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
|
|
|
|
|
|
result of wasm_read_leb128 in a uint64_t and check that bits
|
|
|
|
|
|
are not lost when copying to other locals. Use uint32_t for
|
|
|
|
|
|
most locals. Use PRId64 when printing int64_t.
|
|
|
|
|
|
|
2020-01-13 08:48:36 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c: Formatting.
|
|
|
|
|
|
* score7-dis.c: Formatting.
|
|
|
|
|
|
|
2020-01-13 08:16:55 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* score-dis.c (print_insn_score48): Use unsigned variables for
|
|
|
|
|
|
unsigned values. Don't left shift negative values.
|
|
|
|
|
|
(print_insn_score32): Likewise.
|
|
|
|
|
|
* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
|
|
|
|
|
|
|
2020-01-12 17:46:22 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic4x-dis.c (tic4x_print_register): Remove dead code.
|
|
|
|
|
|
|
2020-01-11 10:02:11 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-ibld.c: Regenerate.
|
|
|
|
|
|
|
2020-01-11 09:53:47 +08:00
|
|
|
|
2020-01-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* xgate-dis.c (print_insn): Don't left shift signed value.
|
|
|
|
|
|
(ripBits): Formatting, use 1u.
|
|
|
|
|
|
|
2020-01-10 05:57:33 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
|
|
|
|
|
|
* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
|
|
|
|
|
|
|
2020-01-09 04:29:42 +08:00
|
|
|
|
2020-01-10 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
|
|
|
|
|
|
and XRREG value earlier to avoid a shift with negative exponent.
|
|
|
|
|
|
* m10200-dis.c (disassemble): Similarly.
|
|
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2020-01-09 22:32:49 +08:00
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2020-01-09 Nick Clifton <nickc@redhat.com>
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PR 25224
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* z80-dis.c (ld_ii_ii): Use correct cast.
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2020-01-09 19:47:44 +08:00
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2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25224
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* z80-dis.c (ld_ii_ii): Use character constant when checking
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opcode byte value.
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2020-01-09 18:38:01 +08:00
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (SEP_Fixup): New.
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(SEP): Define.
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(dis386_twobyte): Use it for sysenter/sysexit.
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(enum x86_64_isa): Change amd64 enumerator to value 1.
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(OP_J): Compare isa64 against intel64 instead of amd64.
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* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
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forms.
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* i386-tbl.h: Re-generate.
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2020-01-08 09:12:36 +08:00
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2020-01-08 Alan Modra <amodra@gmail.com>
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* z8k-dis.c: Include libiberty.h
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(instr_data_s): Make max_fetched unsigned.
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(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
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Don't exceed byte_info bounds.
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(output_instr): Make num_bytes unsigned.
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(unpack_instr): Likewise for nibl_count and loop.
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* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
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idx unsigned.
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* z8k-opc.h: Regenerate.
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2020-01-07 21:25:15 +08:00
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2020-01-07 Shahab Vahedi <shahab@synopsys.com>
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* arc-tbl.h (llock): Use 'LLOCK' as class.
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(llockd): Likewise.
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(scond): Use 'SCOND' as class.
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(scondd): Likewise.
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(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
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(scondd): Likewise.
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2020-01-04 17:23:19 +08:00
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2020-01-06 Alan Modra <amodra@gmail.com>
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* m32c-ibld.c: Regenerate.
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2020-01-06 06:22:39 +08:00
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2020-01-06 Alan Modra <amodra@gmail.com>
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PR 25344
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* z80-dis.c (suffix): Don't use a local struct buffer copy.
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Peek at next byte to prevent recursion on repeated prefix bytes.
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Ensure uninitialised "mybuf" is not accessed.
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(print_insn_z80): Don't zero n_fetch and n_used here,..
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(print_insn_z80_buf): ..do it here instead.
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2020-01-04 05:41:43 +08:00
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2020-01-04 Alan Modra <amodra@gmail.com>
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* m32r-ibld.c: Regenerate.
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2020-01-03 05:42:00 +08:00
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2020-01-04 Alan Modra <amodra@gmail.com>
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* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
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2020-01-03 04:37:17 +08:00
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2020-01-04 Alan Modra <amodra@gmail.com>
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* crx-dis.c (match_opcode): Avoid shift left of signed value.
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2020-01-01 16:16:43 +08:00
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2020-01-04 Alan Modra <amodra@gmail.com>
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* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
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2020-01-03 17:14:16 +08:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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2020-01-03 17:16:44 +08:00
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|
* aarch64-tbl.h (aarch64_opcode_table): Use
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|
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
|
2020-01-03 17:14:16 +08:00
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forms of SUDOT and USDOT.
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|
2020-01-03 17:13:31 +08:00
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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|
2020-01-03 17:16:44 +08:00
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|
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
|
2020-01-03 17:13:31 +08:00
|
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|
|
uzip{1,2}.
|
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|
* opcodes/aarch64-dis-2.c: Re-generate.
|
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|
2020-01-03 17:12:49 +08:00
|
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|
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
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|
2020-01-03 17:16:44 +08:00
|
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|
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
|
2020-01-03 17:12:49 +08:00
|
|
|
|
FMMLA encoding.
|
|
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|
|
|
* opcodes/aarch64-dis-2.c: Re-generate.
|
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|
|
2020-01-02 22:10:40 +08:00
|
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|
|
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
|
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|
* z80-dis.c: Add support for eZ80 and Z80 instructions.
|
|
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|
|
2020-01-01 16:22:19 +08:00
|
|
|
|
2020-01-01 Alan Modra <amodra@gmail.com>
|
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|
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|
|
Update year range in copyright notice of all files.
|
|
|
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|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
For older changes see ChangeLog-2019
|
2016-01-01 18:44:31 +08:00
|
|
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|
|
2020-01-01 15:37:11 +08:00
|
|
|
|
Copyright (C) 2020 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
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|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
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|
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|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
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|
|
fill-column: 74
|
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|
|
version-control: never
|
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End:
|
