mirror of
https://sourceware.org/git/binutils-gdb.git
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221 lines
4.1 KiB
ArmAsm
221 lines
4.1 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp
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// Spec Reference: alu2op logical left
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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imm32 r0, 0x00000000;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x856789ab;
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imm32 r5, 0x96789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb89abcde;
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R0.L = 1;
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R1 <<= R0;
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R2 <<= R0;
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R3 <<= R0;
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R4 <<= R0;
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R5 <<= R0;
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R6 <<= R0;
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R7 <<= R0;
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R4 <<= R0;
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R0 <<= R0;
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CHECKREG r1, 0x2468ACF0;
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CHECKREG r2, 0x468ACF12;
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CHECKREG r3, 0x68ACF134;
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CHECKREG r4, 0x159E26AC;
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CHECKREG r5, 0x2CF13578;
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CHECKREG r6, 0x4F13579A;
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CHECKREG r7, 0x713579BC;
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CHECKREG r0, 0x00000002;
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imm32 r0, 0x01230002;
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imm32 r1, 0x00000000;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R1.L = -1;
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R0 <<= R1;
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R2 <<= R1;
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R3 <<= R1;
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R4 <<= R1;
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R5 <<= R1;
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R6 <<= R1;
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R7 <<= R1;
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R1 <<= R1;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x51230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x00000000;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x956789ab;
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imm32 r5, 0x86789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R2.L = 31;
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R0 <<= R2;
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R1 <<= R2;
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R3 <<= R2;
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R4 <<= R2;
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R5 <<= R2;
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R6 <<= R2;
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R7 <<= R2;
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R2 <<= R2;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x80000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x80000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x82345678;
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imm32 r2, 0x93456789;
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imm32 r3, 0x00000000;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R3.L = -31;
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R0 <<= R3;
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R1 <<= R3;
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R2 <<= R3;
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R4 <<= R3;
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R5 <<= R3;
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R6 <<= R3;
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R7 <<= R3;
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R3 <<= R3;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x00000001;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x00000000;
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imm32 r5, 0x96789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb89abcde;
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R4.L = 15;
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R1 <<= R4;
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R2 <<= R4;
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R3 <<= R4;
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R0 <<= R4;
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R5 <<= R4;
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R6 <<= R4;
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R7 <<= R4;
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R4 <<= R4;
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CHECKREG r0, 0x00008000;
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CHECKREG r1, 0x2B3C0000;
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CHECKREG r2, 0xB3C48000;
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CHECKREG r3, 0x3C4D0000;
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CHECKREG r4, 0x00078000;
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CHECKREG r5, 0x4D5E0000;
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CHECKREG r6, 0xD5E68000;
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CHECKREG r7, 0x5E6F0000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x00000000;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0x00000000;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R5.L = -15;
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R0 <<= R5;
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R1 <<= R5;
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R2 <<= R5;
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R3 <<= R5;
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R4 <<= R5;
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R6 <<= R5;
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R7 <<= R5;
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R5 <<= R5;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x51230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0xb1256790;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x956789ab;
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imm32 r5, 0x86789abc;
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imm32 r6, 0x00000000;
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imm32 r7, 0x789abcde;
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R6.L = 24;
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R0 <<= R6;
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R1 <<= R6;
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R2 <<= R6;
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R3 <<= R6;
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R4 <<= R6;
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R5 <<= R6;
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R7 <<= R6;
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R6 <<= R6;
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CHECKREG r0, 0x02000000;
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CHECKREG r1, 0x78000000;
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CHECKREG r2, 0x90000000;
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CHECKREG r3, 0x9A000000;
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CHECKREG r4, 0xAB000000;
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CHECKREG r5, 0xBC000000;
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CHECKREG r6, 0x18000000;
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CHECKREG r7, 0xDE000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x82345678;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0x00000000;
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R7.L = -24;
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R0 <<= R7;
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R1 <<= R7;
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R2 <<= R7;
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R3 <<= R7;
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R4 <<= R7;
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R5 <<= R7;
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R6 <<= R7;
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R7 <<= R7;
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CHECKREG r0, 0x00;
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CHECKREG r1, 0x00;
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CHECKREG r2, 0x00;
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CHECKREG r3, 0x00;
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CHECKREG r4, 0x00;
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CHECKREG r5, 0x00;
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CHECKREG r6, 0x00;
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CHECKREG r7, 0x00;
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pass
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